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* ec: change usage of dummySam Hurst2020-08-051-3/+3
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* Make wait_for_ready available for allDaisuke Nojiri2020-07-281-14/+4
| | | | | | | | | | | | | | | | | | | wait_for_ready is a generic function which loops until bits in a register are set. This patch move it to util.c to make it available for all. There are more places where the function is applicable but this CL keeps the scope under chip/stm32/clock-stm32. There is no functionality change. BUG=none BRANCH=none TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I796599344c1d86ab7144d1d6b434ec54cf1cc55d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2317887 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Keyboard: Allow keyboard size to be set at run timeDaisuke Nojiri2018-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Currently, the keyboard size (i.e. number of columns) is static. This patch allows it to be configured at run time. It's required to support a keyboard with/without keypad in a single image. KEYBOARD_COLS_MAX has the build time col size. It's used to allocate exact spaces for arrays. Actual keyboard scanning is done using keyboard_cols, which holds a runtime col size. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:117126568 BRANCH=none TEST=Verify keyboard functionality on Sona and Veyron. Change-Id: I4b3552be0b4b315c3fe5a6884cf25e10aba8be7c Reviewed-on: https://chromium-review.googlesource.com/1285292 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f4: clock stm32f412 at 96MHzWei-Ning Huang2017-06-211-0/+5
| | | | | | | | | | | | | | | | | | | | | | On stm32f412, AHB prescaler must be 1 in order for stm32f412 to be clocked at greater than 50MHz. APBX prescaler must be 2 so the clocks can be in the right range. When APBX prescaler != 1, it results in 2x timer clocks on both APB1 and APB2. We added a new clock_get_timer_freq() function for stm32 to get timer specific clock frequency so we can return 2x timer clocks when APBX != 1. Flash latencies also need to be changed when we clock at 96MHz, the FLASH_ACR_LATENCY defines are moved into the variant-specific switches so each board can defined latency when setting CPU clocks. BUG=b:38077127 TEST=`make BOARD=rose -j`, touch performance improved by 2x. Change-Id: Ieb211ad80c168d3f57e72a8d16b954b703ee1444 Reviewed-on: https://chromium-review.googlesource.com/539375 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-241-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: Add delay after enabling peripheral clockVic Yang2015-02-101-0/+13
| | | | | | | | | | | | | | | | | We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* clock-stm32l: properly setting HSI/MSI clock based on the RMYen Lin2014-12-171-7/+45
| | | | | | | | | | | | | | | | | | | | | | | According the STM32L RM, when writing to RCC_CFGR to change HSI or MSI clock source, SWS bits of RCC_CFGR register have to be checked if the new clock source is taken into account. Also, when writing ACC64 bit and LATENCY bit to FLASH_ACR register, those bits have to be checked too. Also changed in this CL is to disable MSI if HSI is enabled, and disable HSI if MSI is enabled. BUG=chrome-os-partner:32936 BRANCH=none TEST=passed suspend_stress_test on big, blaze and nyan Change-Id: I3ec660d149ecdec3ca3097239612bf2c542d0548 Signed-off-by: Yen Lin <yelin@nvidia.com> Reviewed-on: https://chromium-review.googlesource.com/234490 Reviewed-by: Kary Jin <karyj@nvidia.com> Tested-by: Kary Jin <karyj@nvidia.com> Reviewed-by: Andrew Bresticker <abrestic@chromium.org> (cherry picked from commit 400d9dca8c41f74cf0c2587e881707b80bb17d3d) Reviewed-on: https://chromium-review.googlesource.com/236050
* Add cprints() and ccprints()Vic Yang2014-05-211-5/+5
| | | | | | | | | | | | | | | | | | | | | Our code base contains a lot of debug messages in this pattern: CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n") The strings are taking up spaces in the EC binaries, so let's refactor this by adding cprints() and ccprints(). cprints() is just like cprintf(), except that it adds the brackets and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...) This saves us hundreds of bytes in EC binaries. BUG=chromium:374575 TEST=Build and check flash size BRANCH=None Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200490 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32l: supports fake-hibernateLouis Yung-Chieh Lo2014-03-061-0/+119
| | | | | | | | | | | | | | | | | | We don't have available GPIO pin for power button as the hibernate (stand-by) wake-up source. Also, we don't want to do board change. So, put the EC in a decent infinite loop to pretend the hibernate mode and wait for particular wake-up event. This should be fine because the AP is already down before EC hibernates. BUG=chrome-os-partner:25435 BRANCH=Nyan TEST=see comment #6 of issue for detailed test steps. Change-Id: I2cae131789f9ca5808b60d5f2495222ca9016e7c Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186061 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: Flush UART buffer before changing EC core clock speedRandall Spangler2013-11-191-1/+7
| | | | | | | | | | | | | | | | | Otherwise UART output gets garbled because there's a delay between changing core clock and the UART divider. Fortunately, the glitch is cosmetic and doesn't affect proper EC operation. BUG=chrome-os-partner:23982 BRANCH=none TEST=power on, power off on pit or nyan --> no UART glitch Change-Id: I32bef119b850a340fc616b83a4b088b20f17267f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177087 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Tested-by: Yung-chieh Lo <yjlou@chromium.org> Commit-Queue: Yung-chieh Lo <yjlou@chromium.org>
* lm4: Add a low power idle task.stabilize-4825.BAlec Berg2013-10-151-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First implementation of a low power idle task for the LM4 chip. The low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a board.h file. This commit turns it on for Peppy, Slippy, and Falco only because those are the only boards tested. When using the low power idle task, the chip goes in to deep sleep when it can. Deep sleep disables clocks to most peripherals and puts the onboard flash and RAM into a low power mode. The chip is woken out of deep sleep using the RTC in the hibernate module. Increased the idle task stack size to handle more involved idle task. In board.c, the array of GPIO info can be used to select which GPIO points can wake up the EC from deep sleep. Currenlty selected are the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5. Additionally the port with the KB scan row GPIO point is also enabled to wake up the EC from deep sleep. Signed-off-by: Alec Berg <alecaberg@chromium.org> BUG=None BRANCH=none TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no noticeable side affects. Verified that the power consumed by the EC is lower when in S3, S5 and G3 by scoping the sense resistor powering the chip. Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726 Reviewed-on: https://chromium-review.googlesource.com/172183 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* STM32L ADC driverVic Yang2013-09-051-3/+20
| | | | | | | | | | | | | | | | | | | | ADC module on STM32L is clocked by HSI oscillator, and thus we need to switch to HSI if using MSI. After the conversion, if the system is not in S0, clock is switched back to MSI again. There are several register bits that can only be written when ADC is powered down. For now, let's just power down the ADC after each conversion. Currently ADC watchdog is not working and is disabled on STM32L. BUG=chrome-os-partner:22242 TEST=Try multiple all-channel and single-channel reads in S0 and S5. BRANCH=None Change-Id: I769dda8a9c69ac9de1eb22d6d259034eef8c1ac4 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167454
* stm32l: Add a "PRE_FREQ_CHANGE" hook to allow other code to prepareDoug Anderson2013-08-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this change drivers had no way of knowing that a frequency change was coming. This could cause problems for some drivers (like i2c) that need to make sure that a transaction isn't happening while a frequency change is happening. The PRE_FREQ_CHANGE archiecture is very simple here and we don't allow any way to cancel it. At the moment, we guarantee: - We won't call PRE_FREQ_CHANGE with interrupts disabled, so acquiring locks / sleeping is OK. - We'll call the actual HOOK_FREQ_CHANGE after the PRE_FREQ_CHANGE. PRE_FREQ_CHANGE and HOOK_FREQ_CHANGE should not use deferred function calls. BRANCH=pit BUG=chrome-os-partner:22093 TEST=With all patches together: - on AP: suspend_stress_test - on EC: battery 10000 50 Change-Id: I2731a3e85d41e749fa571fdb74b5c9b12043cda6 Signed-off-by: Doug Anderson <dianders@chromium.org> Previous-Reviewed-on: https://chromium-review.googlesource.com/167101 (cherry picked from commit d84c0dbbf7c5a72917a820e292ecfdfa698d0fb9) Reviewed-on: https://chromium-review.googlesource.com/167148 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Clean up more config options - FMAP, etc.Randall Spangler2013-07-241-20/+1
| | | | | | | | | | | | | | | | CONFIG_FMAP is now defined by default, because all platforms other than the host unit tests use it. No functional changes, just renaming config options and removing dead code. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms Change-Id: Ie6496310c822491068e2fa6976933486f26badb0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63271 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32: Add CHIP_FAMILY definesRandall Spangler2013-07-011-0/+210
Previously, code which needed to work on all STM32F platforms needed to specify them by name (CHIP_VARIANT_stm32f100 || CHIP_VARIANT_stm32f10x), and we needed extra symlinks in the chip/stm32/ directory to allow the build system to find family-specific files. Add a CHIP_FAMILY level of abstraction, so that things which are common across all STM32F platforms don't need to specify every STM32F variant. Make the chip build look for family-specific filenames instead of variant-specific filenames (except for config*.h, which is actually variant specific). In the few places where things actually are variant-specific, keep using the existing CHIP_VARIANT defines. Code refactoring only; no functional changes. BUG=chrome-os-partner:20567 BRANCH=none TEST=build all platforms Change-Id: I1da831aadabf8b8dd9dfde423cac13c9f43eb953 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60247 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
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