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* chip/stm32/gpio.c: Format with clang-formatJack Rosenthal2022-06-301-7/+8
| | | | | | | | | | | BUG=b:236386294 BRANCH=none TEST=none Change-Id: I39775a445c62c2ffd82b54a3b4b391abf0a8b678 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729509 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* tree: Make DECLARE_IRQ routine staticTom Hughes2021-11-081-3/+7
| | | | | | | | | | | | | For consistency, make all IRQ handler routines static. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I43dc4dd0a8cd593d6eb761768acc5c7b6b95e22b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3227265 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32: Fix manual interrupt clearing functionCraig Hesling2020-03-121-1/+3
| | | | | | | | | | | | | | | | | | | This fixes a bug in gpio_clear_pending_interrupt, where all pending interrupts are unintentionally cleared. This is not in the code path for normal gpio interrupt handlers, since the normal interrupt clearing occurs in gpio_interrupt (right below this function). BRANCH=none BUG=chromium:1059520 TEST=none Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4d6fe7947f4d76cf3b57dfbf3bb926e41851c80c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2101208 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32f4: Implement UNUSED pinsCraig Hesling2019-11-081-0/+14
| | | | | | | | | | | | | | | | | | | | | | This CL adds support for UNUSED pins to the STM32F4 family of chips. This places the unused/unconnected pins in the lowest power state. In this case, ST recommends that you configure the pin as analog-in to disable the schmitt trigger logic. This codified the work done in crrev.com/c/1883127 . The CL should have no functional change for boards that have not specified UNUSED pins in their gpio.inc. BRANCH=nocturne,hatch BUG=b:130561737 TEST=make buildall -j Change-Id: I444b868b277b016a896e410dccae84429b68839e Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894242 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip/stm32/gpio: Disable external interrupts in gpio_pre_initNicolas Boichat2019-06-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | After a sysjump, external interrupts are left enabled. However, exti_events is reset to 0, so upon receiving an interrupt, gpio_interrupt will call the handler for signal 0 (the first GPIO_INT defined in gpio.inc) for these sources. This is obviously very wrong, and the easiest (and most robust) way to fix this is to disable all interrupts on sysjump, and let the new code re-enable if desired. BRANCH=none BUG=chromium:977950 TEST=On kukui, with following CL, trigger a watchdog (stop daisydog; echo > /dev/watchdog), see that no interrupt is generated. Change-Id: Ic55262f8b8dd9d154619cb0620e1889b3da3feec Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1673950 Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kukui/emmc: Share EXTI15 interrupt between SPI and eMMCNicolas Boichat2018-10-301-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | We never need to have interrupts enabled on both SPI1_NSS and EMMC_CMD, so we can actually share the interrupt selection EXTI15 between the 2 pins. This frees up PA14 (and EXTI14) for future interrupt needs. To make sure that we can answer host commands as soon as the AP as booted, we quickly poll for the eMMC bootblock switch to turn away from EC, and switch interrupt from eMMC to SPI. Also, we clear exit_events in chip/stm32/gpio.c, so that we do not report a override warning if we disable then re-enable another interrupt on the same EXTI. BRANCH=none BUG=b:113370127 TEST=Boot kukui rev1, check that EC commands works after boot Change-Id: Ib1f0a56a9f37e1bda01dc4e6b55734196bb3ff50 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1195345 Reviewed-by: Yilun Lin <yllin@chromium.org>
* stm32: Add STM32H7 familyVincent Palatin2018-01-081-0/+4
| | | | | | | | | | | | | | | | | | Start adding support for the STM32H7 family of device and the first available one the STM32H743. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=manual, run on stm32h743i-eval and zerblebarn boards get a stable serial console. Change-Id: I9ae10f0d843e5318451713c21ed22d455a23758c Reviewed-on: https://chromium-review.googlesource.com/806168 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: gpio: implement gpio_disable_interruptWei-Ning Huang2017-07-171-0/+13
| | | | | | | | | | | | | | | | gpio_disable_interrupt is missing for stm32, add it so board functions can use it. BRANCH=none BUG=b:63685022 TEST=`make BOARD=rose -j` Change-Id: Ibbdd8506540e7949fa110c26131dca028671be06 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/573981 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* gpio: Add function to clear pending interruptDuncan Laurie2017-03-011-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently if an interrupt is pending before it is enabled the interrupt will fire immediately. In most cases this is fine, but if we want to use the interrupt to trigger something like waking the AP it should be sure that it won't immediately fire once enabled. For example: on the Eve board we have the trackpad interrupt run to the AP and the EC in order to support wake from Deep S3 (magic AP state that only the EC can wake it from). This interrupt is used in S0 by the AP while ignored by the EC, and then enabled on the transition to S3 in order to be able to wake. Since it has been active the interrupt may be pending in the EC (depending on the chip), which can result in the interrupt firing immediately and waking the AP. BUG=chrome-os-partner:62224 BRANCH=none TEST=This has been functionally tested on npcx only as that is what I have a use case and system for, the others compile and look right but have not been directly tested. Change-Id: I9e0877d99e7f09f4c30bf9861fbad81c12c059ad Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/446962 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f0: Allow change of external int prioritiesDaisuke Nojiri2016-11-091-3/+3
| | | | | | | | | | | | | | This change allows each board to customize external interrupt priorities. BUG=none BRANCH=none TEST=make buildall Change-Id: I5941f368ea70a069b34ce1d98508a1fad1ac22da Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/408796 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f446e-eval: add support for stm32f446Nick Sanders2016-08-171-1/+1
| | | | | | | | | | | | | | | | | | This adds basic support for the stm32f446. This consists of: * New DMA model for stm32f4 * New clock domain support. * MCO oscillator gpio export support. * Flash support for irregular blocks. BUG=chromium:608039 TEST=boots w/ correct clock, stm32f0 also boots. BRANCH=None Change-Id: I1c5cf6ddca09009c9dac60da8a3d0c5ceedfcf4d Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363992 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* GPIO: Move STM32 specific gpio_enabled_clocksAnton Staaf2016-03-021-1/+1
| | | | | | | | | | | | | | | | | | | | This function should not be part of the public GPIO API. It is only available and used in the STM32 implementation. This moves the prototype to a chip specific gpio.h that is used within the STM32 chip directoy. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Manually verify GPIO functionality on discovery board Change-Id: If9c97f8038b26815318652ca62c1132c95519fa2 Reviewed-on: https://chromium-review.googlesource.com/329968 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* GPIO: Remove gpio_get_level_reg functionAnton Staaf2016-01-271-6/+0
| | | | | | | | | | | | | | | | | | | | After talking with Simon Glass about this we concluded that this was an optimization that is not needed, as such, and since it is only used in one location and only available from one chip family I'm removing it. This further simplifies the GPIO API and removes more uses of port/mask pairs. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I40754a385e0a4fa3a56d67fca1dd59fc8f3cc85a Reviewed-on: https://chromium-review.googlesource.com/323827 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Rename gpio_is_reboot_warm() to system_is_reboot_warm()Vijay Hiremath2015-09-291-1/+2
| | | | | | | | | | | | | BUG=chrome-os-partner:40788 TEST=make buildall -j BRANCH=none Change-Id: I4fb248da4656374e1218af98678cfb694f4c9176 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/302674 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: GPIO: Use common macro for converting mask to GPIOShawn Nematbakhsh2015-07-191-1/+1
| | | | | | | | | | | | | | The same calculation is used across the code, so move it to a common macro. BUG=chrome-os-partner:42104 TEST=Verify Glados still boots AP. BRANCH=None Change-Id: I90da348f37fc670971737cfc5ddcfb9c34096c4b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/286169 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* STM32F: Remove support for this familyAnton Staaf2015-06-301-10/+1
| | | | | | | | | | | | | | | | | | There are no boards left that use this family of STM32 parts. If we add one later we can resurect support. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: If985a9e9f93c935e98c93f33c075ce00cb9a91ac Reviewed-on: https://chromium-review.googlesource.com/282532 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* Add option to enable GCC LTOVincent Palatin2015-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the flash footprint of the firmware. Add additional protection to some functions/data to avoid removal by the linker when their usage is not obvious. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall (with and without LTO enable on all boards) Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059 Reviewed-on: https://chromium-review.googlesource.com/271291 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* gpio: Refactor IRQ handler pointer out of gpio_listAseda Aboagye2015-04-101-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the gpio_info struct, we had a irq_handler pointer defined even though a majority of the GPIOs did not have irq handlers associated. By removing the irq_handler pointer out of the struct, we can save some space with some targets saving more than others. (For example, ~260 bytes for samus_pd). This change also brings about a new define: GPIO_INT(name, port, pin, flags, signal) And the existing GPIO macro has had the signal parameter removed since they were just NULL. GPIO(name, port, pin, flags) In each of the gpio.inc files, all the GPIOs with irq handlers must be defined at the top of the file. This is because their enum values from gpio_signal are used as the index to the gpio_irq_handlers table. BUG=chromium:471331 BRANCH=none TEST=Flashed ec to samus and samus_pd, verified lightbar tap, lid, power button, keyboard, charging, all still working. TEST=Moved a GPIO_INT declaration after a GPIO declaration and watched the build fail. TEST=make -j BOARD=peppy tests TEST=make -j BOARD=auron tests TEST=make -j BOARD=link tests Change-Id: Id6e261b0a3cd63223ca92f2e96a80c95e85cdefb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/263973 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cortex-m0: Add deferred schedulerAlexandru M Stan2015-02-121-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If 2 interrupts happen at the same time, there is a chance that the nested interrupt will not call svc_handler when it needs to. In extreme cases this could lead to tasks not getting woken up when they're supposed to and watchdog resetting. The reason stuff worked was because there were enough other interrupts around to eventually call the scheduler and switch to the ready task. This change modifies the interrupt calls to not call the scheduler directly (because in nested interrupt situation this causes problems), but defer the call to scheduling until after the irq finishes by triggering a low priority interrupt which will for sure call svc_host at the end. The PendSV irq was used for this purpose. BUG=chrome-os-partner:36193 TEST=No more SPI errors caused by scheduler problems TEST=usleeps now are more accurate, they're guaranteed to not take forever now BRANCH=veyron Change-Id: I42acde6b3eb7be2540a0de9a8562dee2ea2be7ab Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/248902 Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* stm32: Add delay after enabling peripheral clockVic Yang2015-02-101-0/+4
| | | | | | | | | | | | | | | | | We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* Add support for STM32F373Vic Yang2014-10-071-1/+2
| | | | | | | | | | | | | | | | | | | This mostly reuses chip drivers for STM32F and STM32F0. Since this chip doesn't fit either STM32F or STM32F0, let's use symlink to specify which drivers to use for STM32F3. This is just the preparatory work and it's not verified on a chip yet. BUG=chrome-os-partner:32660 TEST=make buildall to make sure this doesn't break anything BRANCH=None Change-Id: I709ed49265e8f84552251a97d03b9b98496de99e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221412 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32/gpio: Supress overriding interrupt warning in some casesAlexandru M Stan2014-09-241-1/+1
| | | | | | | | | | | | | | | | | | | The warning should only warn if there's an actual danger(in order to give a clue to developers that something might be amiss). Messages like "Overriding SPI1_NSS with SPI1_NSS on EXTI4" are just spammy. This patch makes it so it only warns if the interrupt is different. BUG=chrome-os-partner:31390 TEST=spam gpio_enable_interrupt(GPIO_SPI1_NSS); in a bunch of places (like spi_event), it should not complain about the interrupt being set to the same thing before. Whereas before it was so spammy it did not even have time to reply to SPI. BRANCH=None Change-Id: I786a821eb8167e3568d0be371c4de26bb124431a Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218563 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* GPIO: Reduce code duplication in STM32 gpio driverAnton Staaf2014-07-171-0/+125
| | | | | | | | | | | | | | | | | | | | Previously the F0 and L variants had almost identical driver files and the F variant shared about half of its driver. This refactor moves the shared code into gpio.c and gpio-f0-l.c, the latter is for code shared between the F0 and L variants. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=none TEST=make buildall -j Followed by manual testing of interrupt on change and UART functionality on STM32F0 based discovery board. Change-Id: I920babd1861548272af2857c8bd3e4f9dac4985c Reviewed-on: https://chromium-review.googlesource.com/207986 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* Move gpio_get_name() to gpio_common.cRandall Spangler2013-04-111-15/+0
| | | | | | | | | | | | | | | Its implementation is the same on all platforms. No functional changes, just renaming/moving. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms Change-Id: I78741c6587ea61e7ac8edae5a509502b7ab5078b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/47898 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Clean up GPIO module.Randall Spangler2012-10-301-1/+0
| | | | | | | | | | | | No functional changes, just code cleanup. BUG=chrome-os-partner:15579 BRANCH=none TEST=gpioget returns reasonable values Change-Id: I4301ccc68ade775f78f4ccd84710d2cd4bc25252 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36800
* Clean up GPIO moduleRandall Spangler2012-10-251-1/+1
| | | | | | | | | | | | | Just code cleanup; no functional changes BUG=chrome-os-partner:15579 BRANCH=none TEST=build code; boot link; gpioget still works Change-Id: If0770c1a5ce0d5c51ba528fbe2944a73fafa949b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36556 Reviewed-by: Simon Glass <sjg@chromium.org>
* stm32: Add a generic gpio librarySimon Glass2012-05-101-0/+16
| | | | | | | | | | | | | | Much of the code in gpio-stmxxx.c is duplicated. Also the gpio_get_name() function is not present in the new file. Create a common gpio.c file to hold this function, and hopefully other code in the future. BUG=none TEST=build on all platforms, boot on daisy Change-Id: I4ab33e0e5c52843b770fabc777c917493abccffe Signed-off-by: Simon Glass <sjg@chromium.org>
* introducing chip variant for stm32 family [3/3]Vincent Palatin2012-05-011-199/+0
| | | | | | | | | | | | | Add STM32F support. Based on David's changelist. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: Ide817d11480f0b56f67deaae3c08bc631f605075
* introducing chip variant for stm32 family [1/3]Vincent Palatin2012-05-011-0/+199
just rename STM32L to STM32. Most of the STM32L15x code is common with STM32F1xx. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: I819eff5fcd23deff57f5f6dedcf37e6c421b96c2
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