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* stm32/hwtimer: Fix CONFIG_WATCHDOG_HELP #endif commentCraig Hesling2020-02-041-1/+1
| | | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: Ic9a2f35f06e5e0a8a1fe85eb5959781310f7d430 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2037093 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip: stm32: Fix Timers 9 through 11 for STM32F4Moritz Fischer2019-03-161-1/+1
| | | | | | | | | | | | | | | | | | The timers 9 through 11 have different enable bits in the STM32_RCC_APB2ENR on STM32F446/411/412 targets versus the default (used by STM32F4/L4/STM32L) value set. Break out the CHIP_FAMILY_STM32F4 case separately. BRANCH=none BUG=none TEST=Observe PWM output on STM32412 EVM vs none before Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Change-Id: I9f00902afe58ef8ef141da39b2b912ecc592944b Reviewed-on: https://chromium-review.googlesource.com/1493273 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* watchdog: Don't discard irqprio data due to CONFIG_LTOShawn Nematbakhsh2017-06-261-1/+1
| | | | | | | | | | | | | | | | | | | | | Don't discard irqprio data when the IRQ_PRIORITY macro is used directly (for watchdog / watchdog timer). This change is probably a NOP for all platforms, since the power-on default for the IRQ prio register seems to be zero, which is the same priority we're setting in our direct use of IRQ_PRIORITY. BUG=chromium:634701 BRANCH=None TEST=Verify 'prio_44' entry exists in irqprio section by checking ec.RO.map on kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idaffc484a2ce4749c18212f179b3951ff570aed0 Reviewed-on: https://chromium-review.googlesource.com/545201 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f4: clock stm32f412 at 96MHzWei-Ning Huang2017-06-211-1/+2
| | | | | | | | | | | | | | | | | | | | | | On stm32f412, AHB prescaler must be 1 in order for stm32f412 to be clocked at greater than 50MHz. APBX prescaler must be 2 so the clocks can be in the right range. When APBX prescaler != 1, it results in 2x timer clocks on both APB1 and APB2. We added a new clock_get_timer_freq() function for stm32 to get timer specific clock frequency so we can return 2x timer clocks when APBX != 1. Flash latencies also need to be changed when we clock at 96MHz, the FLASH_ACR_LATENCY defines are moved into the variant-specific switches so each board can defined latency when setting CPU clocks. BUG=b:38077127 TEST=`make BOARD=rose -j`, touch performance improved by 2x. Change-Id: Ieb211ad80c168d3f57e72a8d16b954b703ee1444 Reviewed-on: https://chromium-review.googlesource.com/539375 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* stm32: hwtimer: Use correct TIM1 interruptShawn Nematbakhsh2015-11-191-4/+4
| | | | | | | | | | | | | | | | | | Our system timer uses capture compare mode, so the TIM1_CC interrupt should be used. BUG=chrome-os-partner:47851 TEST=Set TIM_CLOCK_LSB to 1 on snoball (TIM1), verify that timer interrupts function, HOOK_SECOND hooks are called and watchdog doesn't fire. BRANCH=None Change-Id: Id5cc18d0cd216b5b448e11cf0bae9696db74eb02 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313188 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* STM32F: Remove support for this familyAnton Staaf2015-06-301-1/+1
| | | | | | | | | | | | | | | | | | There are no boards left that use this family of STM32 parts. If we add one later we can resurect support. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: If985a9e9f93c935e98c93f33c075ce00cb9a91ac Reviewed-on: https://chromium-review.googlesource.com/282532 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* Add option to enable GCC LTOVincent Palatin2015-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the flash footprint of the firmware. Add additional protection to some functions/data to avoid removal by the linker when their usage is not obvious. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall (with and without LTO enable on all boards) Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059 Reviewed-on: https://chromium-review.googlesource.com/271291 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* hwtimer/hwtimer32: Remove task_resched_if_needed from watchdog helpAlexandru M Stan2015-02-181-4/+2
| | | | | | | | | | | | | | | | | | | | | Remove task_resched_if_needed, since we don't do any task scheduling modifications. Just return instead. This makes it work on F0 as well, where we don't have task_resched_if_needed BUG=None TEST=With series, see watchdog help work on any veyron BRANCH=veyron Change-Id: I93cce722b6d53008b015c7cdd56b7e77dc07bbff Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/242713 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> (cherry picked from commit 8363dfb14cb36fca412132ab14d2c9451de7d94e) Reviewed-on: https://chromium-review.googlesource.com/250671 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* stm32: Add delay after enabling peripheral clockVic Yang2015-02-101-0/+6
| | | | | | | | | | | | | | | | | We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* Add support for STM32F373Vic Yang2014-10-071-1/+56
| | | | | | | | | | | | | | | | | | | This mostly reuses chip drivers for STM32F and STM32F0. Since this chip doesn't fit either STM32F or STM32F0, let's use symlink to specify which drivers to use for STM32F3. This is just the preparatory work and it's not verified on a chip yet. BUG=chrome-os-partner:32660 TEST=make buildall to make sure this doesn't break anything BRANCH=None Change-Id: I709ed49265e8f84552251a97d03b9b98496de99e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221412 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* watchdog: Help ensure that the stm32 watchdog help printsDoug Anderson2014-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | On stm32 we were programming the WATCHDOG_HELP timer with the same value as the independent watchdog (which automatically resets the CPU). That means we weren't guaranteed to see the WATCHDOG_HELP. It happened to work most of the time due to the the LSI oscillator fudge (we assumed the watchdog was on a 56 kHz oscillator when it was probably on a 38 kHz one), but let's give ourselves a guaranteed gap. It's unlikely that this extra gap will actually help on most machines (if we're running at 53 kHz or lower we already had this much margin), but it's nice to be safe. BRANCH=ToT BUG=chrome-os-partner:29162 TEST=Increase margin to 400 (instead of 50) and type "waitms 300". Sometimes hit watchdog warning. Change-Id: I7f876757c15d7775116720c408a4127b4b94adfa Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204894 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* zinger: fix bug, increase watchdog timeout to 1.8sAlec Berg2014-06-201-1/+1
| | | | | | | | | | | | | | | | | Fix bug and actually increase watchdog timeout to 1.8s. BUG=none BRANCH=none TEST=put a 3 second blocking delay in pd_task and make sure watchdog reboots. set blocking delay to 1.5seconds and make sure no reboot. Change-Id: Ie66621a3bd98354f9fd22b9b10a866d004277340 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204471 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add support for STM32F0xx familyVincent Palatin2014-03-111-2/+45
| | | | | | | | | | | | | | | | | | Add support for the STM32F0xx family of devices using a Cortex-M0 core and slightly newer peripherals than F1xx family. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run EC console on STM32F072B Discovery board. and pass all available unit-tests on target. Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735 Reviewed-on: https://chromium-review.googlesource.com/188983 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* force the compiler to use a valid register allocation for irq handlersVincent Palatin2014-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Rename mixed-case config constantsRandall Spangler2013-12-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This renames constants used in compiler conditionals to uppercase. BOARD_foo CHIP_foo CHIP_FAMILY_foo CHIP_VARIANT_foo CORE_foo Mixed-case constants are still defined by the makefile, but are now no longer used. I will make one more pass in a week or so to catch any that are part of someone else's CL, since otherwise this change might silently merge correctly but result in incorrect compilation. Then I will remove defining the mixed-case constants. BUG=chromium:322144 BRANCH=none TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no results (similarly for CHIP, CORE, etc.) Change-Id: I6418412e9f7ec604a35c2d426d12475dd83e7076 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179206 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Standardize concatenation macrosRandall Spangler2013-07-241-5/+5
| | | | | | | | | | | | | | | | | | To create a token by concatenating already-defined macros and new text, it's necessary to use multiple levels of macro. We'd already done that in several places in the code such as STM32_CAT; this now standardizes it into a single place. BUG=chrome-os-partner:18343 BRANCH=none TEST=Build all platforms; examine ec.RO.map to see that irq_*_handler and prio_* symbols evaluated the same as before. (Other macro evaluations would simply fail to compile if they were incorrect, since the concatenated tokens wouldn't fully expand.) Change-Id: Ic9bf11d27881a84507fe7b6096dab6217c6c6dc7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63231 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Clean up JTAG registersChromeOS Developer2013-07-081-3/+7
| | | | | | | | | | | | No functional changes, just cleanup. BUG=chrome-os-partner:20529 BRANCH=none TEST=boot pit Change-Id: I2067dffc3b1335f001a95e63b22213a1022f3ae8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61095
* stm32: Add CHIP_FAMILY definesRandall Spangler2013-07-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, code which needed to work on all STM32F platforms needed to specify them by name (CHIP_VARIANT_stm32f100 || CHIP_VARIANT_stm32f10x), and we needed extra symlinks in the chip/stm32/ directory to allow the build system to find family-specific files. Add a CHIP_FAMILY level of abstraction, so that things which are common across all STM32F platforms don't need to specify every STM32F variant. Make the chip build look for family-specific filenames instead of variant-specific filenames (except for config*.h, which is actually variant specific). In the few places where things actually are variant-specific, keep using the existing CHIP_VARIANT defines. Code refactoring only; no functional changes. BUG=chrome-os-partner:20567 BRANCH=none TEST=build all platforms Change-Id: I1da831aadabf8b8dd9dfde423cac13c9f43eb953 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60247 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* pit: Clean up timer init codeRandall Spangler2013-06-261-10/+31
| | | | | | | | | | | | Power LED PWM now uses the same functions as the hardware timer. BUG=chrome-os-partner:20414 BRANCH=none TEST=Suspend system. Power button LED pulses smoothly still. Change-Id: Ib5ca6655d815462baaf68600ad14c4c0c680a6af Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59838
* pit: Support changing EC clock frequencyRandall Spangler2013-06-251-11/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modules which care about system clock frequency now hook HOOK_FREQ_CHANGE. - hwtimer - i2c - uart (which is now also smart enough to use x8 oversampling instead of x16 when the system clock is too slow to support x16) Added 'clock' debug command to set system clock frequency. STM32F platforms don't change clock frequency; on those platforms, clock_get_freq() simply returns CPU_CLOCK, so behavior of those platforms is unchanged. BUG=chrome-os-partner:20414 BRANCH=none TEST=from EC console: - reboot ap-off -> to make sure AP is off during testing - clock msi2 -> reports 2MHz clock - battery -> reports battery info - clock msi1 -> reports 1MHz clock - battery -> reports battery info - clock hsi -> reports 16MHz clock - battery -> reports battery info - power on -> AP powers on and host commands succeed Change-Id: Ib8276bf124727e4fb502297ca8b3d6d4b6170241 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59645
* pit: Fix watchdog help for STM32LRandall Spangler2013-06-241-31/+72
| | | | | | | | | | | | | | | | | Clean up timer initialization code to be more general, so that we can use timer 9 for the LSB on STM32L. Then use timer 4 for the watchdog helper. BUG=chrome-os-partner:18781 BRANCH=none TEST=From EC console: timerinfo -> current time still counts up properly waitms 2000 -> prints watchdog info before rebooting Change-Id: Ib0ba496b0eadb93756dcd1841857546910baf2a9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59612 Reviewed-by: Simon Glass <sjg@chromium.org>
* Define watchdog_reload() to nothing if not CONFIG_WATCHDOGRandall Spangler2013-06-101-2/+3
| | | | | | | | | | | | | | | | | | | Currently, we need to have #ifdefs everywhere watchdog_reload() is called. With this fix we don't. Also don't bother including unused hardware timer watchdog code if the watchdog isn't defined. No change when CONFIG_WATCHDOG is defined (which it is for all normal builds). BUG=chrome-os-partner:20056 BRANCH=none TEST=build all platforms with CONFIG_WATCHDOG commented out in config.h Change-Id: Id3ce33af1a497eda127a4892e13651d9d2534d92 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58094 Reviewed-by: Simon Glass <sjg@chromium.org>
* stm32f10x: Initial importDavid Hendricks2013-03-081-3/+1
| | | | | | | | | | | | | | | | | | | | | This adds initial support for the other chips in the stm32f10x series: stm32f101, stm32f102x, stm32f103x, stm32f105x, stm32f107x. The main difference is in the register definitions. Clock, flash, GPIO, and JTAG modules are similar enough that for now we can symlink the existing source for stm32f100. BRANCH=none BUG=none TEST=Tested on McCroskey (follow-up CL) Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I67363d02578e21be51d842b6bd8b5e4848720993 Reviewed-on: https://gerrit.chromium.org/gerrit/43412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org>
* stm32: Add option to select timer for hardware clockVic Yang2012-12-121-60/+76
| | | | | | | | | | | | | | Hardware clock uses two timers, currently TIM3 and TIM4. This CL adds an option to select between TIM2, TIM3, and TIM4, so that we can use any one the three timer as a PWM source. BUG=chrome-os-partner:14319, chrome-os-partner:7463 TEST=Build and run on snow/spring. Build success on daisy. BRANCH=none Change-Id: I1a00b3d491ee3e131708b573f6ea70e6b56c96dd Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/39584
* Use SECOND and MSEC constantsRandall Spangler2012-10-291-25/+19
| | | | | | | | | | | | | | | | | | We'd defined them in a number of different files. This moves definitions to timer.h, and uses them everywhere we have large delays (since 10*SECOND is less typo-prone than 10000000). Also add msleep() and sleep() inline functions. No need for mdelay() or delay(), since any delays that long should use sleep funcs instead of spin-waiting. BUG=chrome-os-partner:15579 BRANCH=none TEST=boot system; taskinfo displays similar numbers to before Change-Id: I2a92a9f10f46b6b7b6571759b1f8ab4ecfbf8259 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36726
* stm32: fix missed event on MSB hardware timerVincent Palatin2012-08-231-10/+23
| | | | | | | | | | | | | | | | | | | | | | | | When we set the TIM3 hardware timer match interrupt (used for 16-bit MSB of the 32-bit microsecond counter), as the STM32 hardware block is not triggering an interrupt on an exact match (only on the transition from N-1 to match value N), we need to check whether the counter has been incremented to the match value before we set the interrupt enable bit. In that case, we simply fallback to the existing code to set the LSB match interrupt. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:12715 TEST=use Snow board and see we are no longer getting EC watchdog in the idle task. BRANCH=snow Change-Id: I4ceeb46425c799e328603ae0e99b678547d88fbe Reviewed-on: https://gerrit.chromium.org/gerrit/31228 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* add a function to fast forward system timerVincent Palatin2012-08-061-2/+7
| | | | | | | | | | | | | | | | | | | When we wake up from a deep sleep mode, the system timer clock might have been stopped. We need to be able to set using another time source (e.g. the RTC). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8866 TEST=make BOARD=snow && make BOARD=link on Snow, on a software implementing STOP mode, check the system time is still accurate by comparing it to the wall clock. Change-Id: Ieddbb423d052c7aceb398470866b25b25a74c0a0 Reviewed-on: https://gerrit.chromium.org/gerrit/29314 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Use a timer as the watchdog warningSimon Glass2012-07-021-0/+101
| | | | | | | | | | | | | | | | | | | | The WWDG is not ideal for this purpose, since if we fail to handle its interrupt withint 60ms or so, we get a reset. This can be a problem when we are reporting a panic, since the uart output takes a long time. Change to using timer 9, which is free, and make it print a watchdog warning after one second. BUG=chrome-os-partner:10146 TEST=manual: build and boot on snow; waitms 1200 and see that a watchdog timeout is reported correctly. See that the panic message is displayed in full without a reset happening before the end. Change-Id: Ifc3671098e1f3a7ef409b8d1fb919d22eaa90358 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26172
* stm32: force update generation during timer setupDavid Hendricks2012-07-021-2/+2
| | | | | | | | | | | | | | | | | | | This corrects a small bug where by the UG bit in EGR was not getting set, so the shadow registers were not being reloaded as the comments suggest they should be. This is really only a minor clean-up. The timer appears to work fine with or without the patch. Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=none TEST=timerinfo appears sane on Snow Change-Id: I637e2fc1f5dbfa1e70d33f96c8bf38ac57cc7b2c Reviewed-on: https://gerrit.chromium.org/gerrit/26520 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Ready: David Hendricks <dhendrix@chromium.org>
* stm32: switch 32-bit timer to use TIM3/4David Hendricks2012-06-291-42/+42
| | | | | | | | | | | | | | | | Chain TIM3/4 as the 32-bit timer instead of TIM2/3. This frees up TIM2 to be used for other purposes. BUG=chrome-os-partner:10647 TEST=Flashed onto Snow, stuff works and timerinfo output is sane Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Icdfe3596a15bc2ee8536f160b1f08ac3041b9193 Reviewed-on: https://gerrit.chromium.org/gerrit/26202 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org>
* Maintain timer value across sysjumps and clean up init debug outputRandall Spangler2012-05-111-1/+6
| | | | | | | | | | | This helps us keep track of how long vboot is taking on the EC. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9651 TEST=reboot system and look at debug log. time shouldn't start over after it jumps to image A. Change-Id: Iad86e90d42dabf1c67b2c2be80dda1151cf9a288
* introducing chip variant for stm32 family [1/3]Vincent Palatin2012-05-011-0/+142
just rename STM32L to STM32. Most of the STM32L15x code is common with STM32F1xx. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: I819eff5fcd23deff57f5f6dedcf37e6c421b96c2
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