delta/coreboot/chrome-ec.git - review.coreboot.org: chrome-ec.git

	Commit message (Collapse)	Author	Age	Files	Lines
*	stm32: use D-cache on STM32H7	Vincent Palatin	2018-06-04	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Enable the D-cache on STM32H7. Use the ahb4 RAM region as uncached memory for DMA buffers. Mark the serial, SPI and fingerprint DMA buffers as uncached for proper operations. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:78535052, b:75068419 TEST=On ZerbleBarn, run fingerprint match. CQ-DEPEND=CL:*616448 Change-Id: Ia33496ebde3508d3427e522cc7ba060829f8f3fd Reviewed-on: https://chromium-review.googlesource.com/1065822 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
*	stm32: convert to CONFIG_CHIP_MEMORY_REGIONS	Vincent Palatin	2018-03-05	1	-0/+16
	Remove the former special case for USB RAM Add additional RAM regions for STM32H7. For USB RAM, add an explicit alignment directive to ensure we always meet the 8-byte boundary hardware constraint for the BTABLE. This was already true because we put the .usb_ram.btable section first. I keep this property by alpha-sorting the sections but makes it more explicit by adding a 2-digit numeric prefix: e.g. 00_firstsection, 99_lastsection. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, along with the following CLs, run the firmware with large arrays in special AHB memory regions. TEST=build all targets with and without the patch and verify that all smap files are identical. Change-Id: I9ee7f519a13cb14ba9997220f22180028f9c0175 Reviewed-on: https://chromium-review.googlesource.com/946369 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>