| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
| |
This macro is used in many places, so let's move it to common location.
BUG=b:200828093
BRANCH=none
TEST=make -j buildall
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I55ec4f7776f494cbb976d50c91e6809c1827820f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3398913
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Introduce L5xx mostly as copy of L4xx, though registers-stm32l5.c is
extensively modified.
BUG=b:192262089
TEST=Compile and upload board/hyperdebug to Nucleo board
BRANCH=none
Signed-off-by: Jes B. Klinke <jbk@opentitan.org>
Change-Id: Iccc7b05e4f2dfa732559b8099cf856882401e31c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3086362
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
https://en.cppreference.com/w/cpp/keyword
https://en.cppreference.com/w/cpp/keyword/or
BRANCH=none
BUG=b:144959033
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I8ac62e6fbcab8fe0c842c737d183b462899bd017
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2740563
Reviewed-by: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Google is working to change its source code to use more inclusive
language. To that end, replace the term "dummy" with inclusive
alternatives.
BUG=b:162781382
BRANCH=None
TEST=make -j buildall
`grep -ir dummy *`
The only results are in "private/nordic_keyboard/sdk8.0.0"
which is not our code.
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Adds the USB SPI protocol V2, this protocol supports larger
SPI transfers that are delivered in multiple USB packets.
This enables us to perform 2 optimizations on the USB SPI
transfer speed for large USB packets:
* USB packets can be grouped together reducing the total
number of packets exchanged. The host can write multiple
data sections sequentially without the device responding
with a packet for each one. Going the other direction,
the host can continue to poll the device for data until
the transmission is complete.
* Only a single SPI transaction is required, this eliminates
overhead in setting up and getting data from SPI transactions.
Benchmark results show a typical 35% improvement in performance
on Servo Micro platforms with these changes on operations which
involve large SPI transfers reading or writing from the flash.
Signed-off-by: Brian Nemec <bnemec@chromium.org>
Blocked on upstream changes to flashrom:
Depends-On:https://review.coreboot.org/c/flashrom/+/41533
BUG=b:139058552
BRANCH=servo
TEST=Tested with Servo Micro with the reading, erase, write,
and verify operations with updated copies of flashrom.
Change-Id: I04b6cf8449e32cc1b75d3501939958887eb57f5b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224765
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Brian Nemec <bnemec@chromium.org>
Tested-by: Brian Nemec <bnemec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL adds the registers definition file for stm32g4. It was based
off the registers file for the stm32f4 chip family.
BUG=b:148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I4de8e4ed955714d35e75e0c0c5de83a3d8c4c996
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092492
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
According to programming guide, the SDA signal (200kHz) should have its
rising edge in the middle of the SCL (100kHz) transition. Since the
timers are starting at the same time, inverting the SDA timer will
achieve this.
This will affect both servo_micro and c2d2
BRANCH=servo
BUG=b:153393490
TEST=verify with scope on C2D2 is SDA/SCL signals match programming
guide
Signed-off-by: Jett Rink <jettrink@chromium.org>
Change-Id: Ibda89a30f77d39c633f491840b82f7b1dee552c5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142561
Reviewed-by: Matthew Blecker <matthewb@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add necessary console command to allow C2D2 to pass through i2c bus for
ec and ap. Also hook into common ite programming mode code.
BRANCH=servo
BUG=b:148610186,b:147381671
TEST=flash ampton with C2D2 adapter
Change-Id: I1d9b20684b45ff0d101b9cfff8b0b0a85e6c0c70
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064594
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Matthew Blecker <matthewb@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Tab over register values underneath the register definition for
consistent style.
BRANCH=none
BUG=none
TEST=none
Change-Id: I823a454fc57d4ee455c9efb693baff8838bc7d3c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2067158
Reviewed-by: Diana Z <dzigterman@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enables the programmable voltage detector (PVD) interrupt in
ServoMicro. This interrupt fires when the supply voltage drops
from the expected 3.3V to under 2.3V after power on. This gives
several hundred microseconds of time for the device to respond
to the power reduction.
In order to ensure that the ServoMicro does not enter a
non-responsive state, it triggers a reboot of the system to
restore it to a good configuration.
BRANCH=servo
BUG=chromium:1023715
TEST=Configured GPIO output to trigger on pvd_interrupt()
and verified the interrupt fires during the following
situations using Saleae analyzer:
* USB Power removed from working device
* Ramping supply voltage from 1.5V to 5V with a DC supply
* Repoducing failure condition from crbug/1016051
1 Connect ServoMicro to Cyan board
2 dut-control power_state:on
3 dut-control fw_wp_vref:pp3300
4 dut-control power_state:off
5 GPIO toggles and system reset occurs
Change-Id: I721f48ab84b01d52a5f98747cc9d879ff2876a07
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1911759
Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Tested-by: Brian Nemec <bnemec@chromium.org>
Commit-Queue: Brian Nemec <bnemec@chromium.org>
Auto-Submit: Brian Nemec <bnemec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This extracts the STM32F76X variant from the STM32F4 family
registers file.
This also removed a redundant #ifdef CHIP_FAMILY_STM32F4
inside the F4 family register file.
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=Grab registers-extract.bash
from http://go/bit/hesling/6385147721023488/4 .
chmod +x ./registers-extract.bash
# Make dummy board for STM32F76X using STM32f7 fammily
mkdir -p board/usestm32f7
printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f7\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk
touch board/usestm32f7/board.h
./registers-extract.bash board-regs-new
git checkout cros/master
# Change family back to STM32F4
printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f4\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk
./registers-extract.bash board-regs-original
diff board-regs-original board-regs-new
# Expect only a difference in CHIP_FAMILY
Change-Id: I5ff87e1c82c5d27d78c3ea62fed29d647a0f98db
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700167
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We enforce that all family specific registers file can only be
included from registers.h.
We add a brief history and rationale behind splitting registers.h into
multiple family specific header files.
We fix formatting of preprocessor conditionals and documentation.
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=Grab registers-extract.bash
from http://go/bit/hesling/6385147721023488/4 .
chmod +x ./registers-extract.bash
./registers-extract.bash board-regs-new
git checkout cros/master
./registers-extract.bash board-regs-original
diff board-regs-original board-regs-new
[ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad"
Signed-off-by: Craig Hesling <hesling@chromium.org>
Change-Id: I5d5983eb1e0cf7fb46339cba2987d551ff6b16cc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693879
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Using the sort_file.bash script from this bit:
http://go/bit/hesling/5840756455505920/7
$ git fetch "https://chromium.googlesource.com/chromiumos/platform/ec" refs/changes/78/1674678/6 && git cherry-pick FETCH_HEAD
$ cp registers.h registers-split.h
$ ./sort_file.bash chip/stm32/registers-split.h f0=chip/stm32/registers-stm32f0.h f3=chip/stm32/registers-stm32f3.h f4=chip/stm32/registers-stm32f4.h h7=chip/stm32/registers-stm32h7.h l=chip/stm32/registers-stm32l.h l4=chip/stm32/registers-stm32l4.h com=chip/stm32/registers.h
Modified registers.h to include chip family specific header file.
Modify copyright year of output files.
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=Grab registers-extract.bash
from http://go/bit/hesling/6385147721023488/4 .
chmod +x ./registers-extract.bash
./registers-extract.bash board-regs-new
git checkout cros/master
./registers-extract.bash board-regs-original
diff board-regs-original board-regs-new
[ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad"
Signed-off-by: Craig Hesling <hesling@chromium.org>
Change-Id: Ia7804e9a346ed94f881bd5583f5a4bf78422cb47
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1674679
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Ran the following command:
git grep -l 'Copyright (c)' | \
xargs sed -i 's/Copyright (c)/Copyright/g'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Currently, the sampling rate is set only once in adc_init. This patch
makes EC set the sampling rate every time ADC is sampled.
This patch also adds STM32_ADC_SMPR_DEFAULT so that zero can be used to
specify the default sampling rate.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b/131579158
BRANCH=none
TEST=Verified ADC readings match with externally measured voltage
for LCM_ID, BATT_ID, and USBC_THERM.
TEST=buildall
Change-Id: I73a1352dec907c2a8724e2f3f3d0258a706910a7
Reviewed-on: https://chromium-review.googlesource.com/1589253
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: YH Lin <yueherngl@chromium.org>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
No need to set up the TRNG's clock, on STM32F4 it always uses the PLL's
output that is set on boot.
BRANCH=None
BUG=b:124770147
TEST=hatch_fp builds. STM32F412's TRNG is not used on other projects.
Change-Id: Ie1f268137ee9a3a76cd0350e3ea5b2e85def1b76
Signed-off-by: Nicolas Norvez <norvez@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1481653
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
As requested for integration in kernel mfd subsystem, use BIT(...)
instead of (1 << ... ).
Add the macros, apply just to ec_commands.h for now.
BUG=None
BRANCH=None
TEST=Compile
Change-Id: I8509f1e8dc966799c3c4f0269b15f1ccc4138c07
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518658
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The timers 9 through 11 have different enable bits in the
STM32_RCC_APB2ENR on STM32F446/411/412 targets versus the
default (used by STM32F4/L4/STM32L) value set.
Break out the CHIP_FAMILY_STM32F4 case separately.
BRANCH=none
BUG=none
TEST=Observe PWM output on STM32412 EVM vs none before
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: I9f00902afe58ef8ef141da39b2b912ecc592944b
Reviewed-on: https://chromium-review.googlesource.com/1493273
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The CHIP_FAMILY_STM32L has the base addresses for the GPIO F, G
and H banks swapped w.r.t CHIP_FAMILY_STM32F4 and the alphabetic
order vs the base addresses.
Break out the CHIP_FAMILY_STM32F4 case in the registers file,
such that GPIOH bank works for both cases.
BUG=none
BRANCH=none
TEST=Use pin PH0 on STM32F412/11, observe it actually toggling
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: I9a639c4872f6e4c5b384cdab9e3da2f626e32227
Reviewed-on: https://chromium-review.googlesource.com/1481650
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable additional I2C/UART DMA channel mappings for STM32F412 chip
variant. Introduce new CHIP_VARIANT_STM32F41X define, to simplify
further refactoring.
BUG=none
BRANCH=none
TEST=build
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: I61ed545619ddda8846e598fcb461cf971fc9b905
Reviewed-on: https://chromium-review.googlesource.com/1404103
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Philip Chen <philipchen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Make ADCs on STM32F4 chips work by reusing most of the STM32F3 code
with the addition of SWSTART=1 bit in adc_read_channel.
The SWSTART=1 is most likely also required for the F3, but could
not be tested on actual hardware.
BUG=none
BRANCH=master
TEST=Build for nucleo-411RE and check measurements
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: Iea4f961b22119b5f2c1ee71295ec3ef1b7b7232c
Reviewed-on: https://chromium-review.googlesource.com/1217603
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Refactor ADC clock enable code to use clock_module_enable()
BUG=none
BRANCH=master
TEST=Build and run on discovery-stm32f072
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: Id3e8852fd5dd2fe47351dd9b9f84b0be9fb82dda
Reviewed-on: https://chromium-review.googlesource.com/1217602
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch switches the voltage scaler to VOS1 before increasing
the clock speed (PLL) and switches it back to VOS3 after reducing
the clock speed (HSI).
BUG=b:114520154
BRANCH=none
TEST=Enroll and match fingerprint on Nocturne without exceptions.
Change-Id: Ie369a382bab76efb090ca5fecf2cdb5fd05e0575
Reviewed-on: https://chromium-review.googlesource.com/1246832
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit e1f0d3b50bfa30abd2d2aa1a1aee1456bb049662)
Reviewed-on: https://chromium-review.googlesource.com/1249721
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Prevent flash readout, using RDP field in option byte.
When RDP is defined, it makes no sense to be able to unlock
RO, as that'd allow flashing arbitrary RO that could read
back the rest of the flash, so we just tie
EC_FLASH_PROTECT_RO_AT_BOOT and RDP protection. This also
means we can't unlock the flash after it has been finalized
(without removing WP and using BOOT0/stm32mon to mass erase
the chip).
Also, in flash_mp_mcu, call stm32mon with -U, to unlock
flash for read-back first (which disables RDP and triggers
a mass erase if RDP was enabled). Finally, load spidev
before putting releasing reset, which makes reflashing
more reliable.
BRANCH=nocturne
BUG=b:111330723
TEST=cp flash_mp_mcu read_mp_mcu, replace stm32mon line with:
"stm32mon -u -p -s ${SPIDEV} -r rb.bin"
dut-control fw_wp_state:force_off
=> Check that read_mp_mcu works
dut-control fw_wp_state:force_on
ectool --name=cros_fp flashprotect enable
ectool --name=cros_fp reboot_ec
=> RDP is now on
dut-control fw_wp_state:force_off
=> Check that read_mp_mcu does not work anymore
TEST=Add -U to stm32mon line above in read_mp_mcu, check that
readback only gets blank data.
TEST=In EC console, check that RDP bits are indeed not 0xaa:
Before: rw 0x5200201c => 0x07d6aaf0
After: rw 0x5200201c => 0x07d600f0
TEST=flash_mp_mcu still works (does a flash erase that removes
RDP protection)
Change-Id: Ifbe37ecafbf23f48d4a3cc17933130b7b104b728
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1222094
Commit-Ready: Nicolas Norvez <norvez@chromium.org>
Tested-by: Nicolas Norvez <norvez@chromium.org>
Reviewed-by: Nicolas Norvez <norvez@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
enable_ite_dfu: Enable direct firmware update (DFU) over I2C mode on
ITE IT8320 EC chip by sending special non-I2C waveforms over the
I2C bus wires.
get_ite_chipid: Verify that DFU mode is enabled by querying the EC over I2C
for its CHIPID1 and CHIPID2 registers. It will only respond over I2C when
in DFU mode.
BRANCH=none
BUG=b:79684405
TEST=get_ite_chipid succeeds after enable_ite_dfu
Change-Id: Ief2c12ebd902285ea3d285767deb8d35c0017592
Signed-off-by: Matthew Blecker <matthewb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1152565
Reviewed-by: Nick Sanders <nsanders@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The Reference Manuals for STM32H7 and STM32F4 makes it clear that,
when updating the watchog reload value, one needs to wait until
IWDG_SR bit RVU is reset before reloading the watchdog.
(the code in question is only used on STM32H7 and STM32F4, as other
variants use OBL_LAUNCH to reset themselves, so I didn't check
the other RMs).
This probably has not been seen before, as, normally, we use a 1s
watchdog timeout, so the EC would reset anyway after a second
(since it is stuck in the while loop below).
On meowth_fp, however, we use a 10 seconds watchdog, and the EC
takes too _long_ time to reboot, which breaks things like flashrom.
BRANCH=none
BUG=b:111144409
TEST=On nocturne_fp, run:
for i in `seq 1 1000`; do echo $i; \
./ectool --name=cros_fp reboot_ec cold; sleep 1; done
No watchdog warning, no error.
Change-Id: I110fa9873ed974bfafce23389866aac8cabb662a
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1134631
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
STM32H7 contains a True Random Number Generator. Add support for
that.
We source rng_clk from HSI48 oscillator (confusingly misspelled
hsi8_clk in RM), and fine-tune number of tries to make sure we
wait long enough for a random number, no matter the CPU speed
(64 or 400 MHz).
We also add a console command to test the random number generator
(disabled by default).
BRANCH=none
BUG=b:111190988
TEST=reboot; clock pll; rand => works.
TEST=reboot; rand => works.
Change-Id: I45624ff4df30b6a332226245e02e3e435b9b15bf
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1128785
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When entering STOP mode on STM32H743, the MCU was freezing forever if we
had power-cycle the MCU since the last time we entered the STM
Bootloader mode (but not when we had just flashed and reset it through
the reset pin).
This seems to be an interesting side-effect of the power configuration
locking.
The STM32H7 Reference Manual says the following about the PWR_CR3
register:
"[it is] reset only by POR only, not reset by wakeup from Standby mode
and RESET pad
...
The lower byte of this register is written once after POR and shall
be written before changing VOS level or ck_sys clock frequency."
Indeed, the system would fail waking from STOP mode if we don't do this
write (and when not doing a POR, the bootloader mode was doing it and
locking the register for us).
So keep the default configuration with the LDO enabled and lock the
register by writing SCUEN to 0.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:75105319
TEST=On Nocturne, power-cycle the full board and verify that the FPMCU
can come in and out of stop mode properly.
Change-Id: I822d74598b65c852b25e40ccb66a09a3e099dd2d
Reviewed-on: https://chromium-review.googlesource.com/1119922
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enter STOP mode when possible.
Use LPTIM1 clocked on the 32-Khz LSI as a time keeper / wake-up event
during STOP mode.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:75105319
TEST=On ZerbleBarn, use on-board INAs to measure idle power consumption,
w/o CONFIG_LOW_POWER_IDLE pp3300_h7_ma:14.0
with CONFIG_LOW_POWER_IDLE pp3300_h7_ma:1.84
Change-Id: I1b72a8f6964c7bc6174c07458f307dda57fe71f3
Reviewed-on: https://chromium-review.googlesource.com/1096767
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Parity defaulted to 7 bit data, but hammer wants 8 bit.
Change servo_micro to match.
BRANCH=servo-firmware
BUG=b:37513705
TEST=flash_ec -b hammer
Change-Id: I91cc126b03c99107084fb0d1d2e90031b2435fe2
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/952677
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Set the PLL frequency to 400 Mhz (max value) and the AHB frequency to
200 Mhz.
Fix the PLL clocking code for STM32H7 :
- fix the frequency computation.
- adjust the timer divider depending on the system clock.
- the 64Mhz HSI is already setup properly at startup, takes it into
account.
- set the SPI ports on the fixed 64-Mhz HSI, so clocking changes don't
mess up their frequencies or stability.
Note: this is just modifying the CPU frequency when the system is
clocked by the PLL, by default the system is still clocked by the 64-Mhz
HSI. Currently, one have to use the 'clock pll' console command to test
this PLL mode, some code will be added soon to switch on-demand for
heavy computations.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508, b:72879097
TEST=On ZerbleBarn, do 'clock pll', check 'gettime' against wall clock,
run image capture and enrollment.
TEST=on ZerbleBarn, verify on the scope that the SPI master frequency is
4 Mhz in both configuration.
Change-Id: I92a2216999337cf9831fb5dfc2797ab1cce71a8f
Reviewed-on: https://chromium-review.googlesource.com/941226
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We can turn off ADC after the first successful read for board version.
A few milliwatts saved is important when Scarlet is in S3.
BUG=b:72160379
BRANCH=scarlet
TEST=Try 'version' command a few times on EC console and see
correct board version.
Change-Id: Id2bef415f161431ed895f49db30d50347479176d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/942377
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Derek Basehore <dbasehore@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The STM32H743xI Errata document (rev Y) mentions in the paragraph 2.2.15
'Reading from AXI SRAM might lead to data read corruption':
"""
Read data might be corrupted when the following conditions are met:
- Several read transactions are performed to the AXI SRAM,
- and a master delays its data acceptance while a new transfer is
requested.
"""
We can actually hit this under a fair interrupt load and two tasks
running (e.g polling with the AP with host commands while doing
fingerprint image acquisitions).
So apply the proposed workaround and limit concurrent read access on AXI
master to 1 by setting the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD
register.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=on ZerbleBarn or Meowth, run 'ectool fpmode capture vendor',
poll in a tight loop with 'ectool fpmode'. No longer see random panics.
Change-Id: I6270866b74645d53e4d65f07f65431d5dee11576
Reviewed-on: https://chromium-review.googlesource.com/926009
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The STM32H7 family has 2 banks of flash (with 2 hardware controllers
able to do 2 parallel operations at the same time).
Each bank of flash has 4 or 8 128-kB erase blocks (1MB and 2MB
variants).
The flash can only be written by 256-bit word (with an additional 10-bit
ECC computed by the hardware).
For the flash write-protection, we cannot use our 'classical' PSTATE
scheme as the erase-blocks are too large (128-kB) to dedicate one to
this and the embedded word in the RO partition would not work as the
flash has ECC and triggers bus-fault when the ECC is incorrect (which
includes the case where the 256-bit word is written a second time).
So we will do the following:
- use the RSS1 bit in the option bytes as the Write-Protect enabled bit.
- if the WP GPIO is set, lock at startup the option bytes until next
reboot.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=run flashinfo/flashwp/flashwrite/flasherase commands on the EC
console.
Change-Id: I823fce3bd42b4df212cf0b8ceceaca84109b78e6
Reviewed-on: https://chromium-review.googlesource.com/901423
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
stm32f0 has 20 bytes (not 20 words) of VBAT-backed RAM. Make more
efficient use of our limited storage to prevent trying to use storage
that doesn't exist.
BUG=b:71333840
BRANCH=None
TEST=Negotiate PD, run "reboot" on scarlet EC console, verify reset path
is taken in pd_partner_port_reset().
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ie4c303b74a1b82b84ec971cdcc19c2b21a0032e7
Reviewed-on: https://chromium-review.googlesource.com/885461
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
According to RM0091, steps for using DMA for SPI peripheral should be:
1. enable DMA RX / TX
2. enable SPI
3. wait for DMA to complete
4. disable DMA RX / TX
5. disable SPI
BUG=b:70482333
TEST=tested on reworked staff (half-duplex)
TEST=tested elm (full-duplex)
Change-Id: I095409195cd1e0379995f0bfa6605c2e1a0dfd3c
Reviewed-on: https://chromium-review.googlesource.com/853715
Commit-Ready: Wei-Han Chen <stimim@chromium.org>
Tested-by: Wei-Han Chen <stimim@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update the host command support on the STM32 SPI slave for the STM32H7
silicon.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=with a servo v2 connected to ZerbleBarn,
send host commands v3 through the servo FTDI SPI interface.
Change-Id: I26ff4b6a3a45e446cd16e9da43c6932c24c37256
Reviewed-on: https://chromium-review.googlesource.com/839864
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Start adding support for the STM32H7 family of device and the first
available one the STM32H743.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=manual, run on stm32h743i-eval and zerblebarn boards
get a stable serial console.
Change-Id: I9ae10f0d843e5318451713c21ed22d455a23758c
Reviewed-on: https://chromium-review.googlesource.com/806168
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move all the peripheral blocks base addresses in a common block rather
than spread among the register definitions.
This will help making a cleaner STM32H7 implementation whose base
addresses are all different from other families.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=b:67081508
TEST=compare all the ec.bin generated by 'make buildall' and verify
they are bit-identical with and without the change.
Change-Id: I52cafd2f3c9145dbcd585166df3fc78e38573bb4
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enables the clock to the debug module so that when connecting via SWD
debugger the watchdog and timers are stopped.
BRANCH=master
TEST=Build on stm32f0x board and connect via SWD, observe no watchdog
reset.
Change-Id: Ic40b16c09acc5920da2c1a39e9391a6b21849d2c
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/765290
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz.
To use stm32 RTC for applications requiring accurate timing, let's setup
LSE (a more accurate clock source) as RTCCLK.
Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally.
BUG=b:63908519
BRANCH=none
TEST=boot scarlet rev1 and wait for an hour,
confirm rtc time == kernel system time.
Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/679601
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The STM32F76x is really close to the STM32F4 family, so the most concise
implementation is just using CHIP_FAMILY_STM32F4 and adding
CHIP_VARIANT_F76X.
Tune the clock settings to 180 Mhz CPU clock as the goal is performance.
(over-drive is not implemented yet to get to 216 Mhz)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=ran on nucleo-f767zi board.
'make BOARD=nucleo-f767 flash', the red LED is on and the green LED
turns on/off when pressing the user button, UART console works properly.
Change-Id: I1f67df3aec874c965c81188df46c72de210728d9
Reviewed-on: https://chromium-review.googlesource.com/612750
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
To enable console with DMA, we need to specifically
remap DMA channels for USART1.
ch2/3 and ch6/7 are already used by SPI1/2 modules.
So we have to remap USART1_TX to ch4 and USART1_RX to ch5.
BUG=b:64575809
BRANCH=none
TEST=confirm ec console works on scarlet rev1
Change-Id: Ie2bb141c72252aee98e4cd4a284a01b4d57605f4
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/611147
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add support for OTP memory: if needed store serial number in first bank.
BUG=chromium:746471
BRANCH=none
TEST=On sweetberry, check we can write serial number with serialno
command. Check serial number survive a firmware update.
First, check without write protect, check we can write 0s (but not 1s)
serialno
Serial number: NNNNNNNNNNNNNNNNNNNNNN
>
> serial set MMMMMMMMMMMMMMMMMMMMMMMMMMMMM
Saving serial number
Serial number: LLLLLLLLLLLLLLLLLLLLLL
After lock enabled, check we can not overwrite.
> serial set AMMMMMMMMMMMMMMMMMMMMMMMMMMMM
Saving serial number
Serial number: LLLLLLLLLLLLLLLLLLLLLL
Access Denied
Check that serialno returns "Uninitialized" if it was never set.
Change-Id: I9ab08486a7c3e1958e964649640d69b5b70947e3
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/580290
Reviewed-by: Nick Sanders <nsanders@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Unique device ID register (96 bits) is at a different place on STM32F4
compared to other STM32.
BUG=none
BRANCH=none
TEST=Using board_read_serial() from hammer/board.c in
sweetberry/board.c, confirmed that we can extract and assign a unique
USB serial number.
Change-Id: Idb257f0f20422482c729a2b97b4b16ee231ca4d9
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/579575
Commit-Ready: Gwendal Grignou <gwendal@google.com>
Tested-by: Gwendal Grignou <gwendal@google.com>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add a control interface to set parity
for USB-UART bridge.
BRANCH=None
BUG=b:37513705
TEST=parity settable on command line or by servod
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Change-Id: Ib859a70981162be58edfa79c7cb267e0084e05e6
Reviewed-on: https://chromium-review.googlesource.com/564150
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Before
72afc55bd9d3 "stm32: cleanup flash-f by using constant from register.h"
lock() function would simply do:
STM32_FLASH_CR = FLASH_CR_LOCK;
which would clear all other bits in STM32_FLASH_CR, including
FLASH_CR_OPTER and FLASH_CR_OPTWRE.
This allow preserve_optb to work, as it does:
1. erase_optb
a. unlock()
b. Set FLASH_CR_OPTER
c. lock() (clears FLASH_CR_OPTER!)
2. write_optb
a. unlock()
b. Set FLASH_CR_OPTPG
c. Write option byte
d. Clear FLASH_CR_OPTPG
e. lock()
After the patch, we now have:
STM32_FLASH_CR |= FLASH_CR_LOCK;
which seems more correct. However, 1.c. does not clear FLASH_CR_OPTER,
and 2.b. ends up with both FLASH_CR_OPTPG and FLASH_CR_OPTER set,
and the programming operation does not do anything.
This patches does 3 things:
- Rename FLASH_CR_OPTSTRT to FLASH_CR_OPTER, as that's the correct
register name for STM32F0 and STM32F3.
- Fix the above by clearing FLASH_CR_OPTER in erase_optb
- Also clear FLASH_CR_OPTWRE in lock(). Not strictly necessary,
but this seems to be the right thing to do.
BRANCH=none
BUG=chromium:739608
TEST=On hammer, type flashwp true; reboot; flashwp all; reboot
flashinfo => All flash is protected
Change-Id: Ic276545ae3c0bdb685c7b117a7f896ec341731bb
Reviewed-on: https://chromium-review.googlesource.com/562839
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We currently set STM32_FLASH_OPT_LOCKED
to (STM32_FLASH_CR & FLASH_CR_OPTWRE), however the bit is set
when option byte are _unlocked_.
From STM32F0 Reference Manual:
Bit 9 OPTWRE: Option byte write enable
When set, the option byte can be programmed. This bit is set
on writing the correct key sequence to the FLASH_OPTKEYR register.
This bit can be reset by software
BRANCH=none
BUG=chromium:739608
TEST=Flash hammer, flashwp true; reboot; flashinfo
=> hammer does not hang on reboot, RO is protected
Change-Id: I1b6eb5d638534ece90d6d5164586f49bdb0c151d
Reviewed-on: https://chromium-review.googlesource.com/561036
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On stm32f412, AHB prescaler must be 1 in order for stm32f412 to be
clocked at greater than 50MHz. APBX prescaler must be 2 so the clocks
can be in the right range. When APBX prescaler != 1, it results in 2x
timer clocks on both APB1 and APB2. We added a new
clock_get_timer_freq() function for stm32 to get timer specific clock
frequency so we can return 2x timer clocks when APBX != 1.
Flash latencies also need to be changed when we clock at 96MHz, the
FLASH_ACR_LATENCY defines are moved into the variant-specific switches
so each board can defined latency when setting CPU clocks.
BUG=b:38077127
TEST=`make BOARD=rose -j`, touch performance improved by 2x.
Change-Id: Ieb211ad80c168d3f57e72a8d16b954b703ee1444
Reviewed-on: https://chromium-review.googlesource.com/539375
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The flash controller of STM32F4 and STM32L4 supports data and
instruction caching. Enable them properly.
BRANCH=none
BUG=b:38077127
TEST=on rose,
> rw 0x40023c00
read 0x40023c00 = 0x00000701
Touch process loop is 5% faster.
Change-Id: Ibb28c0ed0c6a293547d5f0f7c6962f36fa417dd3
Signed-off-by: Wei-Ning Huang <wnhuang@google.com>
Reviewed-on: https://chromium-review.googlesource.com/497230
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|