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* spi: extend spi master API on STM32Vincent Palatin2017-08-171-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the SPI master API to be able to do fancier transactions: - allow to read the incoming bits while transmitting. If SPI_READBACK_ALL is set in 'rxlen' when calling spi_transaction(), then the received data during transmission is recorded in rxdata buffer and the function assumes that the real 'rxlen' is equal to 'txlen'. - add spi_transaction_wait() which is similar to spi_transaction_flush() but without de-asserting the chip select, so we can chain several transfers in a single transaction. Implement them for STM32. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648259 TEST=on Eve, use the FP sensor with the passthru. Change-Id: Iebff617acd3230277d36a4f565766b7748721a1d Reviewed-on: https://chromium-review.googlesource.com/452898 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> (cherry picked from commit 23ea0c9fa39163d3afb3dc5a96dce2962fb5014c) Reviewed-on: https://chromium-review.googlesource.com/618285 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* stm32: add support for STM32L442Vincent Palatin2017-02-171-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Should be close to the STM32L476 in the STM32L4 family. Slightly different flash/RAM. It's currently running from the internal clock (HSI) at 16Mhz, we need to upgrade to 80Mhz (or 48Mhz if this is fast enough to save us the PLL locking time). The internal flash write/erase/protection is still not implemented for the whole STM32L4 family. Upgrade the SPI master support and verify that the TX works. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:62893 TEST=make BOARD=eve_fp run it on Nucleo-L432KC (STM32L432KC is mostly the same MCU without AES) Change-Id: I87be7d4461aedfbd683ff7bb639c3a6005ee171e Reviewed-on: https://chromium-review.googlesource.com/442466 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: spi: Add lock around spi_transactionGwendal Grignou2015-08-011-0/+6
| | | | | | | | | | | | | | Like the implementation for mec1322, add a lock around spi_transaction. It prevents 2 tasks from accessing a given bus at the same time. BRANCH=smaug TEST=Check the BMI160 FIFO corruption disappeared in SPI mode. BUG=None Change-Id: I9e8a9e39ca96ea56692e3125930ab05ae6ef143f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289856 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Enable 3rd SPI interfaceGwendal Grignou2015-07-301-0/+15
| | | | | | | | | | | | | | | | Remove assumption of only one SPI master going to the SPI flash. SPI3 can be used as second SPI master. Define a new module type, SPI_FLASH, that can be turned on/off when flash is not in used without impacting other SPI masters. BRANCH=smaug BUG=chrome-os-partner:42304 TEST=Test on Ryu board. Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288514
* common: change interface to SPI flashGwendal Grignou2015-07-301-49/+71
| | | | | | | | | | | | | | | | Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
* stm32: fixed spi shared_mem_release bugSheng-Liang Song2014-12-181-1/+1
| | | | | | | | | | | | | | | If shared_mem_acquire() failed, we should not call shared_mem_release(). BRANCH=none BUG=chrome-os-partner:34703 TEST="Compiled" Change-Id: I5179f8b75b13451a63eb3209c9156066231aa12d Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/236392 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* spi_flash: add error checking for dma timeoutsDominic Chen2014-07-231-3/+8
| | | | | | | | | | | BUG=none BRANCH=none TEST=verify timeouts are caught by spi_transaction_*() Change-Id: I2e28ccbce58e555262bc4448a1c2e1a50253613e Signed-off-by: Dominic Chen <ddchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209116 Reviewed-by: Vic Yang <victoryang@chromium.org>
* Refactor STM32 SPI flash driverVic Yang2014-07-151-0/+211
This CL factors out the SPI flash driver to be a STM32-specific SPI master driver and a common SPI flash driver. BUG=None TEST=Verify on Fruitpie BRANCH=None Change-Id: I9cca918299bc57a6532c85c4452e73f04550a424 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/206582 Reviewed-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Daming Chen <ddchen@chromium.org> Tested-by: Daming Chen <ddchen@chromium.org>
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