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* lm4: stm32: Store panic data in backup registers on hard resetShawn Nematbakhsh2015-03-141-2/+37
| | | | | | | | | | | | | | | | | | On hard reset / hibernate, RAM will be erased and panic data will normally be lost. When software panic data saving is enabled, try to save this data just before hard reset and restore it when we come back up. BUG=chrome-os-partner:37380 TEST=Manual on Samus with WP + SW sync enabled. Boot AP, then run "crash divzero" on console. After hard reset, verify that "panicinfo" dumps data and shows divzero exception code. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9516dd4b6db12ef35e512cc4710f9b97d7e663cb Reviewed-on: https://chromium-review.googlesource.com/255912 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: Add delay after enabling peripheral clockVic Yang2015-02-101-0/+3
| | | | | | | | | | | | | | | | | We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* Write protect support for STM32F0Vic Yang2014-10-151-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On STM32F0, we cannot work around the hard fault triggered when trying to protect the whole flash. Therefore, we need to go with the ALL_AT_BOOT approach. When write protect is enabled, instead of setting ALL_NOW flag to immediately lock down the entire flash, we need to set ALL_AT_BOOT and then reboot to have the protection take effect. BUG=chrome-os-partner:32745 TEST=Along with the next CL. On Ryu: 1. Enable HW WP. Check the output of 'ectool flashprotect' and see correct flags. 2. 'flashrom -p ec --wp-range 0 0x10000'. Check RO_AT_BOOT is set. 3. Reboot EC and check RO_NOW is enabled. 4. Boot the system and check ALL_NOW is set. 5. Update BIOS and reboot. Check software sync updates EC-RW. 6. 'flashrom -p ec --wp-disable' and check it fails. 7. Disable HW WP and reboot EC. Check RO_NOW and ALL_NOW are cleared. 8. 'flashrom -p ec --wp-disable' and check RO_AT_BOOT is cleared. TEST=Enable/disable WP on Spring. Check RO_AT_BOOT/ALL_NOW can be set properly. BRANCH=samus Change-Id: I1c7c4f98f2535f1c8a1c7daaa88d47412d015977 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/222622 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f: stm32f0: guard hibernate function with CONFIG_HIBERNATEVic Yang2014-10-081-0/+2
| | | | | | | | | | | | | | If CONFIG_HIBERNATE is explicitly undefined for a platform, we shouldn't try to hibernate. BUG=chrome-os-partner:32727 TEST=None BRANCH=None Change-Id: Id0f93a3a694065478373e364d82589ff08e7d980 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/222013 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add support for STM32F373Vic Yang2014-10-071-3/+6
| | | | | | | | | | | | | | | | | | | This mostly reuses chip drivers for STM32F and STM32F0. Since this chip doesn't fit either STM32F or STM32F0, let's use symlink to specify which drivers to use for STM32F3. This is just the preparatory work and it's not verified on a chip yet. BUG=chrome-os-partner:32660 TEST=make buildall to make sure this doesn't break anything BRANCH=None Change-Id: I709ed49265e8f84552251a97d03b9b98496de99e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221412 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f0: stm32l: Fix backup register indexingVic Yang2014-08-081-0/+19
| | | | | | | | | | | | | | | On stm32f0 and stm32l, the backup registers are 32-bit. Fix the index calculation. BUG=chrome-os-partner:31214 TEST=On Ryu, save and load VbNvContext BRANCH=None Change-Id: I86e5dc31c80bed46a6fe13929c7e6a1d4ca9f97b Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/211462 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add cprints() and ccprints()Vic Yang2014-05-211-1/+1
| | | | | | | | | | | | | | | | | | | | | Our code base contains a lot of debug messages in this pattern: CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n") The strings are taking up spaces in the EC binaries, so let's refactor this by adding cprints() and ccprints(). cprints() is just like cprintf(), except that it adds the brackets and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...) This saves us hundreds of bytes in EC binaries. BUG=chromium:374575 TEST=Build and check flash size BRANCH=None Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200490 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: add support for STM32F0xx familyVincent Palatin2014-03-111-1/+1
| | | | | | | | | | | | | | | | | | Add support for the STM32F0xx family of devices using a Cortex-M0 core and slightly newer peripherals than F1xx family. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run EC console on STM32F072B Discovery board. and pass all available unit-tests on target. Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735 Reviewed-on: https://chromium-review.googlesource.com/188983 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Rename mixed-case config constantsRandall Spangler2013-12-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | This renames constants used in compiler conditionals to uppercase. BOARD_foo CHIP_foo CHIP_FAMILY_foo CHIP_VARIANT_foo CORE_foo Mixed-case constants are still defined by the makefile, but are now no longer used. I will make one more pass in a week or so to catch any that are part of someone else's CL, since otherwise this change might silently merge correctly but result in incorrect compilation. Then I will remove defining the mixed-case constants. BUG=chromium:322144 BRANCH=none TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no results (similarly for CHIP, CORE, etc.) Change-Id: I6418412e9f7ec604a35c2d426d12475dd83e7076 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179206 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Improve / remove more TODO commentsRandall Spangler2013-11-011-6/+0
| | | | | | | | | | | | | Add bug references. Remove one assert that can no longer be triggered. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I3f4d2e4f2f3343a8d0531cb0715d151eaa4d0b50 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175293 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32: Add CHIP_FAMILY definesRandall Spangler2013-07-011-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, code which needed to work on all STM32F platforms needed to specify them by name (CHIP_VARIANT_stm32f100 || CHIP_VARIANT_stm32f10x), and we needed extra symlinks in the chip/stm32/ directory to allow the build system to find family-specific files. Add a CHIP_FAMILY level of abstraction, so that things which are common across all STM32F platforms don't need to specify every STM32F variant. Make the chip build look for family-specific filenames instead of variant-specific filenames (except for config*.h, which is actually variant specific). In the few places where things actually are variant-specific, keep using the existing CHIP_VARIANT defines. Code refactoring only; no functional changes. BUG=chrome-os-partner:20567 BRANCH=none TEST=build all platforms Change-Id: I1da831aadabf8b8dd9dfde423cac13c9f43eb953 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60247 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* stm32: add hibernate support using stm32f100 standby modeVincent Palatin2013-06-111-11/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the EC hibernate mode by using the stm32f100 standby low power mode. As we cannot de-activate the watchdog during long hibernation, the following workaround is implemented: we are woken-up once by the watchdog and go back to hibernate if we detect that condition. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=spring BUG=chrome-os-partner:19595 TEST=on Spring with rework on the EC wake-up pin, type "hibernate 10" and see the EC console going blank for 10s, then booting with reset cause equals to "hibernate". Press Alt+VolUp+H, then wake-up the system by pressing power key. Change-Id: I28150e69817ae80314f52977ec6b62750017c2c4 Reviewed-on: https://gerrit.chromium.org/gerrit/58086 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Support flash write protect on STM32LRandall Spangler2013-05-221-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for write protecting the RO code at boot, and the entire flash on demand. Implementation if WP# is not asserted is currently a little different than STM32F and LM4; RO is still protected at boot if ro_at_boot, but can be unprotected and the change will commit on the next reboot. This saves the bank of flash which we use for pstate on LM4 and STM32F. I think I can use one of the unused option bits (WRP2 bit 0) to hold the RO-at-boot flag, in which case I can more closely match the behavior of the other chips, but I'd like to do that (or give up and implement pstate) in a separate CL so it's clearer what I'm doing. BUG=chrome-os-partner:15613 BRANCH=none TEST=manual - flashinfo -> (no flags) - enable WP (via screw or dut-control) - flashinfo -> wp_gpio_asserted - flashwp enable - flashinfo -> wp_gpio_asserted ro_at_boot - flashwp now - flashinfo -> wp_gpio_asserted ro_at_boot all_now - flashwp disable -> fails - flashinfo -> wp_gpio_asserted ro_at_boot all_now - flasherase 0x1fc00 0x400 -> fails - reboot - flashinfo -> wp_gpio_asserted ro_at_boot ro_now - flasherase 0xfc00 0x400 -> fails - flasherase 0x1fc00 0x400 -> succeeds - disable WP (via screw or dut-control) - reboot - flashinfo -> ro_at_boot ro_now - flashwp disable - flashinfo -> ro_now - reboot - flashinfo -> (no flags) - flasherase 0xfc00 0x400 -> succeeds - flasherase 0x1fc00 0x400 -> succeeds Change-Id: Id1b6b099a44a1985a5ab9387feb882a8f26e3aa1 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55594
* Add console command to force enable consoleVic Yang2013-05-151-18/+16
| | | | | | | | | | | | | | | | | | | | | | When system is locked, the console is disabled. However, we need console for debugging and testing. This CL uses a bit from back-up register to indicate if the console should always be enabled. (This bit is currently used by fake WP, which is removed in this CL.) With this, we can set this bit with console command 'forceen 1' to ensure console is never disabled. To prevent device shipped in this state, the chip name is postfixed with '-unsafe' so that the device is not able to pass HWID check. BUG=chrome-os-partner:19293 TEST=Manual BRANCH=spring Change-Id: I88556e973ca542c1bdc27ba64988718291e01a26 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51086 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: unimplemented hibernate hard-reboots instead of hangingtoolchainAstabilize-3912.79.Brelease-R27-3912.BRandall Spangler2013-03-251-2/+9
| | | | | | | | | | | | | | | This more closely emulates what LM4 does if it hibernates and then immediately wakes. Keeps the system from becoming silently unresponsive if a hibernate is triggered on STM32. BUG=chrome-os-partner:18371 BRANCH=none TEST=from ec console, 'hibernate' reboots instead of hanging Change-Id: I031f79239725d69ba054323e4fbf8f59133f2093 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/46286 Reviewed-by: Vic Yang <victoryang@chromium.org>
* stm32f10x: Initial importDavid Hendricks2013-03-081-1/+1
| | | | | | | | | | | | | | | | | | | | | This adds initial support for the other chips in the stm32f10x series: stm32f101, stm32f102x, stm32f103x, stm32f105x, stm32f107x. The main difference is in the register definitions. Clock, flash, GPIO, and JTAG modules are similar enough that for now we can symlink the existing source for stm32f100. BRANCH=none BUG=none TEST=Tested on McCroskey (follow-up CL) Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I67363d02578e21be51d842b6bd8b5e4848720993 Reviewed-on: https://gerrit.chromium.org/gerrit/43412 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org>
* Clean up system moduleRandall Spangler2012-10-251-23/+13
| | | | | | | | | | | | | | No functional changes. (it might look like SYSTEM_HIB_MINIMUM_DURATION is a change, but it's not used at present) BUG=chrome-os-partner:15579 BRANCH=none TEST=version; chip info should print successfully Change-Id: Idd7f60a29528e9f6af4f91cd5a556e7336acee9f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36599 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32: Store VbNvContext in backup registersChe-Liang Chiou2012-09-051-0/+43
| | | | | | | | | | | | | | | | | | | | | | This would improve boot speed when compared to storing in eMMC because initialing eMMC is slow. So far other platforms do not have this need because CMOS is quite efficient; thus it is left unimplemented in lm4. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> BRANCH=snow BUG=chrome-os-partner:10660,13094 TEST=On Snow, see VbNvContext is preserved across power cycles (you have to patch U-Boot to test this) Change-Id: If5072c678b87bc47a3a82a1dff2afa3896304f36 Reviewed-on: https://gerrit.chromium.org/gerrit/31832 Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Che-Liang Chiou <clchiou@chromium.org>
* stm32: Squeeze fakewp backup register for VbNvContextChe-Liang Chiou2012-09-051-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We squeeze 2 bytes out of fakewp backup register so that we would have full 16 bytes for VbNvContext. As fakewp will go away real soon and it needs just 1 bits, we move it to saved reset flags register's most significant bit, which is currently unused. Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> BRANCH=snow BUG=chrome-os-partner:10660,13094 TEST=manual Make sure reset flags are still preserved: 1. reset with keyboard. flags -> reset-pin 2. trigger watchdog reset. flags -> reset-pin watchdog 3. 'reboot soft preserve' flags -> reset-pin watchdog soft 4. trigger watchdog reset. flags -> reset-pin watchdog 5. 'reboot soft' flags -> reset-pin soft Make sure fakewp is still preserved: 1. 'flashinfo' -> no flags 2. 'fakewp 1' -> 'wp_gpio_asserted' 3. 'flashwp enable' -> 'wp_gpio_asserted ro_at_boot' 4. 'reboot' -> 'wp_gpio_asserted ro_at_boot ro_now' 5. 'fakewp 0' -> 'ro_at_boot ro_now' 6. 'reboot' -> 'ro_at_boot' 7. 'fakewp 1' -> 'wp_gpio_asserted ro_at_boot' 8. 'flashwp rw' -> 'wp_gpio_asserted ro_at_boot rw_at_boot' 9. 'reboot' -> 'wp_gpio_asserted ro_at_boot ro_now rw_at_boot rw_now' 10.'flashwp disable'-> error 7 11.'flashwp norw' -> 'wp_gpio_asserted ro_at_boot ro_now rw_now' 12.'reboot' -> 'wp_gpio_asserted ro_at_boot ro_now' Change-Id: Ibb7dc8aa224d3226bbaac217e494565e448b5858 Reviewed-on: https://gerrit.chromium.org/gerrit/32041 Commit-Ready: Che-Liang Chiou <clchiou@chromium.org> Tested-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: simplify hard resetVincent Palatin2012-08-241-102/+23
| | | | | | | | | | | | | | | | | | | use the watchdog instead of the hibernation mode and RTC wake-up to accomplish the hard reset. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:13126 TEST=on Snow, in U-Boot console, type "mbkp reboot cold" and see the AP rebooting properly. BRANCH=snow Change-Id: Ic8b83f033e9dd4ccf1dff664226bf0ae6b9c47e5 Reviewed-on: https://gerrit.chromium.org/gerrit/31373 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f: Use FLASH_KEYR to lock entire flashVic Yang2012-08-081-13/+0
| | | | | | | | | | | | | | | | | | | | | | | | Writing wrong key to FLASH_KEYR locks entire flash and effectively performs RW_NOW. Therefore we can use this and remove RW_AT_BOOT to prevent having to reboot for RW to be protected. BUG=chrome-os-partner:12043 TEST=1. fakewp 1 -> wp_gpio_asserted 2. flashwp now -> nothing happens 2. flashwp enable -> wp_gpio_asserted ro_at_boot 3. reboot -> wp_gpio_asserted ro_at_boot ro_now 4. flasherase 0x10000 0x1000 -> success 5. flashwp now -> wp_gpio_asserted ro_at_boot ro_now rw_now 6. flasherase 0x10000 0x1000 -> error 7. reboot -> wp_gpio_asserted ro_at_boot ro_now 8. flasherase 0x10000 0x1000 -> success Change-Id: I22df188e31404c190c5830c6d94c9646224eb9ab Reviewed-on: https://gerrit.chromium.org/gerrit/29255 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* Snow has write protect pin (PB4) wired to EC.Louis Yung-Chieh Lo2012-08-011-0/+2
| | | | | | | | | | | | | | Intend to keep fake_wp functions for test. BUG=chrome-os-partner:9986 TEST=build only (success on link/snow/daisy/bds). Have no hardware to test. Change-Id: I1e2ae923790d65b6c95819f5274dbe8c7f254429 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/28793 Commit-Ready: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com> Tested-by: Yung-Chieh Lo <yjlou%chromium.org@gtempaccount.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f: Flash write protectVic Yang2012-07-261-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement STM32F write protect to match refactored flash module. Also move fake write-protect pin to use backup register to preserve value across reboot. BUG=chrome-os-partner:11699 TEST=1. 'flashinfo' -> no flags 2. 'fakewp 1' -> 'wp_gpio_asserted' 3. 'flashwp enable' -> 'wp_gpio_asserted ro_at_boot' 4. 'reboot' -> 'wp_gpio_asserted ro_at_boot ro_now' 5. 'fakewp 0' -> 'ro_at_boot ro_now' 6. 'reboot' -> 'ro_at_boot' 7. 'fakewp 1' -> 'wp_gpio_asserted ro_at_boot' 8. 'flashwp rw' -> 'wp_gpio_asserted ro_at_boot rw_at_boot' 9. 'reboot' -> 'wp_gpio_asserted ro_at_boot ro_now rw_at_boot rw_now' 10.'flashwp disable'-> error 7 11.'flashwp norw' -> 'wp_gpio_asserted ro_at_boot ro_now rw_now' 12.'reboot' -> 'wp_gpio_asserted ro_at_boot ro_now' Change-Id: I40405c266e30b10793ccae2f1d26fb9710ce304b Reviewed-on: https://gerrit.chromium.org/gerrit/28372 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* Refactor reboot command to add ap-off and cancel optionsRandall Spangler2012-07-231-5/+9
| | | | | | | | | | | | | | | | | | | | | | Also add 'preserve' flag, for tracking when flags have been preserved from a previous boot. BUG=chrome-os-partner:11663 TEST=manual reboot -> flags = soft reboot preserve -> flags = soft preserve From ectool, 'ectool reboot_ec cold at-shutdown' sysinfo -> shows reboot at shutdown: 4 reboot cancel sysinfo -> no longer shows pending reboot reboot ap-off -> flags = soft ap-off, AP is not powered on Change-Id: I117f33fe21048edb2261be4dcdc6c828a5794d54 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/28139
* stm32f: Support hard resetVic Yang2012-07-191-6/+33
| | | | | | | | | | | | | | | | Now that we have hibernate ability, we can use this to perform a hard reset. BUG=chrome-os-partner:11579 TEST=Build success and working on 'snow': 'reboot' and see reset cause is 'reset-pin soft'. 'reboot hard' and see reset cause is 'hard'. Build success on 'daisy'. Change-Id: I18132eee2f0d574d7d1674f7be25249dbe19749d Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27930 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f: Add hibernate supportVic Yang2012-07-191-0/+74
| | | | | | | | | | | | | | | | | This adds hibernate support to stm32f. Watchdog can wake us but cannot be stopped unless system resets, so the longest time we can hibernate for now is about 26s. And wake from wake pin is not working. Nevertheless, we can use this for hard reset for now, and fix these problems later. BUG=chrome-os-partner:11579 TEST='hibernate 1' and see system wakes after 1 second. See reset cause is 'hibernate'. Change-Id: Iafa42012b59c12b70e18a7908c5d864c6e8bd2b4 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27909 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: Support backup registers and preseving reset flagsVic Yang2012-07-191-6/+50
| | | | | | | | | | | | | | | | | | | | This CL configures backup registers and add support of preseving reset flags in backup registers before rebooting. BUG=chrome-os-partner:11368 TEST=On snow there's always a reset-pin flag now, so test this with watchdog and soft reset. 1. reset with keyboard. flags -> reset-pin 2. trigger watchdog reset. flags -> reset-pin watchdog 3. 'reboot soft preserve' flags -> reset-pin watchdog soft 4. trigger watchdog reset. flags -> reset-pin watchdog 5. 'reboot soft' flags -> reset-pin soft Change-Id: I8b8a8abfbd69d8abb3386b188af73b9f662f4b38 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27848 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Support preserving reset flags across a resetRandall Spangler2012-07-161-2/+2
| | | | | | | | | | | | | | | | | | | | This is needed for flash pre-init to be able to hard reset to clear uncommitted write protect flags without losing the reset flags. BUG=chrome-os-partner:11368 TEST=manual Use reboot and sysinfo commands... 1. reset with keyboard. flags -> reset-pin 2. 'reboot soft preserve' flags -> soft reset-pin power-on 3. 'reboot hard preserve' flags -> hard soft reset-pin power-on 4. 'reboot soft'. flags -> soft 5. 'reboot hard'. flags -> hard power-on Change-Id: I6164a78d99c5c10330f90f651148c5795e7afdda Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27418
* Refactor reset reasonsRandall Spangler2012-07-161-12/+17
| | | | | | | | | | | | | | | | | | | | | | | | | Reasons are really bitflags, not a single reason. This will make it easier to implement flash protection on LM4, where hibernate is a subset of power-on reasons. Also added some additional flags we pass in a hibernate register so... 1) We don't recognize spurious RTC wake reasons 2) Hard reset via system_reset(1) is detected as a hard reset, not a RTC wake BUG=chrome-os-partner:11368 TEST=manual 1. Keyboard reset = power-on reset-pin 2. Pull battery = power-on 3. reboot = soft 4. reboot hard = power-on rtc-alarm 5. hibernate 10 then push power button = power-on wake-pin 6. reboot 3 sec later = soft 7. hibernate 1 = power-on rtc-alarm Change-Id: Icbbdbcf6dfd13c8a6a4f80a23f64cebebbfba26e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27417
* Add LM4 support for hard resetRandall Spangler2012-05-211-16/+9
| | | | | | | | | | | | (And add STM32 support for disabling interrupts before reset, which got missed before.) Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7470 TEST=from console, "reboot", then "reboot hard" Change-Id: Ib98792abc0c91a01e2230b419fc876052380655a
* introducing chip variant for stm32 family [3/3]Vincent Palatin2012-05-011-1/+13
| | | | | | | | | | | | | Add STM32F support. Based on David's changelist. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: Ide817d11480f0b56f67deaae3c08bc631f605075
* introducing chip variant for stm32 family [1/3]Vincent Palatin2012-05-011-0/+121
just rename STM32L to STM32. Most of the STM32L15x code is common with STM32F1xx. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: I819eff5fcd23deff57f5f6dedcf37e6c421b96c2
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