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* Fix various misspellings in commentsMartin Roth2016-11-151-1/+1
| | | | | | | | | | | | | No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* stm32: Fixed bugs with stm32l4 register masksChris Chen2016-09-271-4/+6
| | | | | | | | | | | | | | | Also filled out rest of CCIPR register defs for stm32l4 chip family BRANCH=None BUG=None TEST=make buildall Change-Id: Ic9d1f966068915e304a0994c49fa9bbafec6cdf4 Reviewed-on: https://chromium-review.googlesource.com/367830 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32f446e-eval: add support for stm32f446Nick Sanders2016-08-171-2/+15
| | | | | | | | | | | | | | | | | | This adds basic support for the stm32f446. This consists of: * New DMA model for stm32f4 * New clock domain support. * MCO oscillator gpio export support. * Flash support for irregular blocks. BUG=chromium:608039 TEST=boots w/ correct clock, stm32f0 also boots. BRANCH=None Change-Id: I1c5cf6ddca09009c9dac60da8a3d0c5ceedfcf4d Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363992 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* STM32: Set UART clock sources to SYSCLKDaisuke Nojiri2016-04-291-2/+6
| | | | | | | | | | | | | | | | Since uart_freq_change assumes we drive UARTs at system clock, we need to set UARTs clock sources accordingly. This will allow us to clock up the chip without worrying about prescaler values set for HCLK and PCLK or the on/off status of HSI. BUG=none BRANCH=tot TEST=make buildall. Verified LPUART on stm32l476g-eval. Change-Id: I02898921e31b68cacbc2235a29c47a212c350afe Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341260 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* UART: Remove enable/disable interrupt functionsAnton Staaf2016-04-271-10/+0
| | | | | | | | | | | | | | | | These were not being used and complicate changes to the UART API. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I73e256f09f7ea72f0cc4831cc7ce391a7125e555 Reviewed-on: https://chromium-review.googlesource.com/340841 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* STM32: Support LPUART consoleDaisuke Nojiri2016-04-251-0/+8
| | | | | | | | | | | | | | | This patch adds support for console on LPUART (low power UART). It is wired to the USB type B port on the board, which is also one of the power sources. So, using LPUART simplifies the set up. BUG=none BRANCH=tot TEST=Verified console works on stm32l476g-eval. make buildall Change-Id: Iccf697cfabdcb7e1362d8453708eb79610d2e0cb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340101 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Bring up STM32L476G-EvalDaisuke Nojiri2016-04-251-2/+9
| | | | | | | | | | | | | This patch adds initial set of files to bring up STM32L476G-Eval board. BUG=none BRANCH=tot TEST=Tested console. make buildall && make tests Change-Id: I0c0f73f31e84099746fced4214c5ed7f45468cef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340100 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Add delay after enabling peripheral clockVic Yang2015-02-101-0/+6
| | | | | | | | | | | | | | | | | We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* stm32f0: USART: Disable ORECF interrupt we never check forAlexandru M Stan2014-12-181-1/+7
| | | | | | | | | | | | | | | | | | | When the EC is busy enough to start missing RX characters an ORECF might come (Overrun error), we never check for this bit, so that means the interrupt handler will be called in a loop because it never clears that bit. This disables the overrun detection feature. BUG=chrome-os-partner:33451 TEST=get firmware to poll the EC for keyboard presses, type really fast on the keyboard, note how system does not watchdog reset anymore but loses the occasional character instead. BRANCH=None Change-Id: I711483768e4ba80aaeb4a324c7dee790b3a23682 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/236088 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f0: stm32f3: Wake from STOP mode on UART start bitVic Yang2014-10-281-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | By default, UART wakes the chip up on RXNE interrupt. This means when the chip wakes up, RDR is full and only the shift register is empty, and this leaves us only the time of a single character to process the character in RDR. On some system, this is not enough and the first (or even the second) character is overrun, and thus any multi-character keys (e.g. arrow keys) break. To avoid this problem, let's change the wake source to wake on start bit detection. This gives us the time for one more character to wake up and process the console input. BRANCH=None BUG=chrome-os-partner:33219 TEST=Enable low power mode on Ryu P2. In STOP mode, hit up arrow key and see the last command show up. Change-Id: Idce4c0bdfcf3e04ad84152ba525f704a0909f115 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225771 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@google.com>
* stm32: Wait for UART Tx to complete before entering STOP modeVic Yang2014-10-241-1/+20
| | | | | | | | | | | | | | | | | | | | | | | Before entering STOP mode, we need to ensure UART Tx has completed. Otherwise, we may lose some characters or some bits within a character. For Tx DMA mode, this is already done as we wait until TC (Tx complete) is set before disabling Tx. However, when not using DMA, we enable sleep when TXE is set. At this moment, the last character is still in the shift register and going into sleep causes loss of the whole or part of the last character. To avoid this, let's enable TC interrupt and enable sleep only if we have no more characters to send and TC is set. BRANCH=None BUG=chrome-os-partner:33219 TEST=Enable low power mode on Ryu P2. Type when the EC is in STOP mode and check there is no broken character. Change-Id: Ife42671882b7f1d1d17734d7d20fb4ba7dffb371 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225283 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Fix UART Rx DMA for USART2 and aboveVic Yang2014-10-241-1/+1
| | | | | | | | | | | | | | This modifies the stray hard-coded DMA channel for UART Rx to the correct config flag. BRANCH=None BUG=chrome-os-partner:32660 TEST=On Ryu, enable UART Rx DMA and check console is still responsive Change-Id: Icec2de6ad4d34c6e0f8df2a1d51d9fefd982c9f4 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225239 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Support UART DMA on UART2Vic Yang2014-10-221-2/+10
| | | | | | | | | | | | | | | This adds the DMA channel definition for UART2 and allows selection of DMA channel for UART. BRANCH=None BUG=chrome-os-partner:32660 TEST=With the CLs to enable the new Ryu boards, check the console is working. Change-Id: I964c284899777dda67c264e622aea6aba752ea76 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224176 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add support for STM32F373Vic Yang2014-10-071-4/+6
| | | | | | | | | | | | | | | | | | | This mostly reuses chip drivers for STM32F and STM32F0. Since this chip doesn't fit either STM32F or STM32F0, let's use symlink to specify which drivers to use for STM32F3. This is just the preparatory work and it's not verified on a chip yet. BUG=chrome-os-partner:32660 TEST=make buildall to make sure this doesn't break anything BRANCH=None Change-Id: I709ed49265e8f84552251a97d03b9b98496de99e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221412 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f0: fix UART clock source for console on UART2Alec Berg2014-09-221-2/+2
| | | | | | | | | | | | | | | | Bug fix. Recently changed to use HSI 8MHz clock as clock source for console UART, but the clock register was set incorrectly for the case that the console UART is UART2. BUG=chrome-os-partner:32170 BRANCH=none TEST=Tested on fruitpie which is using UART2 for console. Verified that console works. Change-Id: Ied629eb3828e5fab911acb6a8e5f4087563ddb32 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219312 Reviewed-by: Vic Yang <victoryang@chromium.org>
* stm32f0: Change uart clock to HSIAlexandru M Stan2014-09-191-1/+22
| | | | | | | | | | | | | | | | | | | | | When waking up from sleep, the real CPU_CLOCK is a lie for a moment(since we cannot switch to the real clock during the first character) so the first character will be corrupted. The UART clock is now sourced from HSI(8MHz) which is available from the first moment after the cpu wakes up from sleep. BUG=None TEST=Console should work. When waking up(not implemented yet) it will also not lose a character BRANCH=None Change-Id: Ia12ed0634290f3edadfe3471b311759c3176260e Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218728 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* stm32: change USART register macros to take a base addressAnton Staaf2014-07-171-30/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously these macros took a small integer to identify the USART to access. This integer was token concatenated to form the macro name that resolved to the base address. This made it imposible to use these macros in a driver that could manage more than one USART because there was no runtime way to go from base address (or other unique identifier) to register address. This change makes it possible to pass either a static compile time known base address or a runtime variable with the base address, thus supporting either sort of driver. The existing USART driver has been updated to compute the base address of the console USART and pass that at compile time, resulting in no increase in code size. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=none TEST=make buildall -j Followed by manual testing of console over UART functionality on the STM32F072 based discovery board. Change-Id: I06547a173b1e5cf625a57019ea4b8a84d1768444 Reviewed-on: https://chromium-review.googlesource.com/208488 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* stm32: Enable USART TCIE after clearing TCstabilize-5875.BDavid Hendricks2014-05-211-0/+3
| | | | | | | | | | | | | | | | | | | After clearing the TC flag, we should re-enable TCIE so that when the DMA transfer is done we re-interrupt and allow uart_process_output() to continue printing whatever is in the circular buffer (in the case of wrap-around) or finish gracefully if there is nothing left in the buffer. BUG=chrome-os-partner:28837 BRANCH=nyan TEST=Commands now reliably print full output whereas before they might appear truncated until another interrupt was triggered to finish printing the buffer. Change-Id: I0a4236139f57812f384e2b99af45195537201a04 Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200499
* stm32: add support for STM32F0xx familyVincent Palatin2014-03-111-6/+6
| | | | | | | | | | | | | | | | | | Add support for the STM32F0xx family of devices using a Cortex-M0 core and slightly newer peripherals than F1xx family. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run EC console on STM32F072B Discovery board. and pass all available unit-tests on target. Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735 Reviewed-on: https://chromium-review.googlesource.com/188983 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* force the compiler to use a valid register allocation for irq handlersVincent Palatin2014-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Rename mixed-case config constantsRandall Spangler2013-12-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This renames constants used in compiler conditionals to uppercase. BOARD_foo CHIP_foo CHIP_FAMILY_foo CHIP_VARIANT_foo CORE_foo Mixed-case constants are still defined by the makefile, but are now no longer used. I will make one more pass in a week or so to catch any that are part of someone else's CL, since otherwise this change might silently merge correctly but result in incorrect compilation. Then I will remove defining the mixed-case constants. BUG=chromium:322144 BRANCH=none TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no results (similarly for CHIP, CORE, etc.) Change-Id: I6418412e9f7ec604a35c2d426d12475dd83e7076 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179206 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* lm4: Add a low power idle task.stabilize-4825.BAlec Berg2013-10-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First implementation of a low power idle task for the LM4 chip. The low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a board.h file. This commit turns it on for Peppy, Slippy, and Falco only because those are the only boards tested. When using the low power idle task, the chip goes in to deep sleep when it can. Deep sleep disables clocks to most peripherals and puts the onboard flash and RAM into a low power mode. The chip is woken out of deep sleep using the RTC in the hibernate module. Increased the idle task stack size to handle more involved idle task. In board.c, the array of GPIO info can be used to select which GPIO points can wake up the EC from deep sleep. Currenlty selected are the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5. Additionally the port with the KB scan row GPIO point is also enabled to wake up the EC from deep sleep. Signed-off-by: Alec Berg <alecaberg@chromium.org> BUG=None BRANCH=none TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no noticeable side affects. Verified that the power consumed by the EC is lower when in S3, S5 and G3 by scoping the sense resistor powering the chip. Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726 Reviewed-on: https://chromium-review.googlesource.com/172183 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* stm32: Use DMA for UART receiveRandall Spangler2013-09-161-5/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STM32 has a single-byte mailbox for UART I/O. When the core clock runs at 16Mhz we can service interrupts fast enough to handle 115200 baud input, but when we drop to 1MHz we drop characters. Using DMA to receive input solves this problem. The STM32 DMA engine can only generate interrupts when the transfer is half-done / all-done, so we need to poll the DMA receive-head-pointer to see if individual characters have been received. Do this in the tick task (every 250ms). When a character is received, poll more quickly for a bit (5 times before the next tick) so the input console is more responsive to typing. BUG=chrome-os-partner:20485 BRANCH=none TEST=Console is responsive to debug commands. For example, help -> prints help apshutdown -> shuts down AP arrow keys -> move cursor and scroll through command history Ctrl+Q, help, wait a second, Ctrl+S -> help output printed after Ctrl+S Then in chip/stm32/config_chip.h, comment out #define CONFIG_UART_RX_DMA and rebuild/reflash the EC. When the AP is up, the console works normally but after 'apshutdown', the EC drops to 1MHz core clock, and the arrow keys don't work. (This step confirms that adding DMA support did not change the behavior of systems where CONFIG_UART_RX_DMA is not defined.) Change-Id: I199448354824bd747c7b290ea7fd5ccf354c11bb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169406 Reviewed-by: Simon Glass <sjg@chromium.org>
* Simplify uart_tx_start()Randall Spangler2013-09-141-5/+4
| | | | | | | | | | | | | | | | | | | All calls to it did if (uart_tx_stopped()) uart_tx_start(); And that was the only use of uart_tx_stopped(). Merge the functions. BUG=chrome-os-partner:20485 BRANCH=none TEST=EC debug console still prints output and accepts commands. Ctrl+Q pauses output and Ctrl+S resumes it. Change-Id: I113c64f5fdfc6b02b63034a74b1a3c6c6a76c351 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/169329 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* stm32: Support DMA-based UART outputRandall Spangler2013-09-111-8/+55
| | | | | | | | | | | | | | | This reduces the number of UART interrupts by a factor of 12, and reduces the overall interrupt rate on STM32 by a factor of 2. BUG=chrome-os-partner:20485 BRANCH=none (not required for pit branch) TEST=Boot pit. Ctrl+Q pauses debug output; Ctrl+S resumes it. 'crash divzero' still prints a full crash dump. And util/makeall.sh passes builds all platforms and passes tests. Change-Id: I86993e14b436150298dcb2c6d29086cc3c9db418 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168814
* Split uart_process() into input and output processingRandall Spangler2013-09-111-1/+2
| | | | | | | | | | | | | | This is a precursor to DMA-based UART transfers, which require different processing for DMA vs PIO output types. BUG=chrome-os-partner:20485 BRANCH=pit TEST=Boot pit; verify EC console still works. Change-Id: I6d6f55561eeebe9bd2928b2bfb25278c86f689d1 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168811 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Clean up configuring GPIO alternate functionsRandall Spangler2013-08-071-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO alternate functions used to be configured throughout the code, which made it hard to tell which ones you needed to configure yourself in board.c. It also sometimes (chip/lm4/i2c.c) led to GPIOs being configured as alternate functions even if they weren't used on a given board. With this change, every board has a table in board.c which lists ALL GPIOs which have alternate functions. This is now the only place where alternate functions are configured. Each module then calls gpio_init_module() to set up its GPIOs. This also fixes a bug where gpio_set_flags() ignored most of the flags passed to it (only direction and level were actually used). On stm32f, gpio_set_alternate() does not exist, and pins are configured via direct register writes from board.c. Rather than attempt to change that in the same CL, I've stubbed out gpio_set_alternate() for stm32f, and will fix the register writes in a follow-up CL. BUG=chrome-os-partner:21618 BRANCH=peppy (fixes I2C1 being initialized even though those pins are used for other things) TEST=boot link, falco, pit, spring Change-Id: I40f47025d8f767e0723c6b40c80413af9ba8deba Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64400
* Clean up and document UART config optionsRandall Spangler2013-07-241-6/+1
| | | | | | | | | | | | No functional changes, just renaming config options. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms Change-Id: I91584cb1f8990dd0f980abd32c04465a66243e71 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63244
* stm32: Add CHIP_FAMILY definesRandall Spangler2013-07-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, code which needed to work on all STM32F platforms needed to specify them by name (CHIP_VARIANT_stm32f100 || CHIP_VARIANT_stm32f10x), and we needed extra symlinks in the chip/stm32/ directory to allow the build system to find family-specific files. Add a CHIP_FAMILY level of abstraction, so that things which are common across all STM32F platforms don't need to specify every STM32F variant. Make the chip build look for family-specific filenames instead of variant-specific filenames (except for config*.h, which is actually variant specific). In the few places where things actually are variant-specific, keep using the existing CHIP_VARIANT defines. Code refactoring only; no functional changes. BUG=chrome-os-partner:20567 BRANCH=none TEST=build all platforms Change-Id: I1da831aadabf8b8dd9dfde423cac13c9f43eb953 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60247 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* stm32: Clean up register constants for uart moduleRandall Spangler2013-06-271-23/+19
| | | | | | | | | | | | | No functional changes, just cleanup. BUG=chrome-os-partner:20529 BRANCH=none TEST=ec console on uart still works Change-Id: I316ea2b069c47ed230169b74da4b3a8e71a383a8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/60177 Reviewed-by: Vic Yang <victoryang@chromium.org>
* pit: Support changing EC clock frequencyRandall Spangler2013-06-251-10/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modules which care about system clock frequency now hook HOOK_FREQ_CHANGE. - hwtimer - i2c - uart (which is now also smart enough to use x8 oversampling instead of x16 when the system clock is too slow to support x16) Added 'clock' debug command to set system clock frequency. STM32F platforms don't change clock frequency; on those platforms, clock_get_freq() simply returns CPU_CLOCK, so behavior of those platforms is unchanged. BUG=chrome-os-partner:20414 BRANCH=none TEST=from EC console: - reboot ap-off -> to make sure AP is off during testing - clock msi2 -> reports 2MHz clock - battery -> reports battery info - clock msi1 -> reports 1MHz clock - battery -> reports battery info - clock hsi -> reports 16MHz clock - battery -> reports battery info - power on -> AP powers on and host commands succeed Change-Id: Ib8276bf124727e4fb502297ca8b3d6d4b6170241 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59645
* Clean up UART moduleRandall Spangler2012-10-301-3/+1
| | | | | | | | | | | | | | And change some direct uart_printf()/uart_puts() output to console output methods instead. Disable unused comxtest debug command. No other functional changes. BUG=chrome-os-partner:15579 BRANCH=none TEST=boot system; should still see debug output with reset flags Change-Id: I57fe6bb781a1ba7884afa6d090b74a92f45a53cc Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36835
* Change UART interrupt to priority 2Simon Glass2012-09-051-1/+1
| | | | | | | | | | | | | | | The UART probably shouldn't have such a high priority. Reduce it to below that of comms driver interrupts. BUG=none BRANCH=none TEST=manual Boot and see that UART console still functions Change-Id: If906c9c4c37617d076ad8415d126b50f52d8b09e Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/32077 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f100: implement low power modeVincent Palatin2012-08-091-0/+3
| | | | | | | | | | | | | | | | | | | | | When the AP is not running and we have enough time go to STOP mode instead of simple idle. The EC consumption should drop from 12mW to a few mW. This is currently not activated by default, you need to type "sleepmask 0" in the EC console to activate it. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8866 TEST=on Snow, check the software is still working properly when STOP mode is activated and measure power consumption on 3v_alw rail. Change-Id: I231d76fe6494c07b198c41694755b82d87c00e75 Reviewed-on: https://gerrit.chromium.org/gerrit/29315 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* Remove unused UART definesRandall Spangler2012-07-091-6/+0
| | | | | | | | | | | | | No longer needed since the rewrite of the panic handler in C. BUG=none TEST=link and snow still compile Change-Id: Ib790004ae4d0ba11f0800e85e14ea372a53025f8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26890 Reviewed-by: Che-Liang Chiou <clchiou@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* introducing chip variant for stm32 family [3/3]Vincent Palatin2012-05-011-0/+4
| | | | | | | | | | | | | Add STM32F support. Based on David's changelist. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: Ide817d11480f0b56f67deaae3c08bc631f605075
* introducing chip variant for stm32 family [1/3]Vincent Palatin2012-05-011-0/+150
just rename STM32L to STM32. Most of the STM32L15x code is common with STM32F1xx. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: I819eff5fcd23deff57f5f6dedcf37e6c421b96c2
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