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* pd: cleanup pd_get_roleDenis Brockus2020-01-091-1/+1
| | | | | | | | | | | | | | | | | | pd_get_role in the TCPMv1 stack meant pd_get_power_role. pd_get_role in the TCPMv2 stack meant pd_get_data_role. This CL will clean that up and make them the correct naming. pd_get_power_role will also return an enum pd_power_role type instead of an int. BUG=b:147290482 BRANCH=none TEST=make buildall -j Change-Id: I73ee465401ccd050c2bd151f2fc043a59d95e079 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1991844 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Add a board specific helper to return USB PD port countKarthikeyan Ramasubramanian2019-11-091-1/+1
| | | | | | | | | | | | | | | | | | | | | Certain SKUs of certain boards have less number of USB PD ports than configured in CONFIG_USB_PD_PORT_MAX_COUNT. Hence define an overrideable board specific helper to return the number of USB PD ports. This helps to avoid initiating a PD firmware update in SKUs where there are less number of USB PD ports. Also update charge manager to ensure that absent/ invalid PD ports are skipped during port initialization and management. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and garg(2A + 1C + 1HDMI config). Change-Id: Ie345cef470ad878ec443ddf4797e5d17cfe1f61e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879338 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-011-5/+6
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chocodile_vpdmcu: Firmware for chocodile mcuSam Hurst2019-04-081-0/+11
| | | | | | | | | | | | | | | | | | Implement Chocodile Charge-Through Vconn Powered firmware for mcu using new Type-C/PD State machine stack. BUG=b:115626873 BRANCH=none TEST=manual Charge-Through was tested on an Atlas running a DRP USB-C/PD state machine with CTUnattached.SNK and CTAttached.SNK states. Signed-off-by: Sam Hurst <shurst@chromium.org> Change-Id: I847f1bcd2fc3ce41e66edd133a10c943d5e8c819 Reviewed-on: https://chromium-review.googlesource.com/1225250 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Stefan Reinauer <reinauer@google.com>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-6/+6
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* pd: remove unnecessary delay in phy initAlec Berg2015-10-231-1/+1
| | | | | | | | | | | | | | Remove unnecessary 250ms delay in USB PD phy init BUG=none BRANCH=none TEST=test on glados and samus. verify we negotiate with zinger after EC or PD reboots. Change-Id: I561e41fb0b8bbfeacdd7d6a9ceaf67a1606f65e5 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308535 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: Cleanup usb_pd low power idle sleep maskShawn Nematbakhsh2015-10-061-2/+6
| | | | | | | | | | | | | | | | | | | | | | | Add a new define CONFIG_USB_PD_LOW_POWER_IDLE_WHEN_CONNECTED that indicates the chip should try to go to low power idle even when a PD connection is established -- this is the current behavior only for Zinger. Also, enable and disable the sleep mask bit from tcpc on rx enable / disable. BUG=chrome-os-partner:45010 TEST=Manual on glados / glados_pd. Insert Zinger, verify that glados_pd stays out of low power idle. Remove Zinger, verify that glados_pd resumes going into low power idle. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie763ae75f4459f56cad47d77d9c25d76358aa484 Reviewed-on: https://chromium-review.googlesource.com/303490 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* tcpc: disable TX timer as early as possible after DMA doneAlec Berg2015-06-131-3/+3
| | | | | | | | | | | | | | | | Move disabling the TX timer up to as soon as possible after DMA transmit is complete to avoid potentially clocking another bit, which could corrupt the end of the transaction. BUG=none BRANCH=smaug TEST=load on glados and use a scope to verify the end of transmit is clean. Change-Id: If52ba2475eeb9752da0acc8efc957c1f472bc711 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277298 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tcpc: change pd_tx_done() to only wait for DMA done eventAlec Berg2015-06-131-5/+1
| | | | | | | | | | | | | | | | | | Change pd_tx_done() to wait specifically for the DMA complete event using task_wait_event_mask(). This fixes a potential bug where if we get another event, for example a TCPM event, while waiting for transmit to complete we restore the pending event after we are done. BUG=none BRANCH=smaug TEST=run on glados and make a bunch of contracts with zinger. Change-Id: Ie28d97eba3edcc7a98fe842e8b7eb6b9d7707047 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277297 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* oak: Add PD communication to oakAlec Berg2015-05-301-0/+2
| | | | | | | | | | | | | | | | | | Add TCPM on EC side and TCPC on PD side to allow PD communication. Enable PD communication on port 0. BUG=none BRANCH=none TEST=load on oak. plug in hoho on port 0, and make sure we successfully negotiate a PD contract. (note: you have to manually enable 5V VBUS right now) Change-Id: I0ce7c016545bc56c5e10f66b49b73722187f12dc Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/271829 Reviewed-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Sheng-liang Song <ssl@chromium.org> Commit-Queue: Sheng-liang Song <ssl@chromium.org>
* pd: move non-phy layer config out of usb_pd_config.hAlec Berg2015-05-271-6/+6
| | | | | | | | | | | | | | | | | | | | | Move parts of usb_pd_config.h that are not part of the phy layer out of usb_pd_config.h and into board.h. This cleans up the division between the TCPC and TCPM as only the TCPC needs to use usb_pd_config.h. Also cleans up the use of the CC detection voltage thresholds by creating standard macros to use based on Rp strength for the board. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I946cceb38bea8233095b8a4b287102bb8a3a296d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270337 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: cleanup PD receive error enumAlec Berg2015-04-291-2/+2
| | | | | | | | | | | | | | Cleanup PD receive error enum by including RX in name since we will have a different enum for TX errors. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I355092e0e73a022acb4a92736374cd2289d324bf Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/267670 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: ignore cable resetAlec Berg2015-04-241-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Identify and ignore cable reset PD command BUG=chrome-os-partner:39464 BRANCH=samus TEST=connect two samus'. on one samus add code to send a cable reset like such: int send_cable_reset(int port) { int off; CPRINTF("C%d Send cable reset\n", port); /* 64-bit preamble */ off = pd_write_preamble(port); /* Hard-Reset: 3x RST-1 + 1x RST-2 */ off = pd_write_sym(port, off, BMC(PD_RST1)); off = pd_write_sym(port, off, BMC(PD_SYNC1)); off = pd_write_sym(port, off, BMC(PD_RST1)); off = pd_write_sym(port, off, BMC(PD_SYNC3)); /* Ensure that we have a final edge */ off = pd_write_last_edge(port, off); /* Transmit the packet */ if (pd_start_tx(port, pd[port].polarity, off) < 0) { pd[port].send_error = -5; return -5; } pd_tx_done(port, pd[port].polarity); /* Keep RX monitoring on */ pd_rx_enable_monitoring(port); return 0; } Without this CL, the receiving samus times out and ends up causing equivalent of hard reset. With this CL, we receive cable reset and drop it. Also used twinkie to measure goodCRC delay. No measureable change in delay on samus and zinger. Samus delay is ~70us and zinger delay is ~65us. Change-Id: Ic0e871c8cf96502b861f430e05ee145881fb55fa Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/266981 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* twinkie: add simple text tracing mechanismVincent Palatin2015-04-101-50/+63
| | | | | | | | | | | | | | | | | | | | | | When using the Twinkie dongle without a protocol decoder on the host, add a simple text tracing mechanism, so the user can get the timestamped traces of the packets on the wire (in a best effort fashion). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=On Twinkie command-line, type "tw trace on" then plug a DingDong to Samus through Twinkie and see the PD message traces on the console. Change-Id: I4fa35d6783cc6279c95209c86f37e6d717de7301 Reviewed-on: https://chromium-review.googlesource.com/237222 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* pd: Modify BIST mode according to ECR#PD2.0.1.0.004Scott2015-04-091-7/+22
| | | | | | | | | | | | | | | | | | | | | | - Changed TX BIST mode so that it transmits for 50 msec instead of transmitting forever. - Added console command to initiate TX BIST mode. - Fixed an issue with circular DMA mode which was causing watchdog. - Modified RX BIST to account for shorter TX BIST duration. BUG=chrome-os-partner:36335 TEST=Manual on Samus to Samus, manual on Zinger to Samus BRANCH=Samus Signed-off-by: Scott Collyer <scollyer@chromium.org> Change-Id: I666347de47c81b5b7a1e82c2b99345ff3ebbb7d4 Reviewed-on: https://chromium-review.googlesource.com/256194 Tested-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Trybot-Ready: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* pd: Massage initialization at task start.Todd Broch2015-02-251-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Refactoring effort to unify the set of PD intialization tasks that need to occur. Those areas include: 1. host mode as it relates to power & pull-ups/downs 2. PD tx init 3. PD mux settings Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=samus BUG=chrome-os-partner:36481 TEST=manual, 1. compiles and functions on samus_pd 2. If sysjump w/ dongle connected than alternate mode re-entered properly including muxing and HPD Change-Id: I47f32acaeccbd7745e1e01a8b085b1804c4c5000 Reviewed-on: https://chromium-review.googlesource.com/249273 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* stm32: Add delay after enabling peripheral clockVic Yang2015-02-101-0/+4
| | | | | | | | | | | | | | | | | We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* samus: pd: fix potential junk at end of tx transmissionstabilize-6670.BAlec Berg2015-01-091-64/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fix potential junk at end of PD TX transmit by adding to the DMA transmit complete interrupt a blocking wait for SPI to finish and then immediately disable SPI clock. This means we block in an interrupt function for approximately 45us at the end of every transmit. But, this is the highest priority thing going on anyway. Note, there is still a potential for junk if both ports are transmitting at the same time and finish very close to the same time. BUG=chrome-os-partner:34600 BRANCH=samus TEST=load onto samus and test communications with zinger. tested specifically with an old zinger CL, https://chromium-review.googlesource.com/#/c/226118/11, which watchdogs when samus has junk at end of transmit. Tested without this CL and verified we could never successfully flash zinger over PD due to this watchdog and verified on scope presence of junk. Then tested with this change and was able to successfully flash zinger using ectool on both ports in both polarities. Change-Id: If0cd9ab0551d36a7d7dc10232b6476dd56735972 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/239244 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: check for collisions before transmittingAlec Berg2014-12-171-11/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added check for collision just before transmitting on CC line. To check for collision, RX monitoring is left on all the time (except when in the act of receiving or transmitting, or in between receiving and sending a goodCRC), and a simple check for RX transmission started is used to see if the CC line is idle or not. RX monitoring is also changed to only trigger on 3 edges within 20us, as per the PD spec. When a collision is detected by seeing that CC is not idle, the transmitting packet is dropped. BUG=chrome-os-partner:30135 BRANCH=samus TEST=load onto samus and zinger. make sure we negotiate and make sure custom VDMs succeed. enabled pings and made sure we stay alive with pings for a few min. Also added code to pd_rx_handler to toggle a test point on EVT board to verify the timing of when we get RX interrupts: Change-Id: I22d172163319437d3d901e019eda79d4d592f6b8 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/226118 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Twinkie: add packet injection capabilityVincent Palatin2014-11-181-6/+7
| | | | | | | | | | | | | | | | | | | | | | | Add commands to send PD packets and to tweak individual parameters (TX clock frequency, RX detection threshold, resistors on CCx). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28337 TEST=verify that the PD sniffing is still working by dumping traffic between Zinger and Samus. Connect Twinkie to Zinger, set Rd by using "tw res NONE RD" and see VBUS going to 5V (reading it using "ina 0"). Send a BIST mode 2 request using the following command : tw send 2 0x1043 50000000 and see the other end starting sending BIST. Change-Id: I3c8ddf858435ac1c17a43f59351bbaa69603a209 Reviewed-on: https://chromium-review.googlesource.com/227778 Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* Add new build target ryu_p2 for Ryu P2 boardsVic Yang2014-10-221-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | The new build target ryu_p2 is mostly based on ryu. On ryu_p2, we have a new EC chip with bigger flash, so make the corresponding changes: - Pinout changes - HW Timer: TIM5 - USB PD Tx Timer: TIM3_CH4 - USB PD Rx Timer: TIM2_CH4 - Use UART2 for EC console - Disable UART Tx DMA as it conflicts with USB PD Tx DMA - Use 24MHz HSE x2 = 48MHz for SYSCLK BRANCH=None BUG=chrome-os-partner:32660 TEST=Sanity check on a new board: - i2cscan - PD negotiation - UART console - gettime Change-Id: I4ef6b53a928a2777721e3874032aeb0e6b2b4c92 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221404 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: allow selection of Tx timer channelVic Yang2014-10-211-8/+16
| | | | | | | | | | | | | | | | So far, we always use channel 1 of the Tx timer and the configuration code is hard coded. We need to support other channels for new Ryu boards. Let's make this a configurable bit. BRANCH=samus BUG=chrome-os-partner:32660 TEST=make buildall TEST=Plug in Zinger to Ryu and see 20V come up. Change-Id: Id08d4eb0d6a5721d8a03672484d0892a0714383b Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/223836 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add support for STM32F373Vic Yang2014-10-071-2/+2
| | | | | | | | | | | | | | | | | | | This mostly reuses chip drivers for STM32F and STM32F0. Since this chip doesn't fit either STM32F or STM32F0, let's use symlink to specify which drivers to use for STM32F3. This is just the preparatory work and it's not verified on a chip yet. BUG=chrome-os-partner:32660 TEST=make buildall to make sure this doesn't break anything BRANCH=None Change-Id: I709ed49265e8f84552251a97d03b9b98496de99e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221412 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* zinger: minimuffin: add board support for minimuffinAlec Berg2014-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Minimuffin is identical to zinger, same MCU, same gpio, same circuitry aroundt the MCU with two differences: - Rated current is 2.25A instead of 3A - USB PD hardware device ID needs to be different so that host can differentiate between the two. Due to the similarity between the two, minimuffin is defined as a symlink to the zinger board. BUG=none BRANCH=samus TEST=make BOARD=minimuffin load onto a zinger and verify that samus reads device ID correctly and limits input current limit to 2.25mA. Change-Id: Ie39ec43262c7d14663eb68abff073bfeec451a24 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/220689 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: use interrupt on Rx retryVic Yang2014-08-111-2/+2
| | | | | | | | | | | | | | | | | After sending a message, we wait for up to 2.7 ms for reply. If we don't get one, we retry for up to twice. Therefore, a undelivered message could take up to >8ms. To prevent starving other tasks, let's yield to other tasks on retries and rely on interrupt to wake us. BUG=chrome-os-partner:28341 TEST=Plug in zinger on port 0 and C-to-A dongle on port 1. Check that port 0 drops connection less frequently. BRANCH=None Change-Id: If85a70fd1140fef69d79243b198703ce601f8030 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/211281 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* samus: pd: dual USB-PD port support for samusAlec Berg2014-07-281-157/+167
| | | | | | | | | | | | | | | | | | | | | | | | | Adds dual USB-PD port support for samus. Both ports are in dual-role and can perform either role. Both ports work fine when only one of the ports is in use. But, still having problems with PD errors on the lower priority port (port 0). If you have a charger plugged into port 0, and a type-C USB dongle plugged into port 1, then port 1 has higher priority, and in the SRC_DISCONNECTED state, every 1.5 seconds when it sends source cap packet, we occasionally drop pings on port 0, which results in a lot of start/stop charging. BUG=chrome-os-partner:28585 BRANCH=none TEST=Tested on samus to make sure both ports work when I plug in a charger and a type-C USB dongle with a pull-down on the CC line. Tested on plankton and zinger to make sure PD works as expected. Change-Id: Ie7bde3e258f5cd23a0b82b626c0993a45b0df074 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200750 Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* pd: clean up beg/end transitions of PD commsAlec Berg2014-07-031-40/+79
| | | | | | | | | | | | | | | | | | Fix the beginning and end of BMC PD communication: - Initial transmission within 1us of taking control of CC line - CC line released between 1us and 23us after last edge - If final bit is a 0, then add two 1 bits to the end - No garbage after the final bit BUG=chrome-os-partner:30132 BRANCH=none TEST=tested with a fruitpie, samus, and zinger. verified timing on scope. Change-Id: Ie45695eb367a7554cf5d5b76b6fbdf1e3fc85d29 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/206453 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: add support for suspending the taskDominic Chen2014-07-021-0/+8
| | | | | | | | | | | | | | used by usb debug, which uses the same spi port BRANCH=none BUG=none TEST=verify PD communication works after suspend with two fruitpies Change-Id: I9d7e963fc27dc5303a8b87a9ddb68e97600a5a10 Signed-off-by: Dominic Chen <ddchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/202992 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* IRQ list support for enabling specific IRQs without common runtimeVic Yang2014-06-191-0/+2
| | | | | | | | | | | | | | | | | | | This adds back DECLARE_IRQ() support when building without common runtime. With this, we can enable only a subset of IRQs and avoid linking in other unused IRQ handlers. Note that after this change, all boards without common runtime need to have a ec.irqlist file. BUG=None TEST=Build Keyborg and check it still works. TEST=make buildall BRANCH=None Change-Id: If68062a803b9a78f383027a1625cf99eb3370d3f Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/203264 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: support bist carrier mode 2Alec Berg2014-06-031-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | Support bist carrier mode 2 - continuously transmit alternating 1's and 0's, and check for bit errors on receive side. note that once the test is started the only way to stop is to hard reboot the devices involved. BUG=none BRANCH=none TEST=connect two fruitpies together. set one to be source: > pd charger and then start the bist > pd bist start receiving data: aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa - incorrect bits: 0 / 0 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 55 - incorrect bits: 0 / 0 Change-Id: Id920f6b7177a418a80e1ce325042243cd633cec6 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/202187 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add SPI register definitions and refactorDominic Chen2014-06-031-3/+3
| | | | | | | | | | | | | refactor existing code in usb_pd_phy.c to use new register definitions BRANCH=none BUG=none TEST=manually verify macro substitutions produce same value Change-Id: Ia0cd815164b0262640425abd6da973c170163f2f Signed-off-by: Dominic Chen <ddchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/202392 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add cprints() and ccprints()Vic Yang2014-05-211-4/+6
| | | | | | | | | | | | | | | | | | | | | Our code base contains a lot of debug messages in this pattern: CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n") The strings are taking up spaces in the EC binaries, so let's refactor this by adding cprints() and ccprints(). cprints() is just like cprintf(), except that it adds the brackets and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...) This saves us hundreds of bytes in EC binaries. BUG=chromium:374575 TEST=Build and check flash size BRANCH=None Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200490 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: add square brackets to make test parser easierLouis Yung-Chieh Lo2014-05-071-4/+4
| | | | | | | | | | | | | | | | This may not contain all. I filtered out possible code by the following command: find . -name "*.h*" -o -name "*.c*" | xargs grep -n CPRINTF | \ grep -v "\[" | grep -v define | less BUG=none BRANCH=none TEST=make buildall tuntests Change-Id: I674f84f5966b34aeb8d4321d22629b450627a120 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197997
* pd: more robust receptionVincent Palatin2014-05-021-0/+6
| | | | | | | | | | | | | | | | | | Ensure that we finish reception if and only if we started it whatever other events happened. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28332 TEST=Connect Zinger to Firefly, request higher voltage and ensure that Firefly was still getting the Pings after several hours. Change-Id: Ie99984aeb4c565be39d349457dbd2813203b3f5b Reviewed-on: https://chromium-review.googlesource.com/197946 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* pd: handle plug polarityVincent Palatin2014-04-301-10/+14
| | | | | | | | | | | | | | | | | | | | Use the plug polarity detected by the ADCs to do the PD communication on the right CCx line. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28339 TEST=make buildall on Firefly, plug Zinger connector in both direction and see it can control it either way. on Fruitpie, use CC1 or CC2 and see it can communicate on both. Change-Id: I81cb00f164cb8194fba73b383014e81c37d975e2 Reviewed-on: https://chromium-review.googlesource.com/197520 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* pd: update policy, timeout and board callbacksVincent Palatin2014-04-301-10/+1
| | | | | | | | | | | | | | | | | | | | | | | Slightly modify interfaces for better sink-only devices implementation (eg Firefly) update the host mode management and the voltage selection and add a hook for board checks. Simplify the reception timeout and fix other timeout detections. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall and use with the follow-up firefly board configuration CL. Change-Id: I0240295764c8605793dc80a2fc21357af1740744 Reviewed-on: https://chromium-review.googlesource.com/195585 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: pd: add config option to use SPI master for USB PD trasmitAlec Berg2014-04-291-8/+46
| | | | | | | | | | | | | | | | | | | | | | | Added config option CONFIG_USB_PD_TX_USES_SPI_MASTER which switches to use SPI master for PD transmit. The advantage of SPI master mode is at the end of the tranmission, we don't have to send any dummy 0 bits. When the option is set, the CPU_CLOCK must be set to 38.4MHz, so that the SPI master can generate the correct clock frequency. BUG=chrome-os-partner:28309 BRANCH=none TEST=Tested by connecting two fruitpies together across CC1. One fruitpie has been modified such that the MISO and MOSI lines are swapped and is running PD TX in SPI master mode with 38.4MHz clock, while the other is running PD TX in SPI slave mode. On EC console ran pd charger on one board and pd dev on other board. Verified that communication works with no errors. Ran for 10 minutes in each configuration. Change-Id: Ib24030d34d95d59f4ac6c2dae98bf7adda1ada01 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197215 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: USB Power Delivery physical layerVincent Palatin2014-04-121-0/+495
Implementation of the physical layer for USB Power Delivery communication using the STM32 chip. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: I2a4adeef572b97a284bf52ab9d14d23246c56d18 Reviewed-on: https://chromium-review.googlesource.com/189867 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
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