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* Bloonchipper: USART based transport layer for host commandBhanu Prakash Maiya2020-06-0512-17/+1008
| | | | | | | | | | | | | | | | | | | | 1. USART host command layer in chip/stm32 2. Fix usart implementation in stm32 BUG=b:147849609 BRANCH=none TEST=1. make BOARD=bloonchipper -j 2. usart request and response works on dragonclaw Change-Id: Idd89d3e490f23aa528ecaf6510c13d16b405de13 Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2190531 Tested-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
* servo: Add USB SPI helper functions and context statesBrian J. Nemec2020-06-052-86/+325
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds context states to USB SPI for handling receiving and transmitting data. These context states allow us to keep track of data buffers that can not fit within a single USB packet. A context state has been added to describe the USB packets accepted by the USB SPI protocol. This structure includes union fields for easily addressing the different packet's fields and to describe the basic attributes for a USB packet including its size and how many bytes are allocated to the header. Helper functions process the USB packets and aid in the transfer of data between them and receive and transmission buffers. BUG=b:139058552 BRANCH=servo TEST=Tested with Servo Micro reading and verifying flash writes are successful in a loop. Signed-off-by: Brian Nemec <bnemec@chromium.org> Change-Id: I3e0b31f33f442719123b9e897495cad25e9e6ed4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224764 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org>
* ec: Minor cleanup of magic number commonly used in STM32 USBBrian J. Nemec2020-06-045-4/+8
| | | | | | | | | | | | | | | | | Minor cleanup of a commonly used magic number in the STM32 USB interface. BUG=none BRANCH=none TEST=Builds Signed-off-by: Brian Nemec <bnemec@chromium.org> Change-Id: I2c0b7947810aae651e452db42ac27221ab19b99b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224763 Tested-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org>
* chip/stm32: Don't reset the backup domain when initializing clockYicheng Li2020-06-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | For the STM32F4 chip family, this software reset of the backup domain causes the RTC backup registers to be reset, which causes all backup data to be lost. The reset flag was not impacted because it's copied out before this reset. BRANCH=none BUG=b:157059753 TEST=make -j BOARD=bloonchipper test-scratchpad On console: > runtest => PASS > reboot > runtest => FAIL, which is CORRECT Signed-off-by: Yicheng Li <yichengli@chromium.org> Change-Id: I85777b7d8a99561198d0b9dc1f795b8f8f6e26c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226955 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Tom Hughes <tomhughes@chromium.org>
* stm32: Disable option bytes if RO is protected on bootTom Hughes2020-05-302-5/+12
| | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:155897971 TEST=On bloonchipper after flashing flash_write_protect.bin test: * Enable HW WP: dut-control fw_wp_en:on * Reboot to RO: reboot ro * Enable flash protection: runtest 1 => PASS * Reboot to RO: reboot ro * Try to disable flash protection: runtest 2 => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ie7bc4d8b518ef1387f77666072a510a8fbfb1d90 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220738 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* test: Add tests for flash option bytes and control registerTom Hughes2020-05-301-0/+6
| | | | | | | | | | | | | | | BRANCH=none BUG=b:155897971 TEST=On dragonclaw v0.2 with Segger J-Trace and servo micro attached: ./test/run_device_tests.py -t flash_physical => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I9a71cdcc2947d13cf2f1d44fdbd57cf20ed6402f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220737 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32: Add helper functions for flash control registersTom Hughes2020-05-303-28/+154
| | | | | | | | | | | | | | | | | | | | No functional change. Improves readability and allows re-use for validation in unit tests. BRANCH=none BUG=b:155897971 TEST=On dragonclaw v0.2 with Segger J-Trace and servo micro attached: ./test/run_device_tests.py -t flash_physical => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ib06fb483f5936dd09e6a39ef515d8b2cbff747e4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220735 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/stm32: Save STAY_IN_RO flag if set during resetTom Hughes2020-05-141-0/+4
| | | | | | | | | | | | | | | This matches the behavior of system_encode_save_flags() and allows us to reboot into RO for testing. BRANCH=none BUG=b:156401765 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibbb95ca81fb87eaa48639dea99be1bd0e35ea230 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2197621 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* stm32: Add chip_read_reset_flags and chip_save_reset_flagsDaisuke Nojiri2020-05-061-3/+13
| | | | | | | | | | | | | | | | | | | | | Battery backed up RAM is used to store the reset flags. This patch wraps the code reading and writing the reset flags with APIs for the consistency and make it available to external callers. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1078470 BRANCH=none TEST=buildall Change-Id: Ica31008b8f0f89f6804002c2c796e3b3c117e06a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182563 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* test: Add on-device unit test for STM32 RTCTom Hughes2020-04-301-0/+1
| | | | | | | | | | | | BRANCH=none BUG=b:151105339 TEST=make BOARD=bloonchipper test-stm32f_rtc -j Flash stm32f_rtc.bin and "runtest" in the console Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I3debfd93b62cb269ad61af0e4ca7e195554b5548 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171569 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* c2d2/servo_micro: invert SDA during ITE programming seqJett Rink2020-04-162-2/+8
| | | | | | | | | | | | | | | | | | | According to programming guide, the SDA signal (200kHz) should have its rising edge in the middle of the SCL (100kHz) transition. Since the timers are starting at the same time, inverting the SDA timer will achieve this. This will affect both servo_micro and c2d2 BRANCH=servo BUG=b:153393490 TEST=verify with scope on C2D2 is SDA/SCL signals match programming guide Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: Ibda89a30f77d39c633f491840b82f7b1dee552c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142561 Reviewed-by: Matthew Blecker <matthewb@chromium.org>
* ec: Enlarged Task Stack size on platformsBrian J. Nemec2020-04-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The task stack size of is small enough that the process was triggering stack overflows when responding to commands. These actions had a small chance of causing EC hardfaults. This was apparent with the gpioget command which had the attributes of performing many calls to a printf function which also has many parameters. Since the structure of a printf with 10 or more parameters is common when constructing console responses, this enlarges the stack for that task. This is more important since the probability of it creating a hardfault is low. To reduce the chance of this issue on other platforms, the platforms with 488 byte tasks were also enlarged to 512 bytes. BUG=chromium:1056780 BRANCH=none TEST=Connected servod to servo_v4 looped the command 'dut-control servo_v4_uart_cmd:gpioget' 1000 times TEST=make buildall -j Verified free ram space remains over 60 bytes on impacted platforms Change-Id: I6b50b204c83a10068153f3e01bc134446047f235 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2133130 Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cleanup: drop the _TYPEC part of USB device configJett Rink2020-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The three USB device configurations describe more than just the Type-C layer, so remove the _TYPEC part within the define. This is also in preparation to change how the usbc build.mk includes files. This was performed with the following commands: $ git grep --name-only CONFIG_USB_TYPEC_DRP_ACC_TRYSRC | xargs perl -i -ple 's/CONFIG_USB_TYPEC_DRP_ACC_TRYSRC/CONFIG_USB_DRP_ACC_TRYSRC/g' $ git grep --name-only CONFIG_USB_TYPEC_CTVPD | xargs perl -i -ple 's/CONFIG_USB_TYPEC_CTVPD/CONFIG_USB_CTVPD/g' $ git grep --name-only CONFIG_USB_TYPEC_VPD | xargs perl -i -ple 's/CONFIG_USB_TYPEC_VPD/CONFIG_USB_VPD/g' BRANCH=none BUG=none TEST=builds Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I4deab784b7c3479cffd3dee7fb3ea3c8a9d6081c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2121193 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* stm32f412: Fix chip config Flash and RAM sizesCraig Hesling2020-03-242-4/+13
| | | | | | | | | | | | | | | | | | We are already using the stm32f446 config for many F4 based chips. Let's actually make this more clear and un-hack our hatch_fp board.h. This present no functional change. BRANCH=none BUG=none TEST=./util/compare_builds.sh -b "hatch_fp sweetberry" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I6b46e696686ad740833dc889c1db5d7bac84a768 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2109244 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* stm32: Refactor clock-stm32h7.cCraig Hesling2020-03-201-70/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This cleans up and modularizes the clock configuration code for the STM32H743. This makes it easier and cleaner to add the STM32H7A3 variant. This brings no functional change, as coarsely verified with crrev.com/c/2096017 . BRANCH=icetower BUG=b:130296790 TEST=Verified all impacted registers values with and without this change using crrev.com/c/2096017 on the Nucleo-H743ZI. The sequence of commands used to test was the following: # After fresh startup (from reset) * > clock * > clock hsi * > clock pll * > clock hsi * > clock hsi * > clock * > waitms 5000 * # Run timer to check accuracy of 5 seconds * > clock pll * > waitms 5000 * # Still broken -> Watchdog should still kick-in early and render MCU unusable. Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4fbf6982190c0d660e31c2027b5ad07cae48755e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2095853 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* chip: stm32: fix TIM9 interrupt for STM32F412Virendra Kakade2020-03-201-0/+4
| | | | | | | | | | | | | | | | | | | | | Currently the TIM9 global interrupt is mapped to 25 instead of 24 which causes the interrupt to not work. Fix this by changing the mapping. RM0402 STM32F412 reference manual: Vector table for STM32F412xx (table 40); TIM1_BRK_TIM9 entry. BUG=none BRANCH=none TEST=make -j4 buildall TEST=TIM9 interrupt works after this change on STM32F412 board. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com> Change-Id: I18ee7cda79e78c01bc561b1d70d2a25fa3aed5a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2098872 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org> Tested-by: Craig Hesling <hesling@chromium.org>
* stm32: pwm: fix timer PSC register calculationVirendra Kakade2020-03-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | The timer PSC register value is calculated based on the cpu clock frequency but it should actually be based on the timer clock frequency. Timer clock frequency and cpu clock frequency may be the same or different based on the STM32 variant. Example: In the STM32F412 case, timer freq = cpu freq * 2. This leads to incorrect PSC calculation based on old formula, ultimately leading to a frequency twice that of requested. BUG=none BRANCH=none TEST=make -j4 buildall TEST=verified that I got expected frequency on a stm32f412 pwm output with this change. Change-Id: I9ff954cf6304507f7506f5cf974857f6c3140b4e Signed-off-by: Virendra Kakade <virendra.kakade@ni.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2096841 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32: Fix manual interrupt clearing functionCraig Hesling2020-03-121-1/+3
| | | | | | | | | | | | | | | | | | | This fixes a bug in gpio_clear_pending_interrupt, where all pending interrupts are unintentionally cleared. This is not in the code path for normal gpio interrupt handlers, since the normal interrupt clearing occurs in gpio_interrupt (right below this function). BRANCH=none BUG=chromium:1059520 TEST=none Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4d6fe7947f4d76cf3b57dfbf3bb926e41851c80c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2101208 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* c2d2: add support for I2C-based flashingJett Rink2020-02-272-4/+22
| | | | | | | | | | | | | | | | Add necessary console command to allow C2D2 to pass through i2c bus for ec and ap. Also hook into common ite programming mode code. BRANCH=servo BUG=b:148610186,b:147381671 TEST=flash ampton with C2D2 adapter Change-Id: I1d9b20684b45ff0d101b9cfff8b0b0a85e6c0c70 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064594 Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Matthew Blecker <matthewb@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* cleanup: tab over register valuesJett Rink2020-02-251-20/+20
| | | | | | | | | | | | | | Tab over register values underneath the register definition for consistent style. BRANCH=none BUG=none TEST=none Change-Id: I823a454fc57d4ee455c9efb693baff8838bc7d3c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2067158 Reviewed-by: Diana Z <dzigterman@chromium.org>
* cleanup: move voltage rail detection to commonJett Rink2020-02-251-3/+17
| | | | | | | | | | | | | | Single source the VDD rail sagging reset interrupt Add VDD detection to C2D2 as well. BRANCH=servo BUG=none TEST=builds Change-Id: Iceac7d9fa7a9bde5a3c23c36e63b6d635d8812a3 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064593 Reviewed-by: Diana Z <dzigterman@chromium.org>
* servo_micro: move ite flashing codeJett Rink2020-02-252-0/+336
| | | | | | | | | | | | | | | | In preparation for servo_micro and c2d2 to sharing the ite, i2c flashing code, move it to a stm specify common file. It is STM specific because it explicitly uses STM registers to accomplish the non-compliant i2c waveforms needed to put the ITE EC into flash mode. BRANCH=servo BUG=b:148610186,b:79684405 TEST=flash ampton with servo_micro using this code Change-Id: Ia0f3f944df2f8a8ad47ea5a62c5f0edae2c71943 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064592 Reviewed-by: Diana Z <dzigterman@chromium.org>
* Servo: Adds persistent storage of MAC addressBrian J. Nemec2020-02-211-0/+58
| | | | | | | | | | | | | | | | | | | | | | | Adds a field to the persistent storage to store the MAC address of the device. This is enabled on ServoV4 in order to store the MAC address for the integrated ethernet port. Added a console command to set and load this value. BUG=b:149506580 TEST=Verified setting and loading the MAC address using: 'macaddr set 12:34:56:78:90:ab' and 'macaddr' or 'macaddr load' Verified that MAC addresses over 19 characters long return an error response and not update the MAC. Verified no set serial number will return the uninitialized string. Verified that the MAC address can be updated independently of serialno Verified that the persist_state fields restore during firmware updates Change-Id: I8425ce9e13322e99a4f59df444ea0dc73821aa6b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2063330 Tested-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Brian Nemec <bnemec@chromium.org>
* chip/stm32: Add explanation for previous STOP mode bug.Yicheng Li2020-02-191-4/+3
| | | | | | | | | | | | | | Commit a6c2477aca71c0dd3aed21d34009aecf056a6f4a fixed a bug in STOP mode. This commit adds more explanation of what was happening. BUG=b:140538084 BRANCH=none TEST=none Change-Id: Ibfca1884aef4fabf8f74238b3ff1f70d5e0da3dd Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1922912 Reviewed-by: Craig Hesling <hesling@chromium.org>
* stm32h7: Pass write protect settings to RWCraig Hesling2020-02-151-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | | Preserving these setting is purely cosmetic, since the enforcement for these settings is done in hardware. These simply reflect the state of the hardware settings, which allows other methods to have more precise errors and statuses. Noticeable Changes: - RW will now known that all_now has been set in RO. Before, all_now had been set in RO (hw enforced), but RW was not aware of this. Running the command flashinfo in RW will now reflect all_now. - The flashwrite and flasherase commands check if all_now is set before starting. They properly return access-denied if all_now is set, but since RW was not aware that all_now, it would return some other error. BRANCH=nocturne,hatch BUG=none TEST=none Change-Id: Iab5511722c114adf1b514e941032bc1c3d33341c Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1987843 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* nocturne_fp: Add fix for legacy reset loopCraig Hesling2020-02-063-16/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch mitigates an infinite reset loop caused by an RO bug. The reset occurs in RO when hardware write protect (wp_gpio_asserted) is disabled, but software write protect (ro_now) is still enabled. This can be seen by disabling hardware write protect and issuing a soft reset. There is one case where RO will forgo issuing this system reset. That is when it detects a power on reset. Furthermore, it retrieves its reset flags from the main system_get_reset_flags function, which combines hardware reset registers AND a special RTC backup register designed to preserve reset flags. We exploit this reset backup register mechanism to inject a fake power-on flag before resetting. As an added bonus, we also inject an ap-off flag so that we can determine on startup if the power-on flag is real or forged by this mechanism. If we detect that the power-on flag was forged, we print a warning and fix the current reset flags. In order to ensure that a power-on will be forged when a spurious reset happens (exception or pin reset), we keep the backup register loaded with the power-on and ap-off reset flags, when the hardware write protect is disabled. In order to keep the typical code path (HW+SW WP enabled) clear of complexity and false power-on reports, we only forge the power-on flag when hardware write protect is disabled. Thus, we conditionally setup the forge on startup and setup an interrupt handler to catch changes to the hardware write protect status. It is safe to use ap-off flag for our nefarious purposes, since the fingerprint controller has no functionality to control an AP and has no included code that uses this reset flag. Review: * Normal power on reset --> The ap-off flag should be cleared * Forged power on reset --> We set the ap-off flag Scenarios covered: * True power on --> No reset loop and ap-off would not be set * HW reset pulse --> We preloaded ap-off and power-on flags in the reset backup register * Exception/Watchdog --> Same as above * System reboot --> We modified the system_reset function to add ap-off and power-on to reset backup register BRANCH=nocturne,hatch BUG=b:146428434 TEST=make buildall -j TEST=Checked all of the scenarios mentioned above in the [SW-WP off + HW-WP off], [SW-WP on + HW-WP on], and [SW-WP on + HW-WP off] situations using the nucleo-h743zi board (https://crrev.com/c/1994624). TEST=Checked all of the previous using nocturne_fp board on nucleo-h743zi TEST=Checked stable RO+fixed-RW on Kohaku Change-Id: I89361fa95be8eafe78c80c30f5b3195d7a724f81 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1992740 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* stm32: Enlarge console task stack for testingYicheng Li2020-02-051-0/+7
| | | | | | | | | | | | | | | | | | | | For on-device unit tests, we use the console to "runtest" and view results. A small console size would result in console stack overflow after the test finishes. Use a larger console stack if it's a test build. BRANCH=None BUG=b:146059307 TEST=make BOARD=nucleo-h743zi tests -j (Flash the build/nucleo-h743zi/test-aes.bin) (Connect to UART console) runtest (Repeat for test-sha256.bin and test-sha256_unrolled.bin) Change-Id: I5c48ae10f5808ed2d3854fdc72275a3a416cf76d Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006709 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* stm32/hwtimer: Fix CONFIG_WATCHDOG_HELP #endif commentCraig Hesling2020-02-041-1/+1
| | | | | | | | | | | | BRANCH=none BUG=none TEST=none Change-Id: Ic9a2f35f06e5e0a8a1fe85eb5959781310f7d430 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2037093 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/stm32/usb: Detect SOF when resume state is not expectedNicolas Boichat2020-02-041-5/+27
| | | | | | | | | | | | | | | | | | | | | | | When the resume interrupt handler is called, but the state is not the expected 0 or 1, let's detect if we receive any SOF from the host. If we do, this means that the link is active and that we shouldn't go back to sleep (which would put us in an infinite loop). BRANCH=kukui BUG=b:144808697 TEST=Type usbresume in console (with other HACK CL), see that we can recover whether or not the interface is autosuspended. TEST=With device autosuspended, short D+/D- on the base, that generates a spurious resume event (similar to what we observed doing ESD testing on Soraka), and check that in that can we don't get an SOF and we go back to sleep. Change-Id: Ibd5c5f7e5f5c324622df5169bb317afa118edc45 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2035436 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* spi: keep HW SPI module enabled longerJett Rink2020-01-293-13/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the HW SPI module is disabled (i.e. SPE bit is cleared), then the stm stops actively driving the SPI CLK signal and lets it float. This can cause spurious communication issues or guaranteed issues if there is a pullup on the CLK signal. Ensure that the CLK signal is being driven (low) for the duration of a USB SPI transaction at minimum. Driving the CLK signal low for the duration of the SPI transaction also seems to help with sporadic reliability issues on servo_micro Also add a flag that enables the SPI module to be enabled for the entire time the firmware wants to enable the SPI module opposed to needing both the firmware and the USB host to enabled the SPI module. BRANCH=servo BUG=b:145314772,b:144846350 TEST=with scope verify that SPI CLK line is help low as soon at the `enable_spi 1800` command is enter on C2D2 console and continues to stay low in between all USB SPI traffic from host. Change-Id: I9dbd6b3ebca8db6470d9ec70bae02ac8366d6c9e Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1995604 Reviewed-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* spi: add flags to spi configurationJett Rink2020-01-291-1/+9
| | | | | | | | | | | | | | | | Add flags field to stm and g chip usb spi configuration. This is unused for g chip, but added for consistency. BRANCH=none BUG=b:147353903 TEST=builds Change-Id: Ie2aa88ae09e8f6f4049ba13fe4565901c604b92c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1995603 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Brian Nemec <bnemec@chromium.org>
* spi: respond to USB endpoint when SPI disabledJett Rink2020-01-281-3/+0
| | | | | | | | | | | | | | | | | If the stm has its SPI bus disabled locally, then the host request to enable or disable SPI would go unacknowledged which would ultimately crash the stm32. BRANCH=none BUG=b:147353903 TEST=execute flash rom when C2D2 is not in SPI mode and watch that C2D2 no longer crashes. Change-Id: I05d6c1519b90932a9c883c013059446c2751c892 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1995602 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Brian Nemec <bnemec@chromium.org>
* chip/stm32: Stop timers and watchdogs on STM32F4 when debuggingCraig Hesling2020-01-212-1/+10
| | | | | | | | | | | | | BRANCH=none BUG=none TEST=make buildall -j TEST=Attach SWD to dragonclaw v0.2 Change-Id: I7bd5741c4862bb2f134ae3067715d2301a18ea78 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1962974 Reviewed-by: Jett Rink <jettrink@chromium.org> Tested-by: Tom Hughes <tomhughes@chromium.org>
* ServoMicro: Enable Brownout detection with PVD circuitBrian J. Nemec2020-01-183-4/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enables the programmable voltage detector (PVD) interrupt in ServoMicro. This interrupt fires when the supply voltage drops from the expected 3.3V to under 2.3V after power on. This gives several hundred microseconds of time for the device to respond to the power reduction. In order to ensure that the ServoMicro does not enter a non-responsive state, it triggers a reboot of the system to restore it to a good configuration. BRANCH=servo BUG=chromium:1023715 TEST=Configured GPIO output to trigger on pvd_interrupt() and verified the interrupt fires during the following situations using Saleae analyzer: * USB Power removed from working device * Ramping supply voltage from 1.5V to 5V with a DC supply * Repoducing failure condition from crbug/1016051 1 Connect ServoMicro to Cyan board 2 dut-control power_state:on 3 dut-control fw_wp_vref:pp3300 4 dut-control power_state:off 5 GPIO toggles and system reset occurs Change-Id: I721f48ab84b01d52a5f98747cc9d879ff2876a07 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1911759 Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org> Auto-Submit: Brian Nemec <bnemec@chromium.org>
* i2c: Support changing I2C bus speed at runtimeTing Shen2020-01-172-29/+33
| | | | | | | | | | | | | | | | | | | | | Add a i2c_set_freq function and let chip drivers add their underlying implementation. Also implemented on stm32f0. BUG=b:143677811,b:78189419 TEST=1) make 2) On kodama, call i2c_set_freq(1, 100) during init. verify the bus is configured to 100kbps in kodama rev 1 BRANCH=kukui Change-Id: Iebb5baacf098b3e5649a4bd8ca14acf097d39693 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1969245 Reviewed-by: Matthew Blecker <matthewb@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* chip/stm32/usb_hid_keyboard: Fix (mu)henkan keys for JP inputNicolas Boichat2020-01-161-1/+1
| | | | | | | | | | | | | | | | | | | かな (kana) key in the right side of the space bar (Row 12/ Column 1) must emit USB keycode 0x8a, which will get translated to KEY_HENKAN(92) by the Linux kernel. 英数 (eisu) key on the left side (Row 12/Column 3) must emit USB 0x8b, translated to KEY_MUHENKAN(94). BRANCH=kukui BUG=b:144141826 TEST=Flash masterball, hand the device to Japanese PM for testing. Change-Id: Ie16453a605a7153f248badbc4c8ebfc3872ce3ac Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002428 Tested-by: Joseph Kurachi Luk <kura@google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* stm32: Factor our bkpdata functionalityCraig Hesling2020-01-154-118/+149
| | | | | | | | | | | | | | | | | | | | | This commit simply refactors the bkpdata functionality, common to all stm32s, into its own source and header files. Same code, different place. This allows for the use of stm32 backup register functionality outside of stm32/system.c. The targeted usage is in https://crrev.com/c/1992740 , a bug fix that is limited to a board's scope. BRANCH=nocturne,hatch BUG=b:146428434 TEST=make buildall -j TEST=Ensured that reset flag preservation works across resets. Change-Id: Id2ba570949e0e7bb3a1faf64e625e122aa3b4ed5 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1992488 Reviewed-by: Jett Rink <jettrink@chromium.org>
* util: enable chargen for USB consoleNamyoon Woo2020-01-151-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows chargen to print output to USB instead of UART, which is chosen by command parameter. If USB console is not supported, then the parameter will be ignored, and output shall go to UART port. The patch increases flash usage by 48 bytes if CONFIG_CMD_CHARGEN is defined. BUG=chromium:992607 BRANCH=None TEST=manually ran on fleex. for BOARD in {cr50, fleex} 1. Define CONFIG_CMD_CHARGEN in board/cr50/board.h, and baseboard/octopus/baseboard.h. 2. Build binaries, and program them. 3. Connect CCD to Octopus Fleex. 4. Open terminal to Cr50 and EC consoles, and run chargen (cr50) chargen 1 4 > // no output, because they went to UART. (cr50) chargen 1 4 usb 0000 > (ec) chargen 1 4 0000 > (ec) chargen 1 4 usb // usb parameter gets ignored. 0000 > Change-Id: I5810421fef56548e0bd667488e853e724f699a31 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1769386 Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
* stm: add register valuesJett Rink2020-01-141-1/+3
| | | | | | | | | | | | | Add new register definitions needed for c2d2 BRANCH=none BUG=b:145314772 TEST=none Change-Id: I159f832a40037271aa352fe83c5289a3a674699b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1991848 Reviewed-by: Craig Hesling <hesling@chromium.org>
* core/system: Extract and doc cortex constCraig Hesling2020-01-131-1/+3
| | | | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=none TEST=make buildall -j TEST=make BOARD=nucleo-h743zi # Reboot H743 into bootloader using boot0 pin and reset # Flash nucleo over FTDI and STM32 bootloader stm32mon -u -U -w build/nucleo-h743zi/ec.bin -d /dev/ttyUSB0 -b 115200 # Reset without boot0 # Open console minicom -D/dev/ttyACM0 reboot soft # Verify soft reset was used reboot hard # Verify hard reboot was used Change-Id: If211198b853ad97cb96b39c063d3e04bfce68179 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1988232 Reviewed-by: Jett Rink <jettrink@chromium.org>
* pd: cleanup pd_get_roleDenis Brockus2020-01-091-1/+1
| | | | | | | | | | | | | | | | | | pd_get_role in the TCPMv1 stack meant pd_get_power_role. pd_get_role in the TCPMv2 stack meant pd_get_data_role. This CL will clean that up and make them the correct naming. pd_get_power_role will also return an enum pd_power_role type instead of an int. BUG=b:147290482 BRANCH=none TEST=make buildall -j Change-Id: I73ee465401ccd050c2bd151f2fc043a59d95e079 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1991844 Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32f4: Add registers for DBGMCUCraig Hesling2019-12-161-1/+35
| | | | | | | | | | | | | This is more for register documentation accuracy. BRANCH=hatch BUG=none TEST=make buildall -j Change-Id: I879ae1feb85115ebfa845fc98ff9bb1b9ef2b936 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1962973 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32f4: Fix SBF clear bitCraig Hesling2019-12-161-1/+1
| | | | | | | | | | | | | | The STM32F412 and STM32F446 reference manuals seem to indicate that the SBF clear bit is actually bit 3. BRANCH=hatch BUG=none TEST=make buildall -j Change-Id: Ib98c5831f19355dfe3643c7d0b8258bd449d373b Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958847 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32f4: Cleanup reset reg constantsCraig Hesling2019-12-161-8/+9
| | | | | | | | | | | | | This brings no function change. BRANCH=hatch BUG=none TEST=make buildall -j Change-Id: I9a9363d4771039244ed79408674a598f768075e9 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958846 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32h7: Cleanup reset reg constantsCraig Hesling2019-12-161-8/+12
| | | | | | | | | | | | | This brings no change in functionality. BRANCH=nocturne,hatch BUG=none TEST=make buildall -j Change-Id: I03ed72ba07affb9b6a8757c1a2154ca31283bb97 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958845 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32f0: expose i2c_init_portTing Shen2019-12-102-2/+18
| | | | | | | | | | | | | | | | Kodama needs to reconfigure i2c bus frequency at runtime. Expose i2c_init_port so we can re-init i2c bus at board_rev_init(). BUG=b:143677811 TEST=verify sensor/battery works on kodama EVT and DVT BRANCH=kukui Change-Id: I4050179d24f05db1ef20270ebbb567eba429546c Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1959669 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* keyscan: decouple keyboard_raw functionality from the presence of TASK_KEYSCANAlexandru M Stan2019-11-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | With the addition of external i2c keyboard controllers, chips that don't necessarly have gpios going to a keyboard can now still have a TASK_KEYSCAN. Therefore it's wrong to assume we want the chip/*/keyboard_raw code included. There was no easy way to make an ways on option (eg: CONFIG_KEYBOARD_RAW) that could get #undefd in strategic places. The place that would always define it would be in include/config.h but I don't believe that executes before the build.mk rules. BUG=b:135895590 TEST=Other boards with keyboards still happy. TEST=No compile errors (regarding missing keyboard GPIOS) when declaring TASK_KEYSCAN on a fresh stm32 board. BRANCH=master Change-Id: I061812a6941a11784950280648912edd5844bd79 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693862 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* stm32: Document flash layout for 1 MB Flash (STM32F412)Tom Hughes2019-11-111-1/+8
| | | | | | | | | | | | | | | | STM32F412xE has 512 KB flash STM32F412xG has 1 MB flash https://www.st.com/resource/en/datasheet/stm32f412cg.pdf BRANCH=none BUG=none TEST=make buildall -j Change-Id: I260659a1de62f3e79f427dd38ca831b4cabed448 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902463 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip/stm32: reinstate static and use EC idiom for alignmentPatrick Georgi2019-11-091-2/+2
| | | | | | | | | | | | | | | | | | | During my bug hunt I had to remove the static attribute. While that wasn't part of the fix, it slipped through. Also, Daisuke pointed out that the standard idiom in the EC codebase is __aligned instead of using the full __attribute__ statement, so switch over. BUG=none TEST=sweetberry gcc8 build still runs Change-Id: I106a8a2df3d6b56bfaba9819228ea7913029f707 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1905767 Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
* chip/stm32/system: Fix the BUILD_ASSERT for CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-091-1/+1
| | | | | | | | | | | | | | | | | Some boards have CONFIG_USB_PD_PORT_MAX_COUNT defined as 3. Fix the concerned build assert. BUG=None BRANCH=None TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and garg(2A + 1C + 1HDMI config). Change-Id: I4dc949b69dbb3986acc5aa0444c6056268f815f7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898686 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
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