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* Add flash command support to boards with STM32F4Gwendal Grignou2017-06-035-385/+233
| | | | | | | | | | | | | | | | | | | Add support to write and erase all flash with flashrom. Add support to use all the memory. Note that PSTATE must not used its own page, as the STM32F4 use big pages. BUG=b:38018926 BRANCH=none TEST=With flashrom, write all, RO, RW regions. Use flash command on the console, including flashwp Change-Id: I4f0aee1b3a4f342bdf4ca97bf5d8e8bcc153fd9c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/264032 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* hammer: Add support for new keyNicolas Boichat2017-06-021-2/+36
| | | | | | | | | | | | | | | | | | | | | There is a new keyboard matrix layout: - We can map the search key to both KSO1, KSI0 and KSO0, KSI3 (old layout will only use the former, new layout will use the latter). - There is a new key on KSO0, KSI5, which we can map to HID page 0xffd1 code 0x0018. BRANCH=none BUG=b:62004286 TEST=Flash hammer kbpress 0 3 1; kbpress 0 3 0 reports KEY_LEFTMETA as expected kbpress 0 5 1; kbpress 0 5 0 reports "BTN_0", which is probably incorrect, and needs to be fixed. Change-Id: I9fb428805ff756b6d63f50cc5b061c6a0e1defbc Reviewed-on: https://chromium-review.googlesource.com/512502 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* stm32: cleanup flash-f by using constant from register.hGwendal Grignou2017-06-023-79/+121
| | | | | | | | | | | | | | Use constants from registers.h, to easily support other ECs. Fix indentation in registers.h BRANCH=none TEST=compile + following patches tested on STM32F411 BUG=None Change-Id: Iecb3ce759a5c4ff13463e7df1cb7e03fc1ce6f69 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/264030 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* stm32f4: i2c: process stop condition after slave receiver executedWei-Ning Huang2017-05-231-22/+22
| | | | | | | | | | | | | | | | We need to process the stop condition after slaver receiver is executed, or else we will lost the last byte of the transmission. BRANCH=none BUG=b:38510075 TEST=`make BOARD=rose -j`, AP suspend/resume should complete within 3 secs Change-Id: I6390a908b6c05b875b8bb2c0a124292785110b20 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/512463 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* rose: spi: add SPI master halfduplex modeRong Chang2017-05-221-27/+60
| | | | | | | | | | | | | | | | This change adds 3-wire mode support in STM32 SPI master driver. BUG=chromium:688979 TEST=manual enable CONFIG_SPI_HALFDUPLEX read id from SPI heatmap sensor BRANCH=none Change-Id: I09139dcbfe39a427721451db6842ea712abf2e33 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444630 Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* hammer: Make keyboard work at firmware screenNicolas Boichat2017-05-184-25/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, libpayload expects the keyboard interface index to be 0. Then, hid_iface_request needs to reply to USB_HID_DT_HID request with the content of struct usb_hid_descriptor. With current code, the variable name is generated (and therefore hard to guess), so we create a new set of macros so that we can use a specific variable name. Also, add support for HID Get_Protocol and Set_Protocol, as they are compulsory for devices supporting boot protocol, even though those are mostly no-op for now. Finally, add a note regarding USB HID keyboard boot protocol, to make sure that we do not accidentally change the report format. BRANCH=none BUG=b:36538963 TEST=Keyboard works in FW screen, both trackpad and keyboard still work when AP has booted. TEST=hammer/staff can still be updated (both RO from RW, and RW from RO) Change-Id: Ibea4888385909c9ce3b430464e5805c039d4b9ed Reviewed-on: https://chromium-review.googlesource.com/505796 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* config: allow increasing i2c host packet buffer size with configWei-Ning Huang2017-05-182-2/+4
| | | | | | | | | | | | | | | | | | Some chip supports two owned slave address. The second slave address is used for other purpose such as board specific i2c commands. This option can be set if user of the second slave address requires larger host packet er size. BRANCH=none BUG=b:37187312 TEST=`make BOARD=rose -j` Change-Id: I8d0b04bf4dded55e3957c7b25d849663299593e5 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/472288 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* stm32f4: Add stm32f4 I2C slave driverRong Chang2017-05-182-1/+261
| | | | | | | | | | | | | | | | | | This patch clones I2C slave and hostcmd driver from stm32f0. This patch contains contribution from Wei-Ning Huang <wnhuang@chromium.org> for fixing i2c slave transmitter (CL:471726). BUG=chromium:688979 TEST=build and load on dev board, run i2cget/set on host and check return value. BRANCH=none Change-Id: I3d159d5bdd4bda6c229cf6d275ab4982836628dc Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/461037 Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
* usb_hid_touchpad: Add config options to set dimensionsNicolas Boichat2017-05-181-73/+29
| | | | | | | | | | | | | | | | | | | | | | In principle, trackpad dimensions (logical and physical), can be probed from the trackpad at runtime, but this would slow down setup time, as we need to wait for the trackpad to be initialized to read those. Also, we do not have a framework to generate HID report at runtime, and a new base with new trackpad would probably require a new overlay anyway. Also, set appropriate (temporary) values for both hammer and staff. BRANCH=none BUG=b:38277869 TEST=Connect hammer/staff to host, correct logical dimensions are shown in evtest, and resolution is always 32. Change-Id: I39b84274d71ca2f4e285f3324c0841331aae9bc1 Reviewed-on: https://chromium-review.googlesource.com/505856 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add clock configuration for stm32f412 to run at 96 MHzWei-Ning Huang2017-05-122-5/+23
| | | | | | | | | | | | | | Add clock definition for stmf412. New stm32f4 chip variant will have to define their own clock definitions. BUG=b:37187312 TEST=`make BOARD=rose- j` Change-Id: Ie053298d2f1255d7bc152f6018a674281bda7004 Reviewed-on: https://chromium-review.googlesource.com/487848 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* chip/stm32/usb_i2c: Remove obsolete implementationNicolas Boichat2017-05-052-322/+0
| | | | | | | | | | | | | | | Since a04fc68e721 "usb_i2c: refactor into common", the code in chip/stm32/usb_i2c.* is dead, let's remove it to avoid confusion. BRANCH=none BUG=b:35578857 TEST=On hammer, userspace application can still talk to trackpad. Change-Id: Idd9cc1109c80f3949fa8c4e50f4fe2e267d5a7ae Reviewed-on: https://chromium-review.googlesource.com/492768 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* hammer: Pulse detection pin on USB wake eventNicolas Boichat2017-05-021-0/+9
| | | | | | | | | | | | | | | | | | When usb_wake is called (key press, trackpad event), pulse detection pin for 100us. This allows Lid EC to wake the AP even when it is in deep S3 mode, where normal wake using USB lines does not work. BRANCH=none BUG=b:35775062 TEST=Flash hammer, looks at poppy console: base power is not disconnected, but events appear in the console. Change-Id: I7b8ee407046d4caa1ce75190c30d693b71b00d2e Reviewed-on: https://chromium-review.googlesource.com/448380 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: More reliable implementation of usb_wakeNicolas Boichat2017-05-021-6/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | Current usb_wake was sleeping between setting and clearing RESUME bit, which is unprecise. Instead, we count ESOF interrupts in usb_interrupt to detect when to clear RESUME. It is also important that usb_wake does not block, as the calling task (e.g. keyboard scanning) must continue to service events while the USB device is resuming. BRANCH=none BUG=b:35587173 TEST=Connect hammer, force autosuspend using: DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct)) echo 500 > $DEVICE/power/autosuspend_delay_ms echo auto > $DEVICE/power/control Wait a second, type something quickly, verify that no keys are lost. Change-Id: I53b46cce5a4adb0ee4c4a7e9f935c00f7f321636 Reviewed-on: https://chromium-review.googlesource.com/490129 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rose: stm32f4: fix DMA macro to get ISR bitsRong Chang2017-04-261-1/+1
| | | | | | | | | | | | | | | | Rose reads heatmap via halfduplex SPI sensors. This change fixed the macro to get correct DMA ISR register. BUG=chromium:688979 TEST=manually run spixfer in EC console and check return value BRANCH=none Change-Id: I303bdb483032c02d01fd322095f17dba37555447 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444631 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rose: add stm32f4 SPI master supportRong Chang2017-04-262-1/+40
| | | | | | | | | | | | | | | | This change adds stm32f4 stream DMA support and a config option to use first SPI port as master. BUG=chromium:688979 TEST=build and load on stm32f4 dev board BRANCH=none Change-Id: I2b504be70e0fbb17f16ce070119ae4715c88333a Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438911 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rose: remove dependency between stm32f4 I2C master and slave driversRong Chang2017-04-261-0/+2
| | | | | | | | | | | | | | | Frequency change hooks are needed in I2C master mode only. BUG=chromium:688979 TEST=remove CONFIG_I2C_MASTER and build rose target BRANCH=none Change-Id: I7244af73f97799d396d8680c8f131e8746a56e18 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438910 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
* rose: enable stm32f4 EXTI IRQsRong Chang2017-04-261-0/+25
| | | | | | | | | | | | | | | This change copied gpio_init() from stm32f373 driver. BUG=chromium:688979 TEST=load on dev board and check button interrupt BRANCH=none Change-Id: I9dc12ffc02899211b6d07a640682899654c2bbed Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438909 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Revert "system: Shutdown AP before entering hibernate mode"Duncan Laurie2017-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 20c439be209a9cc0bb949ad21f289c453126395f. Reason for revert: This breaks hibernate on skylake boards and needs to be tested on more than just kevin before submitting. BUG=chromium:702451 BRANCH=none TEST=power down and successfully hibernate on Eve Original change's description: > system: Shutdown AP before entering hibernate mode > > BUG=chromium:702451 > BRANCH=none > TEST=manually test on gru: confirm > 'Alt+VolUp+h' puts gru in hibernate mode and > AC plug-in wakes it up. > > Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 > Reviewed-on: https://chromium-review.googlesource.com/470787 > Commit-Ready: Philip Chen <philipchen@chromium.org> > Tested-by: Philip Chen <philipchen@chromium.org> > Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> > TBR=rspangler@chromium.org,aaboagye@chromium.org,philipchen@chromium.org # Not skipping CQ checks because original CL landed > 1 day ago. BUG=chromium:702451 Change-Id: Ie847a5e3efb28256b00ddc6534d8ae6bbbba7121 Reviewed-on: https://chromium-review.googlesource.com/482989 Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* system: Shutdown AP before entering hibernate modePhilip Chen2017-04-141-1/+1
| | | | | | | | | | | | | | BUG=chromium:702451 BRANCH=none TEST=manually test on gru: confirm 'Alt+VolUp+h' puts gru in hibernate mode and AC plug-in wakes it up. Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 Reviewed-on: https://chromium-review.googlesource.com/470787 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* rose: add stm32f4 family supportRong Chang2017-03-281-2/+3
| | | | | | | | | | | | | This change applys config-stm32f446.h to stm32f4 family. BUG=chromium:688979 TEST=boots on stm32f401 and stm32f412 dev boards BRANCH=none Change-Id: I939fd17f29f4b431d9c1358c184166c67fef18d3 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438908 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add internal flash support for STM32L4 familyVincent Palatin2017-03-243-6/+554
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a flash driver for the STM32L4 family. For write and erase, the code is very similar to other variants excepted the 'normal' writes need to be perform 2 aligned 32-bit words at a time. Option bytes are a sligthly easier business since the hardware deals with the option bytes page preserving and erasing for us. For the write-protection, the STM32L4 is slightly different from the other variants. The write-protection granularity is still a 2-kB block (2kB here) but instead of having a 'bitmap' of the protected blocks, it defines 2 write-protection ranges (WRP1AR and WRP1BR). For the EC code base, we are using WRP1AR to protect the Read-Only regions and WRP1BR to protect the Rollback and RW regions (if they exist). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648258 TEST=On Eve, run 'flashrom -p ec:type=fp -w /tmp/ec.bin' and 'flashrom -p ec:type=fp --wp-enable --wp-range 0x0 0x20000' Change-Id: Iaa98c1b4d3b07de2923ac076624bd4601c31a600 Reviewed-on: https://chromium-review.googlesource.com/456711 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/stm32/usb-stream: Fix rx_read queue space comparisonNicolas Boichat2017-03-221-1/+1
| | | | | | | | | | | | | | | There is no reason to reject the incoming USB packet if its size equals the amount of space in the queue. BRANCH=none BUG=b:35587171 TEST=usb_updater2 works fine, even with 64-byte USB packets. Change-Id: I2e54f1a758dd8a370dacdc8c2519bbd91e9cb4e5 Reviewed-on: https://chromium-review.googlesource.com/458042 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tigertail: usb-c muxNick Sanders2017-03-211-0/+1
| | | | | | | | | | | | | | | | | | | tigertail allows muxing a usb-c port onto two different passthough targets. This allows for automated switching between USB host and device without DUT or endpoint knowledge. tigertail also routes SBU lines to stm32 UART, and has INAs on VBUS and VCONN to measure power. BUG=b:35849284 BRANCH=None TEST=Muxing power, muxing USB, uart works, INAs work. Change-Id: I5bf2ba038aa78e59352ad99cd71efb0f0d0fbec9 Reviewed-on: https://chromium-review.googlesource.com/438677 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb: Cleanup headersNicolas Boichat2017-03-1610-1/+14
| | | | | | | | | | | | | | | | | | | Let's split the usb headers in 3 different parts, instead of having usb_descriptor.h pull in usb_hw.h and usb_api.h. - usb_api.h: EC functions related to usb (e.g. connect/disconnect) - usb_descriptor.h: common USB names and structures - usb_hw.h: Functions required for interactive with EC's USB HW BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I37ead61e3be5e7ae464f1c9137cf02eaab0ff92e Reviewed-on: https://chromium-review.googlesource.com/454861 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: clean-up the SPI_READBACK_ALL implementationVincent Palatin2017-03-161-2/+4
| | | | | | | | | | | | | | | | | | | | | As advised by Daisuke makes the new API slightly better: - remove the useless rxlen assignment. - keep the normal asynchronous behavior of the function by skipping the last dma wait. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648259 TEST=on Eve, use the FP sensor with the passthru. Change-Id: Iedb8e77cb1af58c273ab5ae6f0a670ce93dfde5a Reviewed-on: https://chromium-review.googlesource.com/454699 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* spi: extend spi master API on STM32Vincent Palatin2017-03-131-5/+18
| | | | | | | | | | | | | | | | | | | | | | | | | Extend the SPI master API to be able to do fancier transactions: - allow to read the incoming bits while transmitting. If SPI_READBACK_ALL is set in 'rxlen' when calling spi_transaction(), then the received data during transmission is recorded in rxdata buffer and the function assumes that the real 'rxlen' is equal to 'txlen'. - add spi_transaction_wait() which is similar to spi_transaction_flush() but without de-asserting the chip select, so we can chain several transfers in a single transaction. Implement them for STM32. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:35648259 TEST=on Eve, use the FP sensor with the passthru. Change-Id: Iebff617acd3230277d36a4f565766b7748721a1d Reviewed-on: https://chromium-review.googlesource.com/452898 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* eve_fp: setup SPI slave communication on STM32L442Vincent Palatin2017-03-131-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | Enable properly the SPI slave command interface to drive the FP MCU from the main CPU using the EC SPI protocol V3. Fix the SPI slave driver on STM32L4 along the way: - the STM32L4 family has the same FIFOs as STM32F0 - on STM32L4, we need to map the DMA requests - set explicitly the data size (rather than setting an invalid value which defaults to 8-bit). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:36025702 TEST=On Eve, use the kernel cros_ec_spi driver to communicate with the FPMCU using the Cros EC SPI protocol V3. Change-Id: Ib641c141808aa60b3a74611319e18e7a6c3736f0 Reviewed-on: https://chromium-review.googlesource.com/452373 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* chip/stm32/usb: Add support for USB SET_FEATURE control requestsNicolas Boichat2017-03-081-5/+30
| | | | | | | | | | | | | | | | | | | | This is required so that the kernel can enable/disable remote wake-up capabilities, and in particular for the kernel to enable autosuspend. Also, properly implement GET_STATUS. BRANCH=none BUG=b:35579996 TEST=echo auto > /sys/bus/usb/drivers/usb/X-Y/power/control, device autosuspends after 2 seconds, and wakes on keypress. Note that this introduces other bugs, where keys are missing, repeated, see b/35775048. Change-Id: I7ddd257ac3877d27fb2da813f20583a614a0169b Reviewed-on: https://chromium-review.googlesource.com/450826 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* hammer: Switch trackpad I2C to 400 kHz, decrease EP interval to 2msNicolas Boichat2017-03-071-1/+1
| | | | | | | | | | | | | | | | These 2 changes improve the measured touchpad drag latency. BRANCH=none BUG=b:35587172 TEST=Measure improved latency with WALT. TEST=Using CONFIG_TRACE, look at output. Change-Id: Ibeb90f6f92423e82100f17df79b2f20d90abfeb7 Reviewed-on: https://chromium-review.googlesource.com/450980 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Charlie Mooney <charliemooney@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* gpio: Add function to clear pending interruptDuncan Laurie2017-03-011-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently if an interrupt is pending before it is enabled the interrupt will fire immediately. In most cases this is fine, but if we want to use the interrupt to trigger something like waking the AP it should be sure that it won't immediately fire once enabled. For example: on the Eve board we have the trackpad interrupt run to the AP and the EC in order to support wake from Deep S3 (magic AP state that only the EC can wake it from). This interrupt is used in S0 by the AP while ignored by the EC, and then enabled on the transition to S3 in order to be able to wake. Since it has been active the interrupt may be pending in the EC (depending on the chip), which can result in the interrupt firing immediately and waking the AP. BUG=chrome-os-partner:62224 BRANCH=none TEST=This has been functionally tested on npcx only as that is what I have a use case and system for, the others compile and look right but have not been directly tested. Change-Id: I9e0877d99e7f09f4c30bf9861fbad81c12c059ad Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/446962 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32/usb: Add support for remote wake-upNicolas Boichat2017-03-014-18/+41
| | | | | | | | | | | | | | | | | | | | USB uses a special mode the trigger remote wake-up during host suspend, by setting the K-state on the data differential pair, and setting a bit in the USB config descriptor attributes field. Let's enable that so that hammer can wake up host from S3. BRANCH=none BUG=chrome-os-partner:62325 TEST=Connect hammer to chell, put chell in S3. Press a key (or use ("kb 3 3 1; kb 3 3 0" in console), or touch trackpad => host wakes. Change-Id: Ib7b1e9047e01869f07ddd771c9c9bc640eef10d6 Reviewed-on: https://chromium-review.googlesource.com/446240 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32/usb: Add support for USB suspendNicolas Boichat2017-03-015-2/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | This follows the basics of what is decribed in RM0091 Reference Manual 30.5.5 Suspend/Resume events . We call enable/disable_sleep at suspend/resume, to make sure the EC stays awake when USB is connected and active. We also call clock_enable/disable_module, which is stubbed on stm32f0, but can be used on other devices in the family. This also fixes interrupt handling in usb_interrupt, by only clearing interrupt bits that were handled instead of resetting them all, which is racy, and can potentially lead to issues if reset comes soon after a resume event. BRANCH=none BUG=chrome-os-partner:62325 TEST=build and flash hammer, connect to chell, suspend/resume, and see that hammer prints USB suspend and USB resume lines. Change-Id: Ie9d02fd4a114add3ebc98dc9393680bc9a64a522 Reviewed-on: https://chromium-review.googlesource.com/446239 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f09x: fix flash protection offsetRong Chang2017-02-272-2/+59
| | | | | | | | | | | | | | | | | | | | | STM32F091VC has 32 flash protection sectors (31 x 4KB + 1 x 132KB), which doesn't fit the layout requirement in config_std_internal_flash.h. This CL hardcodes the layout and flash bank mapping. BUG=chrome-os-partner:62372 BUG=chromium:694972 TEST=load on elm and manually enable write protect using flashrom # flashrom -p ec:dev=0 --wp-enable check ec console write protect option bytes, bank 31 is writable > rw 0x1ffff808 read 0x1ffff808 = 0xff00ff00 > rw 0x1ffff80c read 0x1ffff80c = 0x7f80ff00 BRANCH=oak Change-Id: I23dcf87bfbcd2f37e97a87e94847dce1ea1d343c Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/446176
* pd: Store PD active state in battery-backed memoryShawn Nematbakhsh2017-02-251-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Our previous idea to cut Rd for many reset cases cannot work if cr50 consistently resets the EC by asserting the reset pin shortly after power-on. Therefore, make a decision based upon whether battery-backed memory indicates we previously negotiated a PD power contract as a sink. If we previously did not negotiate a contract, or if power was removed from the device (causing battery-backed memory to wipe) then we can assume that we don't have an active power contract. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/443356 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* flash: Add ROLLBACK flash region, that can be protected separatelyNicolas Boichat2017-02-252-2/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ROLLBACK region will be used to store rollback information, and can be protected independently of RW (it can only be protected when RO is protected, though). This is only supported on stm32f0 currently. BRANCH=none BUG=chrome-os-partner:61671 TEST=on hammer (stm32f072) flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp all; reboot => RO+RW+RB protected flashwp noall; reboot => only RO protected flashwp rw; reboot => only RO+RW protected flashwp rb; reboot => RO+RW+RB protected flashwp norb; reboot => RO+RW protected flashwp all; reboot => RO+RW+RB protected flashwp norw; reboot => RO+RB protected TEST=on reef, rb/norb commands not available Change-Id: I45ffc66d91cf3699ecff025e5114c59a73dc8274 Reviewed-on: https://chromium-review.googlesource.com/430519 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* system: Add generic bbram read / write routinesShawn Nematbakhsh2017-02-241-22/+33
| | | | | | | | | | | | | | | | | | Add generic routines to read or write a byte to battery-backed RAM, and implement vbnvcontext get/set using these routines. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, with subsequent commit, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d Reviewed-on: https://chromium-review.googlesource.com/444444 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash: Add EC_FLASH_PROTECT_RW_[AT_BOOT|NOW] flagsstabilize-9313.BNicolas Boichat2017-02-232-4/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The idea of this flag is to be able to protect/unprotect only the RW portion of the flash. In the (usual) case where ALL=RO+RW, with no other region, this makes no difference compared to the existing EC_FLASH_PROTECT_ALL_* flag, and this flag may not be supported. This is necessary for futher work, where a ROLLBACK region is added, so that RW/ROLLBACK can be protected/unprotected individually. Only support for stm32f0 is added, as this is the target for hammer. BRANCH=none BUG=chrome-os-partner:61671 TEST=build and flash hammer (stm32f072) flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp all; reboot => RO+RW protected flashwp noall; reboot => only RO protected flashwp rw/norw not available TEST=enable CONFIG_FLASH_PROTECT_RW build and flash hammer (stm32f072) flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp all; reboot => RO+RW protected flashwp noall; reboot => only RO protected flashwp rw; reboot => RO+RW protected flashwp norw; reboot => only RO protected TEST=build and flash reef (npcx) flashinfo => RO+RW not protected flashwp true => RO protected flashwp all; flashinfo => all_now displayed reboot => RO protected flashwp rw/norw not available Change-Id: Ica6f499cf2e8a9345b08ef52c915655a983ffe3c Reviewed-on: https://chromium-review.googlesource.com/442265 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32/usb: Add useful register macros instead of hardcoding valuesNicolas Boichat2017-02-232-6/+39
| | | | | | | | | | | | | | | Hopefully makes the code a little easier to understand, and will be useful for future features. BRANCH=none BUG=chrome-os-partner:62325 TEST=build and flash hammer Change-Id: I2b562740794c165da4e6611be371926e737f3887 Reviewed-on: https://chromium-review.googlesource.com/446238 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: more clocks support for STM32L4 familyVincent Palatin2017-02-232-7/+34
| | | | | | | | | | | | | | | | | | | | | | | Add the option to use the PLL connected the 16Mhz HSI oscillator. Fix the system timer pre-scaling when changing frequency: - we need to generate an update event immediately as on a 32-bit timer it might take a very long time before going an actual update event. - we need to ensure that the OS timestamp is monotonic and sensible across the frequency jump. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:62893 TEST=manual, on STM32L4 console, do several gettime and compare against wall time, switch to 80Mhz with 'clock pll', verify again gettime against wall clock. Change-Id: Ibddbd46173b7594d16fb07e4b57660a50c636568 Reviewed-on: https://chromium-review.googlesource.com/445776 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: add TRNG supportVincent Palatin2017-02-233-0/+88
| | | | | | | | | | | | | | | | | Add a driver for the STM32 True Random Number Generator. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:62991 TEST=adhoc on STM32L, craft console command and generate/dump buffers of random numbers. Change-Id: Ie7ce890cfc36a3b9a277715b17051e3e42fdfc96 Reviewed-on: https://chromium-review.googlesource.com/445777 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: add support for STM32L442Vincent Palatin2017-02-176-9/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | Should be close to the STM32L476 in the STM32L4 family. Slightly different flash/RAM. It's currently running from the internal clock (HSI) at 16Mhz, we need to upgrade to 80Mhz (or 48Mhz if this is fast enough to save us the PLL locking time). The internal flash write/erase/protection is still not implemented for the whole STM32L4 family. Upgrade the SPI master support and verify that the TX works. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:62893 TEST=make BOARD=eve_fp run it on Nucleo-L432KC (STM32L432KC is mostly the same MCU without AES) Change-Id: I87be7d4461aedfbd683ff7bb639c3a6005ee171e Reviewed-on: https://chromium-review.googlesource.com/442466 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* flash: Pass more precise parameter to flash_[physical_]protect_at_bootNicolas Boichat2017-02-123-18/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding the rollback protection block, pass EC_FLASH_PROTECT_RO/ALL_AT_BOOT to flash_[physical_]protect_at_boot, instead of an enumeration no protection/RO/ALL. This will later allow us to protect/unprotect the rollback region only, by adding a EC_FLASH_PROTECT_ROLLBACK_AT_BOOT flag. BRANCH=none BUG=chrome-os-partner:61671 TEST=Build hammer with CONFIG_CMD_FLASH command, so that write protection can be checked with flasherase/flashwrite. TEST=On hammer (stm32f072): flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp rw; reboot => RO+RW protected flashwp norw; reboot => only RO protected TEST=On reef (npcx): deassert WP, flashwp false; flashinfo => RO+RW not protected flashwp true => only RO protected reboot => only RO protected flashwp rw => RO+RW protected reboot => only RO protected Change-Id: Iec96a7377baabc9100fc59de0a31505095a3499f Reviewed-on: https://chromium-review.googlesource.com/430518 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* usb: activate CRS on STM32F0Sam Hurst2017-01-262-0/+59
| | | | | | | | | | | | | | | | | | | | | Enable the Clock Recovery Subsystem to automatically adjust the internal HSI48 clock for proper USB operation on the STM32F0. BUG=chrome-os-partner:34160 TEST=Manual testing on STM32F072B-DISCOVERY Plugged in board and verified that device was detected with dmesg. [1400698.702999] usb 3-10: new full-speed USB device number 47 using xhci_hcd [1400698.720063] usb 3-10: New USB device found, idVendor=18d1, idProduct=500f [1400698.720069] usb 3-10: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [1400698.720072] usb 3-10: Product: PDeval-stm32f072 [1400698.720075] usb 3-10: Manufacturer: Google Inc. BRANCH=none Change-Id: I496a9a121a4b1a0009fe04cfe24aaa693ada9236 Reviewed-on: https://chromium-review.googlesource.com/433059 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Remove unused struct definitionsMartin Roth2017-01-022-10/+0
| | | | | | | | | | | | | | | The code that referenced these structure definitions was removed months ago. GCC 6.2 warns about the structures being definte but not used. BRANCH=none BUG=none TEST=Build tested only Change-Id: I68de7cc351667b3fb51aa9004dfc86d936f4a9cc Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424432 Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: Remove useless code from usb_power.cMartin Roth2016-12-261-12/+0
| | | | | | | | | | | | | | | | | | | | | The function usb_power_map_error() is only called from a single location, with a fixed value passed in, and the return value, which is the only reason for the function, is ignored. The whole thing is useless, so remove the function and call. Since the sizes of all platforms are unchanged before and after removing this, I suspect it was getting optimized out anyway. Fixes coverity warning 157563: Useless call BUG=None BRANCH=None TEST=build tested only. Change-Id: Ie6572d2f5579819f06a53a567e1a93aabca217db Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/418070 Reviewed-by: Shawn N <shawnn@chromium.org>
* chip/stm32/usb_hid: Add USB HID touchpad driverNicolas Boichat2016-11-222-0/+352
| | | | | | | | | | | | | | | This describes a 5-finger touchpad. The physical/logical dimensions of the trackpad are hardcoded for the time being. BRANCH=none BUG=chrome-os-partner:59083 TEST=make BOARD=hammer -j && util/flash_ec --board=hammer Change-Id: I04a0833a28c013395974104ebdd6fcb29e5d6680 Reviewed-on: https://chromium-review.googlesource.com/407742 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: Allow interface handler to reply with more than 64 bytesNicolas Boichat2016-11-223-14/+69
| | | | | | | | | | | | | | | | For example, when a HID descriptor is longer than 64 bytes, we need to split it in multiple packets. BRANCH=none BUG=chrome-os-partner:59083 TEST=make buildall -j TEST=make BOARD=hammer -j && util/flash_ec --board=hammer Change-Id: I25a05eabaf9413e332fe3cd70695a0d53639713d Reviewed-on: https://chromium-review.googlesource.com/409316 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid_keyboard: Add functions for keyscanNicolas Boichat2016-11-221-40/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | This first cleans up the code: - Define report as a structure. - Fix USB interval from 40 ms to 32 ms (Linux kernel complains otherwise). Then, this removes the old set_keyboard_report interface, and replaces it by the interface used by the keyboard scanner (i.e. keyboard_state_changed and keyboard_clear_buffer). This also means we need a keycode table to translate from row/column to USB HID keycode. BRANCH=none BUG=chrome-os-partner:59083 TEST=make buildall -j TEST=make BOARD=hammer -j && util/flash_ec --board=hammer With evtest and "hid 0-7" in console, check that key are reported correctly. Change-Id: I5d526db1568c29c7f28fc5e962e213e44303cc16 Reviewed-on: https://chromium-review.googlesource.com/411571 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid_keyboard: Fix set_keyboard_report raceNicolas Boichat2016-11-171-5/+61
| | | | | | | | | | | | | | | | | | | | | | | We always want set_keyboard_report to send the freshest possible data. For this purpose, we use double-buffering on the USB endpoint. When the endpoint is currently busy, we sneak in an address change, hoping that the hardware will pick it up. There is no guarantee about which buffer was transferred, so we queue another transfer anyway. This means that the code will send a duplicate (harmless) report in that case. BRANCH=none BUG=chrome-os-partner:59083 TEST=make buildall -j TEST=make BOARD=hammer -j && util/flash_ec --board=hammer Change-Id: I9d14541b8b05017c1d5051b9a315db381a89dcea Reviewed-on: https://chromium-review.googlesource.com/411741 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid: Separate HID keyboard supportNicolas Boichat2016-11-164-117/+174
| | | | | | | | | | | | | | | | | | | | | In the future, we'd like to have different HID devices on different endpoints (keyboard, trackpad, etc.), so we'd like to separate the keyboard handling. For other chip implementing usb_hid.c (namely, chip/g), we, for now just rename the config option and endpoint/interface definitions. Making the code more generic can be done at a later stage. BRANCH=none BUG=chrome-os-partner:59083 TEST=make buildall -j TEST=make BOARD=hammer -j && util/flash_ec --board=hammer Change-Id: Iad1b00fa226f7635c0f34aae6a435dc53a3ea555 Reviewed-on: https://chromium-review.googlesource.com/409256 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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