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* stm32: update USB version for BOS descriptorsVincent Palatin2017-11-302-4/+4
| | | | | | | | | | | | | | | | | | | | | | Bump the USB version (aka bcdUSB) for BOS descriptors to 2.1 (rather than 2.01) to be compatible with Chrome implementation. The CL 664813 was intending to do this, but I screw up and only changed it for chip/g and let chip/stm32 unchanged : https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/664813 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=twinkie BUG=none TEST=manual, plug an updated Twinkie and see the WebUSB pop-up on Chrome. Change-Id: Ia81fa91b6d7790af6f6683c0da7ca1d794b4e4df Reviewed-on: https://chromium-review.googlesource.com/789934 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f0: i2c: Fix dropped Rx byte in TCPCI slave modeShawn Nematbakhsh2017-11-151-5/+5
| | | | | | | | | | | | | | | | | | | If the i2c master sends a stop condition before we've buffered the last Rx byte (eg. due to higher than normal i2c interrupt latency) then we don't want to drop the last byte on the floor, it's still meaningful. BUG=b:65711378 BRANCH=glados TEST=Spam TCPC_REG_ROLE_CTRL commands from caroline to caroline_pd, verify no errors are observed on either side for 12,000,000 transactions. Change-Id: I0c4a81d97315cff553a5448c0940746e1ef0ed2c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/771936 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: jtag: Enable clock to debug module on stm32f0xMoritz Fischer2017-11-152-0/+4
| | | | | | | | | | | | | | | Enables the clock to the debug module so that when connecting via SWD debugger the watchdog and timers are stopped. BRANCH=master TEST=Build on stm32f0x board and connect via SWD, observe no watchdog reset. Change-Id: Ic40b16c09acc5920da2c1a39e9391a6b21849d2c Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: https://chromium-review.googlesource.com/765290 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usart: Add flags to usart_configNicolas Boichat2017-10-182-16/+33
| | | | | | | | | | | | | Allows setting TXINV/RXINV bits. BRANCH=none BUG=b:65697962 TEST=make BOARD=wand -j Change-Id: Ib1bb290cd9758c53b98c8fc1ca1a9369c8cff39e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/694561 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/clock: Optionally use LSE as RTCCLKPhilip Chen2017-10-114-26/+52
| | | | | | | | | | | | | | | | | | | | The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz. To use stm32 RTC for applications requiring accurate timing, let's setup LSE (a more accurate clock source) as RTCCLK. Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally. BUG=b:63908519 BRANCH=none TEST=boot scarlet rev1 and wait for an hour, confirm rtc time == kernel system time. Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/679601 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/clock: Don't wake up the host when the host resets rtcPhilip Chen2017-10-061-1/+2
| | | | | | | | | | | | | | | | | | | The way AP resets ec rtc alarm is to set rtc alarm wake time in 0 sec. In current implementation, this still sets host_rtc_alarm_set. ...So when rtc irq is triggered next time, it wakes up the host even if the alarm is not set by the host. Let's fix it. BUG=b:66971951, b:67379662 BRANCH=none TEST='powerd_dbus_suspend' and see the host stay in suspend mode Change-Id: I1e14f669e3d887874548813c7c5b4d21d80bc62e Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/699657 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip/stm32/clock: Allow the host to reset rtc alarmPhilip Chen2017-10-021-0/+5
| | | | | | | | | | | | | | | | | | | | | When the host sets rtc alarm wake time = 0, it wants to reset and disable the alarm. Also, align the implementation in npcx with that in stm32 to check both delay_s and delay_us. BUG=b:66971951, b:63908519 BRANCH=none TEST='ectool rtcsetalarm 3'. After alarm goes off, run 'ectool rtcgetalarm' and then see 'Alarm not set'. Change-Id: I693f1c72cba492e837891c716f79e2aa4da59b2a Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/691256 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* chip/stm32/clock: Wakeup AP when rtc alarm goes offPhilip Chen2017-09-282-0/+21
| | | | | | | | | | | | | | BUG=b:63908519 BRANCH=none TEST='powerd_dbus_suspend --wakeup_timeout=10' and see AP do S0->S3(10 secs)->S0 Change-Id: I35e248627e2f3b68b0ed3f27d6bae65eb73a745b Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/674054 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip/stm32/clock: Incorporate RTC date registerPhilip Chen2017-09-274-80/+170
| | | | | | | | | | | | | | | | | | | | | | | The current stm32 rtc driver only uses RTC_TR and RTC_SSR. So we son't be able to use rtc for applications which need time > 24 hours. To support such applications, this patch adds operations for RTC date register (RTC_DR). BUG=b:63908519 CQ-DEPEND=CL:666985 BRANCH=none TEST=manually with 'ectool rtcset/rtcset' and '/sys/class/rtc/rtc0', verify the conversion between calendar time and Unix epoch time works. Change-Id: Iacd5468502e4417a70880d7239ca5e03353d9469 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/659337 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Add WebUSB descriptor supportVincent Palatin2017-09-221-19/+40
| | | | | | | | | | | | | | | | | | | | | | | | | The WebUSB specification defines a specific Platform Descriptor in the Binary Object Store: https://wicg.github.io/webusb/#webusb-platform-capability-descriptor This descriptor provides a special 'Landing page' URL to the host browser and associated privileges for it. Bump the USB version for BOS descriptors to 2.1 to be compatible with Chrome implementation. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=none BRANCH=twinkie TEST=manual: on Twinkie (chip/stm32) and HG proto2 (chip/g), enumerate WebUSB descriptors with lsusb and connect to a WebUSB page in Chrome R61+. Change-Id: I7211ab554f4a6c156c1e8e79a3d9f0d6644217c6 Reviewed-on: https://chromium-review.googlesource.com/664813 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Remove jtag_pre_init()Shawn Nematbakhsh2017-09-078-103/+45
| | | | | | | | | | | | | | | Use our newly-created chip_pre_init() for doing JTAG initialization. BUG=chromium:747629 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic5771895a214a9f1aa9bd289eef576f52adf973f Reviewed-on: https://chromium-review.googlesource.com/629676 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip/stm32/usb_hid_keyboard: implement keyboard backlight controlWei-Ning Huang2017-09-014-18/+107
| | | | | | | | | | | | | | | | | | | | | | | Implement keyboard backlight control through HID output report. One could enable CONFIG_USB_HID_KEYBOARD_BACKLIGHT to enable keyboard backlight support for a given board. Target board must implement the `void board_set_backlight(int brightness)` function in order correctly set backlight. BRANCH=none BUG=b:37971411,b:63364143 TEST=with follow up CLs 1. `make BOARD=hammer -j` 2. `echo 10 > /sys/class/leds/hammer\:\:kbd_backlight/brightness` console shows 'Keyboard backlight set to 10%' Change-Id: Ibeff510a0d996ddebf61b54ed6b500b02c35564a Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/586348 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/clock: Support RTC console/host commandsPhilip Chen2017-08-233-0/+137
| | | | | | | | | | | | | | | | Add the driver for RTC console/host commands on stm32f0. BUG=b:63908519 BRANCH=none TEST=on scarlet, manually test 'rtc'/'rtc set' on ec console and 'ectool rtcget/rtcset/rtcgetalarm/rtcsetalarm' on ap console. Change-Id: I71035c91ed69fa5f65448618ff8bd1a37427eaad Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/627637 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/stm32/i2c-stm32f0: Further adjust 400kHz setting (48Mhz clock source)Nicolas Boichat2017-08-231-1/+1
| | | | | | | | | | | | | | | | | | It turns out SCLH = 0x5 is still a little fast (411 kHz on hammer), let's update it to 0x6. See 5e6f9a2b38 "chip/stm32/i2c-stm32f0: Adjust 400kHz setting (48Mhz clock source)" for details. BRANCH=none BUG=b:36172041 TEST=Measure I2C speed to be <400 kHz on hammer Change-Id: I2b5acc532963c407144b8e2a7786d3e2302192d3 Reviewed-on: https://chromium-review.googlesource.com/625507 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Toshak Singhal <toshak@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_hid_keyboard: Add support for boot protocol reportNicolas Boichat2017-08-231-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | In boot protocol mode, we must only send the first 8 bytes of the report. Also, go back to report mode on USB reset. When mode is changed, we immediately toggle keyboard endpoint, to make sure the appropriately sized packet is sent (otherwise, a longer packet packet will be sent once, which confuses AP firmware). BRANCH=none BUG=b:62004286 BUG=b:64953295 TEST=Flash hammer, check that keyboard works at firmware screen and in the OS, and that new key works in OS. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: If7d6aa6c2dd127b9de34fc93d06bc0dd6e6128a2 Reviewed-on: https://chromium-review.googlesource.com/627344 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* stm32: add embryonic support for STM32F76xVincent Palatin2017-08-186-12/+134
| | | | | | | | | | | | | | | | | | | | | | | The STM32F76x is really close to the STM32F4 family, so the most concise implementation is just using CHIP_FAMILY_STM32F4 and adding CHIP_VARIANT_F76X. Tune the clock settings to 180 Mhz CPU clock as the goal is performance. (over-drive is not implemented yet to get to 216 Mhz) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=ran on nucleo-f767zi board. 'make BOARD=nucleo-f767 flash', the red LED is on and the green LED turns on/off when pressing the user button, UART console works properly. Change-Id: I1f67df3aec874c965c81188df46c72de210728d9 Reviewed-on: https://chromium-review.googlesource.com/612750 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: remove stm32f4 dead code in DMAVincent Palatin2017-08-181-33/+1
| | | | | | | | | | | | | | | | | | The STM32F4 family is building a special variant of the dma code (dma-stm32f4.c), all the conditionals for F4 in stm32/dma.c are just dead code. remove them. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall Change-Id: Icbf8d08c7e50fe5153a1b3830011bb12afcabaa5 Reviewed-on: https://chromium-review.googlesource.com/621391 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* usb_hid_touchpad: Add touch event to FIFO during suspendNicolas Boichat2017-08-161-17/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | Similarly to what we have done with keyboard events, we put touch events in a FIFO. The AP will need to interpret the timestamp in the events to be able to process the events correctly tough. Resume should typically take about 50ms, so a 8-event long FIFO should be good enough. Also, we bypass the FIFO altogether in most cases, when the USB interface is not suspended. BRANCH=none BUG=b:35775048 TEST=Connect hammer, force autosuspend using: DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct)) echo 500 > $DEVICE/power/autosuspend_delay_ms echo auto > $DEVICE/power/control Look at evtest output. Wait a second, make a swipe, see that events are received in a very short amount of time after resume (every EP interval/2ms), but the event timestamps show that some of them are older. Change-Id: If6ab56396f7d564b19e6c3c528847196ffa4d849 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/612221 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_hid_touchpad: Add timestamp field to touch eventsNicolas Boichat2017-08-161-0/+10
| | | | | | | | | | | | | | | | | | | | | | We use the unofficial, Windows 8, Relative Scan time HID usage (Digitizer page, 0x56) to add timestamps to our HID touchpad events. The timestamps is a rolling, unsigned, 16-bit integer, with a resolution of 100us (so it wraps around every 6.5s). The host will be able to synchronize to that timestamp, resetting an offset every time the touchpad is quiet a certain amount of time (e.g. 1 second). BRANCH=none BUG=b:63685117 TEST=Flash hammer, timestamps are reported in HID descriptor. Change-Id: Ie5d56a9df14e464d2cdcd559f550d6e3cc81961f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/603041 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid_keyboard: Add keystrokes to a FIFONicolas Boichat2017-08-161-41/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Put key events in a FIFO. This is especially useful when USB is suspended, so that we can replay the events on resume. This makes sure that no key strokes are lost on resume from USB autosuspend. We coallesce events happening within some interval (18 ms), greater than EP interval (16 ms) to ensure we cannot have a backlog of keys. The interval must also be short enough to ensure that the intended order of key presses is passed to AP, and that we do not coallesce press and release events (which would result in lost keys). We also discard key events in the FIFO buffer that are older than 1 second. Note that we do not fully drop them, we still update the report, but we do not send the events individually anymore (so an old key press and release will be dropped altogether, but a single press/release will still be reported correctly). BRANCH=none BUG=b:35775048 TEST=Connect hammer, force autosuspend using: DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct)) echo 500 > $DEVICE/power/autosuspend_delay_ms echo auto > $DEVICE/power/control Wait a second, type something quickly, verify that no keys are lost. Change-Id: I64d33c15a39ae33af42039fba62cf4ed3abef462 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/471188 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid_keyboard: Simpler buffer handlingNicolas Boichat2017-08-161-31/+17
| | | | | | | | | | | | | | | | | | As suggested in CL:411741, makes the follow-up CL that buffers key strokes much simpler. We can revisit later if we can still sneak it that change, but, all in all, we can guarantee the same key latency by halving the USB endpoint interval. BRANCH=none BUG=b:35775048 TEST=Connect hammer, keyboard works. Change-Id: I6624fde9bd5561ddceb7ce195470d7af7cca7140 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/471187 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: Replace reset handler by generic event handlerNicolas Boichat2017-08-1620-75/+151
| | | | | | | | | | | | | | | | | | | Some USB interface handlers need to know when USB has been successfully resumed after a wake event. For example, this is useful so that HID keyboard can send the events at the right time. BRANCH=none BUG=b:35775048 TEST=Using USB HID keyboard patches to queue keys in a FIFO: After USB autosuspends, press a single key and hold it. Without this patch the endpoint data only gets reloaded on the _next_ event. TEST=On hammer, I2C passthrough still works. Change-Id: I9b52b9de16767c8a66c702a5ae70369334a3d590 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/569547 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* scarlet: Remap DMA channels for USART1Philip Chen2017-08-151-1/+2
| | | | | | | | | | | | | | | | | | | To enable console with DMA, we need to specifically remap DMA channels for USART1. ch2/3 and ch6/7 are already used by SPI1/2 modules. So we have to remap USART1_TX to ch4 and USART1_RX to ch5. BUG=b:64575809 BRANCH=none TEST=confirm ec console works on scarlet rev1 Change-Id: Ie2bb141c72252aee98e4cd4a284a01b4d57605f4 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/611147 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: Split usb wake handler as a different functionNicolas Boichat2017-08-151-43/+49
| | | | | | | | | | | | | | Indentation is growing out of control, let's move to a separate function so that we can return early. BRANCH=none BUG=b:35775048 TEST=Flash hammer, usb_wake works. Change-Id: I9abf99ff55b3977dfc307fc99aac6f1ab7dd1f6a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/612922 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_api.h: Stub usb_wake if CONFIG_USB_REMOTE_WAKEUP is not definedNicolas Boichat2017-08-122-4/+0
| | | | | | | | | | | | | | Removes clutter in callers, so that they do not have to wrap usb_wake calls around ifdefs. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I8641cb7aff702920aaa119e644dc812d5c3e774b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/612220 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: Increase resume timeout to 3 secondsNicolas Boichat2017-08-061-1/+1
| | | | | | | | | | | | | | | | | | | When resuming from S3, it may take a while for the bus to become alive again, so let's increase the timeout. 3 seconds is probably a bit too long, but should work for our purpose: we just do not want to be stuck in that state forever. BRANCH=none BUG=b:35587173 TEST=Use powerd_dbus_suspend to put poppy in S3. Press key, see that hosts sometimes takes ~90ms, but sometimes up to 1.5s to resume. Change-Id: Ic800481b2b500fb68a8d1de16b11cbe77a4013d4 Reviewed-on: https://chromium-review.googlesource.com/569523 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: Fix resume handler in usb_wakeNicolas Boichat2017-08-061-11/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the previous version of the code, we were counting ESOF (every ms) to figure out when to clear the resume bit, and then using ESOF counts again to wait for the USB interface to resume. This missed the fact that ESOF (expected SOF) interrupts are not triggered when SOF are actually received. Somehow, this worked fine in most cases, except that sometimes the last ESOF would race with the RXDP/RXDM going to state 2, and we would not know that the resume completed successfully. Let's also count SOF interrupts, and also take a received SOF as an indicator of a successful resume. While we're at it, trim down USB debugging messages, and add a line when resume is successful. BRANCH=none BUG=b:35587173 TEST=Connect hammer, force autosuspend using: DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct)) echo 500 > $DEVICE/power/autosuspend_delay_ms echo auto > $DEVICE/power/control Add debugging in hammer code, make sure that usb_wake_done goes back to 1 after resume succeeds. Change-Id: I206c9c6b3066a3a337b6bd2370c9d0c6a9e2396c Reviewed-on: https://chromium-review.googlesource.com/569522 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fix compilation with coreboot-sdkStefan Reinauer2017-08-042-15/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Reinauer <reinauer@google.com> BRANCH=none BUG=none TEST=The following sequence passes sudo emerge coreboot-sdk export CROSS_COMPILE_arm=/opt/coreboot-sdk/bin/arm-eabi- export CROSS_COMPILE_i386=/opt/coreboot-sdk/bin/i386-elf- export CROSS_COMPILE_nds=/opt/coreboot-sdk/bin/nds32le-elf- make buildall -j Change-Id: I4cafbcd70efd6bdf102f848f1cca4772b4ccd10e Reviewed-on: https://chromium-review.googlesource.com/595207 Commit-Ready: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* usb_hid_*: Fix __packed struct coding styleNicolas Boichat2017-08-021-2/+2
| | | | | | | | | | | | | | | | EC code style should use __packed at the end of the structure, rather than __attribute__((__packed__)). BRANCH=none BUG=none TEST=Flash hammer Change-Id: Ib5dc71a8439038d46b9bc331bdabff7c57c7300a Signed-off-by: Nicolas Boichat <drinkcat@google.com> Reviewed-on: https://chromium-review.googlesource.com/597037 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid_touchpad: Widen pressure field to 10 bitsNicolas Boichat2017-07-311-7/+7
| | | | | | | | | | | | | | | | | | | | id only really needs 4 bits (16 touch events should be more than enough), so we can steal 2 bits from that field. We also reorder the fields to make sure that width/x are aligned on 8-bit boundary. BRANCH=none BUG=b:63936194 TEST=Flash hammer, touchpad works, ABS_PRESSURE > 255 is reported when a palm is pressed on the touchpad. Change-Id: I1abf1bf53cc9dd998082cea5dc7cd3be17f99ec6 Reviewed-on: https://chromium-review.googlesource.com/583297 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: KT Liao <kt.liao@emc.com.tw>
* stm32f4: Add OTP support.Gwendal Grignou2017-07-284-0/+136
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for OTP memory: if needed store serial number in first bank. BUG=chromium:746471 BRANCH=none TEST=On sweetberry, check we can write serial number with serialno command. Check serial number survive a firmware update. First, check without write protect, check we can write 0s (but not 1s) serialno Serial number: NNNNNNNNNNNNNNNNNNNNNN > > serial set MMMMMMMMMMMMMMMMMMMMMMMMMMMMM Saving serial number Serial number: LLLLLLLLLLLLLLLLLLLLLL After lock enabled, check we can not overwrite. > serial set AMMMMMMMMMMMMMMMMMMMMMMMMMMMM Saving serial number Serial number: LLLLLLLLLLLLLLLLLLLLLL Access Denied Check that serialno returns "Uninitialized" if it was never set. Change-Id: I9ab08486a7c3e1958e964649640d69b5b70947e3 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/580290 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* Add OTP supportGwendal Grignou2017-07-282-26/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One Time Programmable memory can be used to store permanent data like serial numbers. Reorganize the code to support writing serial number to OTP, in addition to pstate (if using its own memory bank) or autogenerate from unique id (hammer). + Add CONFIG_OTP to enable OTP code + Add CONFIG_SERIALNO_LEN to indicate the size of the serial number string. Currently set to 28, when USB serial number is needed. + Expose flash_read|write_pstate_serial and add otp_read|write_serail, remove more generic flash_read|write_serial. + Make board_read|write_serial generic, declared outside of USB subsystem. Priority order to read|write serial string: - board definition (like hammer) - pstate location, if stored in its private memory bank - otp area If none of these methods are available, a compilation error is raised. BUG=chromium:746471 BRANCH=none TEST=compile Change-Id: I3d16125a6c0f424fb30e38123e63cf074b3cb2d3 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/580289 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* chip/stm32/usb_hid_touchpad: Move all finger data to a macroNicolas Boichat2017-07-271-142/+34
| | | | | | | | | | | | | | Reduces code duplication, makes changes easier. BRANCH=none BUG=b:63936194 TEST=Flash hammer, touchpad works Change-Id: I14539fa2611cdc0151c05bc83470265a2bb9faec Reviewed-on: https://chromium-review.googlesource.com/583296 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Chun-ta Lin <itspeter@chromium.org>
* sweetberry: allow larger sense resistorsNick Sanders2017-07-241-6/+11
| | | | | | | | | | | | | | | | | | Currently sweetberry hits an integer truncation issue at 2.4 ohm when uA per div goes below 1. We can use 100ths of a uA as the current per div scale. BRANCH=None BUG=chromium:608039 TEST=log from sweetberry with 10 ohm config. Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I9e9216230329483fd0bfcb44ce23cd15bae864b3 Reviewed-on: https://chromium-review.googlesource.com/577051 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* stm32f4: Set unique ID properlyGwendal Grignou2017-07-201-1/+5
| | | | | | | | | | | | | | | | | | Unique device ID register (96 bits) is at a different place on STM32F4 compared to other STM32. BUG=none BRANCH=none TEST=Using board_read_serial() from hammer/board.c in sweetberry/board.c, confirmed that we can extract and assign a unique USB serial number. Change-Id: Idb257f0f20422482c729a2b97b4b16ee231ca4d9 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/579575 Commit-Ready: Gwendal Grignou <gwendal@google.com> Tested-by: Gwendal Grignou <gwendal@google.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32: gpio: implement gpio_disable_interruptWei-Ning Huang2017-07-171-0/+13
| | | | | | | | | | | | | | | | gpio_disable_interrupt is missing for stm32, add it so board functions can use it. BRANCH=none BUG=b:63685022 TEST=`make BOARD=rose -j` Change-Id: Ibbdd8506540e7949fa110c26131dca028671be06 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/573981 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* servo_micro: add parity settingNick Sanders2017-07-135-0/+138
| | | | | | | | | | | | | | Add a control interface to set parity for USB-UART bridge. BRANCH=None BUG=b:37513705 TEST=parity settable on command line or by servod Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: Ib859a70981162be58edfa79c7cb267e0084e05e6 Reviewed-on: https://chromium-review.googlesource.com/564150 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/stm32/i2c-stm32f0: Adjust 400kHz setting (48Mhz clock source)Nicolas Boichat2017-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STM32 I2C frequency can be computed as such: tSCL = tSYNC1 + tSYNC2 + { [(SCLH+1) + (SCLL+1)] x (PRESC+1) x tI2CCLK } The default values we use come from the datasheet, which assume, for 400 kHz setting, that tSYNC1 + tSYNC2 = 750 ns, and therefore set tSCLH as 500 ns and tSCLL as 1250ns. On hammer, we measured a total tSCL of ~2150 ns (465 kHz) with these settings, so we can easily slow it down to ~2500 ns (400 kHz) by increasing tSCLH to 750 ns (SCLH = 0x5). As highlighted in 48b2edf031b "stm32f0/i2c: adjust the 100kHz setting to never go above 100kHz" this has the disadvantage of slowing down other boards where the RC value on the I2C bus are different, but slowing down should always be safe, and is the best we can do without adding config defines for the fall/rise time. BRANCH=none BUG=b:36172041 TEST=Flash hammer, measure SCL frequency to be about 400 kHz Change-Id: Ia2cac9fb09228abd8a318d57335855be529485c2 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/563219 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/flash-f: Clear option byte write enable/erase operation when doneNicolas Boichat2017-07-072-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before 72afc55bd9d3 "stm32: cleanup flash-f by using constant from register.h" lock() function would simply do: STM32_FLASH_CR = FLASH_CR_LOCK; which would clear all other bits in STM32_FLASH_CR, including FLASH_CR_OPTER and FLASH_CR_OPTWRE. This allow preserve_optb to work, as it does: 1. erase_optb a. unlock() b. Set FLASH_CR_OPTER c. lock() (clears FLASH_CR_OPTER!) 2. write_optb a. unlock() b. Set FLASH_CR_OPTPG c. Write option byte d. Clear FLASH_CR_OPTPG e. lock() After the patch, we now have: STM32_FLASH_CR |= FLASH_CR_LOCK; which seems more correct. However, 1.c. does not clear FLASH_CR_OPTER, and 2.b. ends up with both FLASH_CR_OPTPG and FLASH_CR_OPTER set, and the programming operation does not do anything. This patches does 3 things: - Rename FLASH_CR_OPTSTRT to FLASH_CR_OPTER, as that's the correct register name for STM32F0 and STM32F3. - Fix the above by clearing FLASH_CR_OPTER in erase_optb - Also clear FLASH_CR_OPTWRE in lock(). Not strictly necessary, but this seems to be the right thing to do. BRANCH=none BUG=chromium:739608 TEST=On hammer, type flashwp true; reboot; flashwp all; reboot flashinfo => All flash is protected Change-Id: Ic276545ae3c0bdb685c7b117a7f896ec341731bb Reviewed-on: https://chromium-review.googlesource.com/562839 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/flash-f: Fix incorrect WP computationNicolas Boichat2017-07-061-3/+0
| | | | | | | | | | | | | | | | PSTATE is already included in WP_BANK_OFFSET + WP_BANK_COUNT, so this change is not only unnecessary, but also harmful. BRANCH=none BUG=chromium:739608 TEST=Flash hammer, flashwp true; reboot; flashinfo => RO is protected Change-Id: I31048c0156eff354fbcc6ae5828a6ef313b56b97 Reviewed-on: https://chromium-review.googlesource.com/561037 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/registers.h: Fix STM32_FLASH_OPT_LOCKED polarityNicolas Boichat2017-07-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | We currently set STM32_FLASH_OPT_LOCKED to (STM32_FLASH_CR & FLASH_CR_OPTWRE), however the bit is set when option byte are _unlocked_. From STM32F0 Reference Manual: Bit 9 OPTWRE: Option byte write enable When set, the option byte can be programmed. This bit is set on writing the correct key sequence to the FLASH_OPTKEYR register. This bit can be reset by software BRANCH=none BUG=chromium:739608 TEST=Flash hammer, flashwp true; reboot; flashinfo => hammer does not hang on reboot, RO is protected Change-Id: I1b6eb5d638534ece90d6d5164586f49bdb0c151d Reviewed-on: https://chromium-review.googlesource.com/561036 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/pwm: Prevent sleeping while PWM output is activeNicolas Boichat2017-07-041-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | | STM32F0 cannot keep PWM output active when chip is in deep sleep. The only other board that uses both CONFIG_LOW_POWER_IDLE and CONFIG_PWM on stm32 is jerry, and this logic should also apply to it. Also, switch using_pwm from array to bitmask to simplify handling. BRANCH=none BUG=b:36173380 TEST=On AP, tell it to autosuspend hammer: echo auto > /sys/bus/usb/devices/1-2/power/control Then see, using idlestats, that hammer does to deep sleep. In hammer console: pwm 0 50, see that PWM output is stable, idlestats shows EC does not sleep. In hammer console: pwm 0 -1, idlestats shows EC sleeps again. Change-Id: Ic74c1905364fe4335239da95a99193d0e3e979f7 Reviewed-on: https://chromium-review.googlesource.com/541115 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f4: fix flash_physical_protect_now behaviorWei-Ning Huang2017-06-283-115/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flash_physical_protect_now(), which is called when EC_FLASH_PROTECT_ALL_NOW is set, should protect the entire flash temporarily until reboot. Current behavior enable flash protect on all region permanently. The correct implementation should be writing an invalid key to the flash controller to disable flash flash only temporarily until reboot. Since the implementation of flash-stm32f3 and flash-stm32f4 is almost the same after restoring the changes made in commit 35f4d8acaa40050f10158459a04e0bf9b24149c6, we merge to file by creating a symlink from flash-stm32f3.c to flash-stm32f4.c to reduce code duplication. BRANCH=none BUG=b:37584134 TEST=on eve: 1) `ectool --name=cros_tp flashprotect` Flash protect flags: 0x00000008 wp_gpio_asserted 2) `flashrom -p ec:type=tp --wp-enable 3) `ectool --name=cros_tp reboot_ec` 3) `flashrom -p ec:type=tp --wp-status` WP: status: 0x80 WP: status.srp0: 1 WP: write protect is enabled. WP: write protect range: start=0x00000000, len=0x00040000 4) `ectool --name=cros_tp flashprotect`, all_now should present Flash protect flags: 0x0000000f wp_gpio_asserted ro_at_boot ro_now \ all_now 5) `ectool --name=cros_tp reboot_ec; sleep 0.3; \ ectool --name=cros_tp rwsigaction abort` to stay in RO. In EC console, `flashinfo`, should show that only RO is actually flash protected: Protected now: YYYYYY.. 6) `flashrom -p ec:type=tp -w ec.bin -i EC_RW` works 7) `make BOARD=ryu -j` works (for testing flash-stm32f3.c) Change-Id: Ia7a60ae8b3084198abb468e4fc8074b4445d6915 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/549681 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* watchdog: Don't discard irqprio data due to CONFIG_LTOShawn Nematbakhsh2017-06-262-2/+2
| | | | | | | | | | | | | | | | | | | | | Don't discard irqprio data when the IRQ_PRIORITY macro is used directly (for watchdog / watchdog timer). This change is probably a NOP for all platforms, since the power-on default for the IRQ prio register seems to be zero, which is the same priority we're setting in our direct use of IRQ_PRIORITY. BUG=chromium:634701 BRANCH=None TEST=Verify 'prio_44' entry exists in irqprio section by checking ec.RO.map on kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idaffc484a2ce4749c18212f179b3951ff570aed0 Reviewed-on: https://chromium-review.googlesource.com/545201 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f4: clock stm32f412 at 96MHzWei-Ning Huang2017-06-218-10/+54
| | | | | | | | | | | | | | | | | | | | | | On stm32f412, AHB prescaler must be 1 in order for stm32f412 to be clocked at greater than 50MHz. APBX prescaler must be 2 so the clocks can be in the right range. When APBX prescaler != 1, it results in 2x timer clocks on both APB1 and APB2. We added a new clock_get_timer_freq() function for stm32 to get timer specific clock frequency so we can return 2x timer clocks when APBX != 1. Flash latencies also need to be changed when we clock at 96MHz, the FLASH_ACR_LATENCY defines are moved into the variant-specific switches so each board can defined latency when setting CPU clocks. BUG=b:38077127 TEST=`make BOARD=rose -j`, touch performance improved by 2x. Change-Id: Ieb211ad80c168d3f57e72a8d16b954b703ee1444 Reviewed-on: https://chromium-review.googlesource.com/539375 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* stm32: flash: enable data and instruction cache properlyWei-Ning Huang2017-06-202-1/+19
| | | | | | | | | | | | | | | | | | | | | The flash controller of STM32F4 and STM32L4 supports data and instruction caching. Enable them properly. BRANCH=none BUG=b:38077127 TEST=on rose, > rw 0x40023c00 read 0x40023c00 = 0x00000701 Touch process loop is 5% faster. Change-Id: Ibb28c0ed0c6a293547d5f0f7c6962f36fa417dd3 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/497230 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32/usb: Add support for board-specific serial numberNicolas Boichat2017-06-132-2/+16
| | | | | | | | | | | | | | | | | | | By default, read USB serial number from flash, but provide a way for boards to override the function (e.g., to read serial number from unique chip id). BRANCH=none BUG=b:62280271 TEST=Flash hammer lsusb -d 18d1:5022 -v -v | grep iSerial shows different chip IDs on different boards. Change-Id: I0917752bb8e04c1eff4dffc0b3714f63dcd942b0 Reviewed-on: https://chromium-review.googlesource.com/523045 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Add function to fetch unique idNicolas Boichat2017-06-122-1/+9
| | | | | | | | | | | | | | BRANCH=none BUG=b:62280271 TEST=Flash hammer lsusb -d 18d1:5022 -v -v | grep iSerial shows different chip IDs on different boards. Change-Id: Id56b4509f184eb722d04fef94079c150dc2016e2 Reviewed-on: https://chromium-review.googlesource.com/523044 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* board: Add support for nucleo-f411reGwendal Grignou2017-06-061-24/+38
| | | | | | | | | | | | | | | | | Add nucleo-f411re for testing STM32F411. Fix registers.h to include F411 specific features. TEST=Check uart,gpio works. Check BMI160 accel/gyro sensor works over i2c Install firmware with "make BOARD=nucleo-f411re flash" BUG=b:38018926 BRANCH=none Change-Id: I8514d1aa48e06708053e72f8d4be15738eda6cf4 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/249994 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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