summaryrefslogtreecommitdiff
path: root/chip/stm32
Commit message (Collapse)AuthorAgeFilesLines
* chip/stm32: Only use a mutex when not in interrupt contextTom Hughes2020-10-091-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mutexes shouldn't be used in interrupt context. An ASSERT was added in mutex_lock to verify this commit e6956209119d2b2c1f45401855019e3a0a2f7dd5. There are cases where bkpdata_write can be called from an interrupt context, such as this stack trace that occurs when adding entropy from RO on dartmonkey/icetower (stack captured with Segger J-Trace): > rollbackaddent 1234 panic_assert_fail panic_output.c:132 mutex_lock task.c:889 bkpdata_write bkpdata.c:35 bkpdata_write bkpdata.c:24 bkpdata_write_reset_flags bkpdata.c:86 chip_save_reset_flags system.c:366 system_reset system.c:366 panic_reboot panic_output.c:114 report_panic panic.c:339 exception_panic panic.c:350 Validation of the fix was checked with the "rollback_region1" unit test, which failed before the change and works after. BRANCH=none BUG=b:170147314 TEST=./test/run_device_tests.py -b dartmonkey -t rollback_region1 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ie5509ec024e94b48c786199ccbb81ce93fafe547 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2462545 Reviewed-by: Edward Hill <ecgh@chromium.org>
* core: rename atomic_clear to atomic_clear_bitsDawid Niedzwiecki2020-10-061-2/+2
| | | | | | | | | | | | | | | | | | Change the name of atomic_clear to atomic_clear_bits to make to name more clear - the function clears only selected bits, but the name may suggest that it clears the whole variable. It is done as a part of porting to Zephyr, where atomic_clear zeros the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I7b0b47959c6c54af40f61bca8d9baebaa0375970 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428943 Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32g4: Initial UCPD driver for type-c functionalityScott Collyer2020-09-294-0/+582
| | | | | | | | | | | | | | | | | | | | | The STM32G4 contains a UCPD block that includes similar functions as a TCPC. This CL contains an initial version of the driver required to use this function. This CL adds register block definitions and the implementation of tcpci driver functions required to support type-c operation. This CL does not include support for USB-PD functionality. BUG=b:167601672 BRANCH=None TEST=verfied type-c attaches properly on quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I3e7912f33efa716501896b1f96b4c6d67db0f573 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213840 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* honeybuns: Increase flash size to work with RO onlyScott Collyer2020-09-291-1/+6
| | | | | | | | | | | | | | | | | | | | | We don't have enough flash space on to do a full RO + RW image. This CL simply adjusts the flash size define from 128k to 256k and only the RO image is only being used for development and HW verification. Note also that at this stage there is no support for RO -> RW jump other than using EC console command, so RO is the only image being executed. BUG=b:167462264 BRANCH=None TEST=make -j BOARD=quiche is successful. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Iec062f9f3be966c0653cbdafe72f5a160351cf07 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213839 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-298-13/+15
| | | | | | | | | | | | | | | | We will move to an API compatible with Zephyr's API. See the bug for complete rationale and plan. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id611f663446abf00b24298a669f2ae47fef7f632 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427507 Tested-by: Dawid Niedźwiecki <dn@semihalf.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Bloonchipper: Reduce usart transport's response size to 0x100Bhanu Prakash Maiya2020-09-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Bloonchipper firmware uses usart_host_command.c to communicate with Zork's AP. On AMD SoC we found there is a 256 byte UART FIFO limitation with Designware's UART IP. Typically DMA should have solved this issue but looks like Picasso and Dali, UART DMA is not working at expected. This is causing timeout issues with EC responses > 256 bytes. This patch will limit the response size to 256 bytes which ensures that AP RX packets always stay within FIFO limits. Currently UART based host command transport is only used by FPMCU Dragonclaw STM32 design. BRANCH=none BUG=b:160208269 TEST=1. Run bloonchipper binary on Zork FPMCU devices. 2. Check PCO/DALI do not throw UART DMA overrun interrupt. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Change-Id: I0b99d25cf7d2dd163d05c35585064ad5e61a91ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428203 Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@googlers.com> Tested-by: Bhanu Prakash Maiya <bhanumaiya@googlers.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@googlers.com> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@googlers.com>
* stm32g4: Update dma channels for USARTScott Collyer2020-09-081-6/+6
| | | | | | | | | | | | | | | | This CL adjusts the DMA channel assignment for the USART that's used for EC console. BUG=b:148493929 BRANCH=None TEST=verfied ec console works on quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I87aecdbc16667adc87e15f0158b71cfa39c706c6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213941 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Specify correct ARM core and CPU flagsScott Collyer2020-08-311-1/+2
| | | | | | | | | | | | | | | | The only change required for build.mk is to specify the correct ARM core and machine instruction set. BUG=b:148493929 BRANCH=None TEST=verfied image builds successfully. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I267dfbe54de153c8687f5048fdcccf65ac15678f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195551 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Add flash support for stm32g4 chip familyScott Collyer2020-08-314-83/+91
| | | | | | | | | | | | | | | | | | | This CL adds support for flashing stm32g4. The L4 family has the same flash module and so that was used as basis for G4 driver. This CL renames the l4 flash driver to capture this commonality. In addition, the flash register definitions in G4 registers file was updated appropriately. Previously, this section matched F4 requirements. BUG=b:148493929 BRANCH=None TEST=verfied usb-ep fw update completes successfully Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I6cc818c6329524924534b0566bd9d24145c86c72 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195547 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org>
* stm32l4: Refactor to use page instead of bank notationScott Collyer2020-08-312-31/+77
| | | | | | | | | | | | | | | | | | The L4 and G4 family share the same flash peripheral block. Therefore, the G4 can share the L4 driver. This CL adds macros which more closely track the TRM description of the flash module, especially w.r.t pages. There is no functional change for the L4 driver. BUG=b:148493929 BRANCH=None TEST=make -j BOARD=stm32l476g-eval is successful Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ie2c16ef2b8fa0e35f5945fb124765039f8ea22c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2376388 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Fix build issue with i2c driverScott Collyer2020-08-292-2/+1
| | | | | | | | | | | | | | | This CL fixes 2 minor issues which with the i2c driver file. BUG=b:148493929 BRANCH=None TEST=verfied honeybuns builds correctly. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ide6aafd4e4296891579fa138ec0d3e54a4ed9c6d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2376828 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* usbc: remove PD_EVENT_SM in favor of task_wakeJett Rink2020-08-211-1/+1
| | | | | | | | | | | | | | | | We have used both methods of waking up the PD tasks to process the next state: PD_EVENT_SM and TASK_EVENT_WAKE. They effectively do the same thing and it is more straightforward to only have one way to wake the task up with the sole purpose of re-evaluating the current state. BRANCH=none BUG=none TEST=No regressions on GRL testing. Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I0fa79b82223e6b97eede4130480156949d79f365 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2363466 Reviewed-by: Edward Hill <ecgh@chromium.org>
* task: Change mutex_lock() assertEdward Hill2020-08-151-7/+3
| | | | | | | | | | | | | | | | | | | Instead of asserting that task_start() has not been called, just return without doing any locking. This avoids the need to fix every caller of mutex_lock() to check task_start_called(). BUG=b:164461158 BRANCH=none TEST=Esc+F3+Power enters recovery, does not assert. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ic157d7e7041185a67f257f0f5710fd02e45cd77f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2357496 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* COIL: change usage of sanityDaisuke Nojiri2020-08-141-1/+1
| | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "sanity" with inclusive alternatives. BUG=b:163885307 BRANCH=None TEST=make -j buildall TEST=grep -ir sanity Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I487a50999d506a0337f1d3fbe173f193e5e4098a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2353516 Reviewed-by: Sam Hurst <shurst@google.com>
* stm32g4: Add I2C supportScott Collyer2020-08-132-11/+472
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the i2c driver for stm32g4 chip family. The i2c block for stm32g4 is very similar to that of stm32l4 chip family. The g4 driver is mostly copied from the L4 version of the i2c driver. However, the driver only currently supports master mode. BUG=b:148493929 BRANCH=None TEST=run i2scan on EC console > i2cscan Scanning 0 usbc................. 0x18. 0x19. 0x1a. 0x1b. 0x1c. 0x1d. 0x1e. 0x1f. 0x20. 0x21. 0x22. 0x23. 0x24. 0x25. 0x26. 0x27........................... 0x42.............................. 0x60....................... Scanning 1 usb_mst. 0x08. 0x09. 0x0a. 0x0b. 0x0c. 0x0d. 0x0e. 0x0f. 0x10. 0x11. 0x12. 0x13. 0x14. 0x15. 0x16. 0x17... 0x1a........................... 0x35............ 0x41......... 0x4a. 0x4b...................... 0x61...................... Scanning 2 eeprom......................................... 0x30................................ 0x50....................................... Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Id8b7472e579bae17360a0122fe2b12a333139cfa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2161580 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Fix max clock freq and flash wait stateScott Collyer2020-08-131-5/+5
| | | | | | | | | | | | | | | | | | | | | The clock frequency macro added in previous CL was missing the '0'. This CL fixes that error and makes a minor change to how the flash wait state value is configured. Previously, setting of the wait state field was disabling instruction/data cache until it was restored in the next instruction. This results in swd debugger not remaining attached. BUG=b:148493929 BRANCH=None TEST=verified console is working and debugger remains attached after setting wait state to the correct value. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I65e3a22e36de0bbf14926e5687a995b7e5717e7f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340695 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-121-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. Add check for task_start_called() for NPCX flash_lock, I2C port_mutex, pwr_5v_ctl_mtx, STM32 bkpdata_write_mutex. This was submitted CL:2309057, reverted CL:2323704, submitted CL:2335738, reverted CL:2341706. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I0aadf29d073f0d3d798432099bd024a058332412 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2343450 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* ec: change usage of dummySam Hurst2020-08-0512-34/+34
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* stm32g4: Set uart frequency and enable clocks for stm32g4Scott Collyer2020-07-311-3/+3
| | | | | | | | | | | | | | | | This CL adds changes to enable clocks and configure the uart speed for stm32g4 chip family. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I5600ed64867192fe77fd85fc3dbc0a63f912d738 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195550 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Modify channel select to use DMAMUX for stm32g4Scott Collyer2020-07-311-2/+15
| | | | | | | | | | | | | | | | | | The STM32G4 family chips have similar DMA engine as some other STM32 families and therefore most of DMA code can simply be used as is. However, the STM32G4 does have a DMAMUX and so the correct peripheral request must be set. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I2694881f97558ea7b904a9b83ee20d9ec813c273 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195549 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* spi: Use different hooks for SPI enable/disableWai-Hong Tam2020-07-301-0/+9
| | | | | | | | | | | | | | | | | | | If CONFIG_CHIPSET_RESUME_INIT_HOOK is defined, move the SPI enable/disable to different hooks, i.e. * RESUME_INIT instead of RESUME * SUSPEND_COMPLETE instead SUSPEND The SPI interface has to be enable earlier than other hooks to receive a host sleep event. BRANCH=None BUG=b:148149387 TEST=make buildall -j Change-Id: Ic56a7b5ef20fb8258487d1d350fc5f8a55e33049 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324989 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* stm: rtc: Prevent locking a mutex in interrupt contextWai-Hong Tam2020-07-301-1/+9
| | | | | | | | | | | | | | | | | In the RTC interrupt, it calls host_set_single_event() directly, that eventually tries to lock a mutex. Trying to lock a mutex in the interrupt context should be forbidden. So move the call to a deferred function. BRANCH=None BUG=b:162434716 TEST=Build the board scarlet, which uses stm and enables RTC host command. Change-Id: I3f5ab85549a801f4f5d72cf5661a65c9f9d28e0c Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2327249 Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
* stm32g4: Add clock enable logic for HW timerScott Collyer2020-07-291-0/+11
| | | | | | | | | | | | | | | | This CL adds clock enable support for stm32g4 family. BUG=b:148493929 BRANCH=None TEST=verfied that via scope that led toggle happens at 1 second window when using one second hook call. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ie3d353ec40206e93cfac7b8738166ffee6c8442c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195548 Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Add gpio supportScott Collyer2020-07-291-0/+66
| | | | | | | | | | | | | | | | | This CL adds stm32g4 chip specific changes. Most of gpio code can be reused as is. This file enables clocks and IRQs for supported GPIO banks. This was based on F4 family as the reference. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I47d0b08675b53597b5a0e938d576682e63cc59e0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195546 Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Clock module driverScott Collyer2020-07-291-0/+277
| | | | | | | | | | | | | | | | | | | | This CL adds support to configure rcc module for stm32g4. The driver from the F4 family was used as a reference. Support for RTC was not ported as it's not being used for honeybuns. The function wait_for_ready() was moved to the common clock file for the F-family so it would not need to be replicated for G4 as well. BUG=148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I980c8889965a2e5da401ccd6291079a0bdfa8e4f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195545 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Modifications required for system.cScott Collyer2020-07-291-1/+15
| | | | | | | | | | | | | | | | | This CL updates stm32 specific system.c for the stm32g4 chip family. A comment was added to clarify what's required for enabling the backup domain. In addition, debug mode and detection of a warm boot. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I8b5063419ae6dc1be165b8bb3754703c1e728ae9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195544 Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Add config-chip for stm32g41xbScott Collyer2020-07-292-0/+46
| | | | | | | | | | | | | | | | This CL adds config-chip for stm32g41xb variant of the stm32g4 chip family. BUG=148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I418179153b631e2d7abb597fbf77374f94c4c501 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195543 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Fix issue with APB1 base addressScott Collyer2020-07-291-1/+1
| | | | | | | | | | | | | | | | The initial version of this file had a cut/paste error. Fixing the base address for APB1 bus BUG=148493929 BRANCH=None TEST=make BOARD=quiche is successful Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I5c2abc0342bde4a66f166f87971617110c5acfd5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324403 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org>
* Make wait_for_ready available for allDaisuke Nojiri2020-07-285-61/+10
| | | | | | | | | | | | | | | | | | | wait_for_ready is a generic function which loops until bits in a register are set. This patch move it to util.c to make it available for all. There are more places where the function is applicable but this CL keeps the scope under chip/stm32/clock-stm32. There is no functionality change. BUG=none BRANCH=none TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I796599344c1d86ab7144d1d6b434ec54cf1cc55d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2317887 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* servo: Adds USB SPI protocol V2 commands and responsesBrian J. Nemec2020-07-243-103/+629
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the USB SPI protocol V2, this protocol supports larger SPI transfers that are delivered in multiple USB packets. This enables us to perform 2 optimizations on the USB SPI transfer speed for large USB packets: * USB packets can be grouped together reducing the total number of packets exchanged. The host can write multiple data sections sequentially without the device responding with a packet for each one. Going the other direction, the host can continue to poll the device for data until the transmission is complete. * Only a single SPI transaction is required, this eliminates overhead in setting up and getting data from SPI transactions. Benchmark results show a typical 35% improvement in performance on Servo Micro platforms with these changes on operations which involve large SPI transfers reading or writing from the flash. Signed-off-by: Brian Nemec <bnemec@chromium.org> Blocked on upstream changes to flashrom: Depends-On:https://review.coreboot.org/c/flashrom/+/41533 BUG=b:139058552 BRANCH=servo TEST=Tested with Servo Micro with the reading, erase, write, and verify operations with updated copies of flashrom. Change-Id: I04b6cf8449e32cc1b75d3501939958887eb57f5b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224765 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org> Tested-by: Brian Nemec <bnemec@chromium.org>
* stm32g4: Add registers file for stm32g4 chip familyScott Collyer2020-07-232-0/+1275
| | | | | | | | | | | | | | | | This CL adds the registers definition file for stm32g4. It was based off the registers file for the stm32f4 chip family. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I4de8e4ed955714d35e75e0c0c5de83a3d8c4c996 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092492 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* EC: Add additional stack sizesSam Hurst2020-07-071-0/+2
| | | | | | | | | | | | | | | | | Add two additional stack sizes for tasks that need more stack space. BRANCH=none BUG=b:155813111 TEST=make -j buildall Manual: Changed waddledee's TypeC ports0 and 1 to ULTRA_STACK_SIZE and TRENTA_STACK_SIZE and make -j buildall without errors. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I927d5b978c705f49d1b3a85a09c4020d7fd9ee84 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2280486 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Bloonchipper: USART based transport layer for host commandBhanu Prakash Maiya2020-06-0512-17/+1008
| | | | | | | | | | | | | | | | | | | | 1. USART host command layer in chip/stm32 2. Fix usart implementation in stm32 BUG=b:147849609 BRANCH=none TEST=1. make BOARD=bloonchipper -j 2. usart request and response works on dragonclaw Change-Id: Idd89d3e490f23aa528ecaf6510c13d16b405de13 Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2190531 Tested-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@chromium.org>
* servo: Add USB SPI helper functions and context statesBrian J. Nemec2020-06-052-86/+325
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds context states to USB SPI for handling receiving and transmitting data. These context states allow us to keep track of data buffers that can not fit within a single USB packet. A context state has been added to describe the USB packets accepted by the USB SPI protocol. This structure includes union fields for easily addressing the different packet's fields and to describe the basic attributes for a USB packet including its size and how many bytes are allocated to the header. Helper functions process the USB packets and aid in the transfer of data between them and receive and transmission buffers. BUG=b:139058552 BRANCH=servo TEST=Tested with Servo Micro reading and verifying flash writes are successful in a loop. Signed-off-by: Brian Nemec <bnemec@chromium.org> Change-Id: I3e0b31f33f442719123b9e897495cad25e9e6ed4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224764 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org>
* ec: Minor cleanup of magic number commonly used in STM32 USBBrian J. Nemec2020-06-045-4/+8
| | | | | | | | | | | | | | | | | Minor cleanup of a commonly used magic number in the STM32 USB interface. BUG=none BRANCH=none TEST=Builds Signed-off-by: Brian Nemec <bnemec@chromium.org> Change-Id: I2c0b7947810aae651e452db42ac27221ab19b99b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224763 Tested-by: Brian Nemec <bnemec@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org>
* chip/stm32: Don't reset the backup domain when initializing clockYicheng Li2020-06-031-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | For the STM32F4 chip family, this software reset of the backup domain causes the RTC backup registers to be reset, which causes all backup data to be lost. The reset flag was not impacted because it's copied out before this reset. BRANCH=none BUG=b:157059753 TEST=make -j BOARD=bloonchipper test-scratchpad On console: > runtest => PASS > reboot > runtest => FAIL, which is CORRECT Signed-off-by: Yicheng Li <yichengli@chromium.org> Change-Id: I85777b7d8a99561198d0b9dc1f795b8f8f6e26c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226955 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Tom Hughes <tomhughes@chromium.org>
* stm32: Disable option bytes if RO is protected on bootTom Hughes2020-05-302-5/+12
| | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:155897971 TEST=On bloonchipper after flashing flash_write_protect.bin test: * Enable HW WP: dut-control fw_wp_en:on * Reboot to RO: reboot ro * Enable flash protection: runtest 1 => PASS * Reboot to RO: reboot ro * Try to disable flash protection: runtest 2 => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ie7bc4d8b518ef1387f77666072a510a8fbfb1d90 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220738 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* test: Add tests for flash option bytes and control registerTom Hughes2020-05-301-0/+6
| | | | | | | | | | | | | | | BRANCH=none BUG=b:155897971 TEST=On dragonclaw v0.2 with Segger J-Trace and servo micro attached: ./test/run_device_tests.py -t flash_physical => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I9a71cdcc2947d13cf2f1d44fdbd57cf20ed6402f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220737 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32: Add helper functions for flash control registersTom Hughes2020-05-303-28/+154
| | | | | | | | | | | | | | | | | | | | No functional change. Improves readability and allows re-use for validation in unit tests. BRANCH=none BUG=b:155897971 TEST=On dragonclaw v0.2 with Segger J-Trace and servo micro attached: ./test/run_device_tests.py -t flash_physical => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ib06fb483f5936dd09e6a39ef515d8b2cbff747e4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2220735 Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/stm32: Save STAY_IN_RO flag if set during resetTom Hughes2020-05-141-0/+4
| | | | | | | | | | | | | | | This matches the behavior of system_encode_save_flags() and allows us to reboot into RO for testing. BRANCH=none BUG=b:156401765 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibbb95ca81fb87eaa48639dea99be1bd0e35ea230 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2197621 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* stm32: Add chip_read_reset_flags and chip_save_reset_flagsDaisuke Nojiri2020-05-061-3/+13
| | | | | | | | | | | | | | | | | | | | | Battery backed up RAM is used to store the reset flags. This patch wraps the code reading and writing the reset flags with APIs for the consistency and make it available to external callers. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1078470 BRANCH=none TEST=buildall Change-Id: Ica31008b8f0f89f6804002c2c796e3b3c117e06a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182563 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* test: Add on-device unit test for STM32 RTCTom Hughes2020-04-301-0/+1
| | | | | | | | | | | | BRANCH=none BUG=b:151105339 TEST=make BOARD=bloonchipper test-stm32f_rtc -j Flash stm32f_rtc.bin and "runtest" in the console Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I3debfd93b62cb269ad61af0e4ca7e195554b5548 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171569 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* c2d2/servo_micro: invert SDA during ITE programming seqJett Rink2020-04-162-2/+8
| | | | | | | | | | | | | | | | | | | According to programming guide, the SDA signal (200kHz) should have its rising edge in the middle of the SCL (100kHz) transition. Since the timers are starting at the same time, inverting the SDA timer will achieve this. This will affect both servo_micro and c2d2 BRANCH=servo BUG=b:153393490 TEST=verify with scope on C2D2 is SDA/SCL signals match programming guide Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: Ibda89a30f77d39c633f491840b82f7b1dee552c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142561 Reviewed-by: Matthew Blecker <matthewb@chromium.org>
* ec: Enlarged Task Stack size on platformsBrian J. Nemec2020-04-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The task stack size of is small enough that the process was triggering stack overflows when responding to commands. These actions had a small chance of causing EC hardfaults. This was apparent with the gpioget command which had the attributes of performing many calls to a printf function which also has many parameters. Since the structure of a printf with 10 or more parameters is common when constructing console responses, this enlarges the stack for that task. This is more important since the probability of it creating a hardfault is low. To reduce the chance of this issue on other platforms, the platforms with 488 byte tasks were also enlarged to 512 bytes. BUG=chromium:1056780 BRANCH=none TEST=Connected servod to servo_v4 looped the command 'dut-control servo_v4_uart_cmd:gpioget' 1000 times TEST=make buildall -j Verified free ram space remains over 60 bytes on impacted platforms Change-Id: I6b50b204c83a10068153f3e01bc134446047f235 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2133130 Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cleanup: drop the _TYPEC part of USB device configJett Rink2020-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The three USB device configurations describe more than just the Type-C layer, so remove the _TYPEC part within the define. This is also in preparation to change how the usbc build.mk includes files. This was performed with the following commands: $ git grep --name-only CONFIG_USB_TYPEC_DRP_ACC_TRYSRC | xargs perl -i -ple 's/CONFIG_USB_TYPEC_DRP_ACC_TRYSRC/CONFIG_USB_DRP_ACC_TRYSRC/g' $ git grep --name-only CONFIG_USB_TYPEC_CTVPD | xargs perl -i -ple 's/CONFIG_USB_TYPEC_CTVPD/CONFIG_USB_CTVPD/g' $ git grep --name-only CONFIG_USB_TYPEC_VPD | xargs perl -i -ple 's/CONFIG_USB_TYPEC_VPD/CONFIG_USB_VPD/g' BRANCH=none BUG=none TEST=builds Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I4deab784b7c3479cffd3dee7fb3ea3c8a9d6081c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2121193 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* stm32f412: Fix chip config Flash and RAM sizesCraig Hesling2020-03-242-4/+13
| | | | | | | | | | | | | | | | | | We are already using the stm32f446 config for many F4 based chips. Let's actually make this more clear and un-hack our hatch_fp board.h. This present no functional change. BRANCH=none BUG=none TEST=./util/compare_builds.sh -b "hatch_fp sweetberry" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I6b46e696686ad740833dc889c1db5d7bac84a768 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2109244 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* stm32: Refactor clock-stm32h7.cCraig Hesling2020-03-201-70/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This cleans up and modularizes the clock configuration code for the STM32H743. This makes it easier and cleaner to add the STM32H7A3 variant. This brings no functional change, as coarsely verified with crrev.com/c/2096017 . BRANCH=icetower BUG=b:130296790 TEST=Verified all impacted registers values with and without this change using crrev.com/c/2096017 on the Nucleo-H743ZI. The sequence of commands used to test was the following: # After fresh startup (from reset) * > clock * > clock hsi * > clock pll * > clock hsi * > clock hsi * > clock * > waitms 5000 * # Run timer to check accuracy of 5 seconds * > clock pll * > waitms 5000 * # Still broken -> Watchdog should still kick-in early and render MCU unusable. Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4fbf6982190c0d660e31c2027b5ad07cae48755e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2095853 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* chip: stm32: fix TIM9 interrupt for STM32F412Virendra Kakade2020-03-201-0/+4
| | | | | | | | | | | | | | | | | | | | | Currently the TIM9 global interrupt is mapped to 25 instead of 24 which causes the interrupt to not work. Fix this by changing the mapping. RM0402 STM32F412 reference manual: Vector table for STM32F412xx (table 40); TIM1_BRK_TIM9 entry. BUG=none BRANCH=none TEST=make -j4 buildall TEST=TIM9 interrupt works after this change on STM32F412 board. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com> Change-Id: I18ee7cda79e78c01bc561b1d70d2a25fa3aed5a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2098872 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org> Tested-by: Craig Hesling <hesling@chromium.org>
* stm32: pwm: fix timer PSC register calculationVirendra Kakade2020-03-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | The timer PSC register value is calculated based on the cpu clock frequency but it should actually be based on the timer clock frequency. Timer clock frequency and cpu clock frequency may be the same or different based on the STM32 variant. Example: In the STM32F412 case, timer freq = cpu freq * 2. This leads to incorrect PSC calculation based on old formula, ultimately leading to a frequency twice that of requested. BUG=none BRANCH=none TEST=make -j4 buildall TEST=verified that I got expected frequency on a stm32f412 pwm output with this change. Change-Id: I9ff954cf6304507f7506f5cf974857f6c3140b4e Signed-off-by: Virendra Kakade <virendra.kakade@ni.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2096841 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32: Fix manual interrupt clearing functionCraig Hesling2020-03-121-1/+3
| | | | | | | | | | | | | | | | | | | This fixes a bug in gpio_clear_pending_interrupt, where all pending interrupts are unintentionally cleared. This is not in the code path for normal gpio interrupt handlers, since the normal interrupt clearing occurs in gpio_interrupt (right below this function). BRANCH=none BUG=chromium:1059520 TEST=none Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4d6fe7947f4d76cf3b57dfbf3bb926e41851c80c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2101208 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
View Lorry Controller Status