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* chip/stm32: Make function definition and declaration matchTom Hughes2021-09-292-2/+2
| | | | | | | | | | | | | | | | | | | "test_mockable_static" is static, but the declaration created by DECLARE_IRQ is not static. The mismatch generates a compiler warning when building with clang: chip/stm32/clock-f.c:325:6: error: unused function '__rtc_alarm_irq' [-Werror,-Wunused-function] void __rtc_alarm_irq(void) BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I39e2de93b057b5565c54ffb83e1633a13db1ce46 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172039 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* chip/stm32: UART declarations for STM32L5 seriesJes B. Klinke2021-09-082-1/+164
| | | | | | | | | | | | | | | STM32L5 can have up to four UARTs, one more than previous Lx series. These files were copied from usart-stm32l.{h,c}, modified only by making one more copy of the appropriate declarations. BUG=b:192262089 TEST=Compile with hyperdebug board (from later in the chain) BRANCH=none Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Change-Id: I8bd2d13de67fc74b59c16a79a87fd4615912be09 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3133814 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* chip/stm32: Factor family specific clock logic out of usb.cJes B. Klinke2021-09-085-32/+71
| | | | | | | | | | | | | | | | | | | | | | | The register for enabling USB register clock appears to have been identical across F0, F3, and G4 families, but for L5 it is different. Rather than having #ifdef in usb.c (as I recently committed), this CL will move the clock logic into clock_enable_module() where it arguably belonged all the time. Additionally: Some of the chip families make use of a clock_mask in their implementation of clock_enable_module(), but since the module_id enum has more than 32 value, until now, some values (among those MODULE_USB) would result in overflow, causing new_mask to be identical to clock_mask, and the USB case could have never been reached. BUG=b:192262089 TEST=Compile servo_v4 without linker errors BRANCH=none Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Change-Id: I7c29339f45eb513e3e78f662797a70543912c8c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130733 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* TCPM: Rename enum tcpm_sop_type and its constantsAbe Levkoy2021-08-312-16/+16
| | | | | | | | | | | | | | | As a followup to CL:3104290, give the TCPCI TRANSMIT and RX_BUF_FRAME_TYPE types more consistent names. Most of them can be used for receiving, not just transmitting. Fix lint errors thus revealed. BUG=b:155476419 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I399ec479eacc18622fc4d3f55f8bdabf4560fcff Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3125995 Reviewed-by: Keith Short <keithshort@chromium.org>
* adc: Include adc_chip.h from adc.hCaveh Jalali2021-08-275-13/+0
| | | | | | | | | | | | | | | | This reorganizes adc.h and adc_chip.h so that general code only needs to know about adc.h. adc_chip.h is now included by adc.h directly and does not need to be included in general code. BRANCH=none BUG=b:181271666 TEST=buildall passes (with next patch in series) Cq-Depend: chromium:3120316 Change-Id: I8bc107c6900e831a57f7a7fb8668eb08bb179d6c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3120315 Reviewed-by: Keith Short <keithshort@chromium.org>
* chip/stm32: Add initial support for STM32L5xx seriesJes B. Klinke2021-08-2514-5/+2586
| | | | | | | | | | | | | | | | Introduce L5xx mostly as copy of L4xx, though registers-stm32l5.c is extensively modified. BUG=b:192262089 TEST=Compile and upload board/hyperdebug to Nucleo board BRANCH=none Signed-off-by: Jes B. Klinke <jbk@opentitan.org> Change-Id: Iccc7b05e4f2dfa732559b8099cf856882401e31c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3086362 Tested-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org>
* system: fix system_get_scratchpad APIYuval Peress2021-08-201-2/+3
| | | | | | | | | | | | | | | The current API for system_get_scratchpad mixes the status and the value being read. Update the signature to allow both. BRANCH=none BUG=b:195481980 TEST=make testall && zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I3a5f5ad523d507c53a5d474806f58afafb82e70c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074828 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* TCPM: Rename enum tcpm_transmit_typeAbe Levkoy2021-08-182-8/+8
| | | | | | | | | | | | | | | Rename tcpm_transmit_type to tcpm_sop_type to reflect that it can be used for Rx as well. Describe it in comments. This prepares to consolidate enum pd_msg_type into this enum. BUG=b:155476419 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Ife97d4ad51c48f2e832b94e007954919e236a309 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104290 Reviewed-by: Keith Short <keithshort@chromium.org>
* usb_hid_keyboard: fix incorrect sleep/lock key positionTing Shen2021-08-171-1/+2
| | | | | | | | | | | | | | | | | The position of SLEEP_KEY_MASK bit is not in its intended position because TK_* enum is 1-indexed. Fix this bug by shift the mask by 1. BUG=b:196934919 TEST=evtest BRANCH=trogdor Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I900636f032786510f7870948d1856d0bc4374800 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097478 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* stm32/usb_hid_keyboard; implement new top row keysTing Shen2021-08-091-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the hid usage mapping from drivers/hid/hid-input.c: Page 0xB, Usage 0x2F -> KEY_MICMUTE Page 0xC, Usage 0x7C -> KEY_KBDILLUMTOGGLE BUG=b:194460146 TEST=Map the new keys to F1/F2 on homestar, and verify 1) kernal can get the expected key code. Event: -------------- SYN_REPORT ------------ Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value b002f Event: type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1 Event: -------------- SYN_REPORT ------------ Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value b002f Event: type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 0 Event: -------------- SYN_REPORT ------------ Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value c007c Event: type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), value 1 Event: -------------- SYN_REPORT ------------ Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value c007c Event: type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), value 0 2) `cat /sys/class/input/*/device/function_row_physmap` BRANCH=trogdor Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ibf342b881ee428598adaeb73a63bf242cd220004 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3073440 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* stm32/usb_hid_keyboard: fix feature report data sizeTing Shen2021-08-041-1/+2
| | | | | | | | | | | | | | | | | | | | The usb hid driver always send 60 bytes feature report to the host, this causes host side unhappy because the received data is larger than expected. Fix this bug by sending what we actually declared. BUG=b:195264416 TEST=# cat /sys/class/input/*/device/function_row_physmap C0224 C0227 C0232 C029F 70046 C0070 C006F C00E2 C00EA C00E9 BRANCH=trogdor Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I536e4518a76606a05c006d459d6ffbb61858c2d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066973 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* stm32: change stm32l431 flash layoutBossen WU2021-07-202-1/+54
| | | | | | | | | | | | | | | Due to increase of RW size, stm32l431 flash layout were change to RO: 124KB, PSTATE: 2KB, RW:130KB BRANCH=kukui BUG=b:188117811 TEST=make BOARD=munna; make buidall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I8cf2d2dbdc8a2ae5e95d1d54c6672796eb02fc02 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3037292 Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* stm32: clock: avoid division by zero worries.Bossen WU2021-07-021-4/+4
| | | | | | | | | | | | | | | In chip_config.h, PLLM / PLLN / PLLR was predefined as 0. It raise concern that frequency calculation would have division by zero issue. Redefine PLLM / PLLN / PLLR as 1 to remove such worry. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: If57aa40af29e0176762a981bd5b2dac9528b1144 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999412 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : flashBossen WU2021-07-012-7/+44
| | | | | | | | | | | | | | | stm32l431 related driver: flash-stm32g4-l4.c system.c The stm32l476g-eval is the only board which would be possibly impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I273954c75651b20de58db53eba7e7d0e4553763d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2978652 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : adcBossen WU2021-07-012-1/+258
| | | | | | | | | | | | | | stm32l431 related driver: adc-stm32l4.c adc_chip.h The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I0ce73ee9ab02e1cfd20a178628d935d24a1907ce Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975521 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : dmaBossen WU2021-07-011-6/+29
| | | | | | | | | | | | | | stm32l431 related driver: dma The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: Ia513875963c2c65f6b63605fc113f139656a4028 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975520 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : i2cBossen WU2021-07-011-19/+25
| | | | | | | | | | | | | | | stm32l431 related driver: i2c-stm32l4 The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: If6187e6f3c2f82ab118524444c1849108bb82f82 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975519 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : uartBossen WU2021-06-301-4/+28
| | | | | | | | | | | | | | | stm32l431 related driver: uart The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I861d1cf38430d6b1b5d7c09bd565d727961a4128 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975168 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : watchdogBossen WU2021-06-301-1/+30
| | | | | | | | | | | | | | stm32l431 related driver: watchdog. The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I8488a3bfad31dadedc65078d29c117cfb2308f77 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975160 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : system / clock / timerBossen WU2021-06-307-498/+2575
| | | | | | | | | | | | | | stm32l431 related driver: system / clock / timer. The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: Idf335005d8188f6959835aa40179a6bd771c5114 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905165 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: rename CONFIG_STM32_SPI1_MASTER to …CONTROLLERHarry Cutts2021-06-252-9/+9
| | | | | | | | | | | | | In line with OSHWA terminology. BUG=b:181607131 TEST=make -j BOARD=hammer BRANCH=none Change-Id: I6d212e60d5aceb8497f00520b693006cc1af2d45 Signed-off-by: Harry Cutts <hcutts@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981123 Reviewed-by: caveh jalali <caveh@chromium.org>
* stm32/system: Disable caches before rebootPatryk Duda2021-06-101-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi This fixes problem with jumping to RW when reboot to RO was requested. Log from reproduction on dartmonkey (only relevant parts): --- UART initialized after reboot --- [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft ap-off] ... [1.045743 Jumping to image RW] *** We are in RW. Jump data are initialized and contains correct *** set of reset flags. Reset flags from backup RAM are cleared. reset flags from chip: unknown reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RW, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] ... > > reboot ro reboot ro Rebooting! *** Now we are in RO. RW saved reset cause in backup RAM (with *** stay-in-ro). Please note that RO also finds jump data and *** report that was sysjump! reset flags from chip: reset-pin power-on soft ap-off stay-in-ro reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] When RO is doing sysjump to RW, jump data structure is created in jump_to_image() function. The structure contains information about reset flags. When RW finds jump data in system_common_pre_init() magic field of the structure is set to zero to prevent detecting sysjump accidentally. Nevertheless, when reboot to RO is requested, RO is able to find the structure. As a result, correct reset flags from backup RAM are overwritten by incorrect reset flags from jump data. This happens because we are not flushing D-cache before reboot. All changes in RW which lives in cache (not saved in RAM) will be lost after reboot because cache is always disabled (even if it was previously enabled and we didn't turned it off). To enable cache we need to invalidate it first (see cpu_enable_caches()). Issue reproduces also with debugger connected, except situation when watchpoint is set on jump data magic field. BUG=b:170432597 b:188934337 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, issue 'reboot ro'. Make sure that jump to RO is not performed. TEST=Run flash_write_protect hardware unit test on icetower board using `./test/run_device_tests.py --board dartmonkey \ --tests flash_write_protect` Make sure that after reboot to RO, 'stay-in-ro' reset cause is printed Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: If56153a1a3ac7ae05700eac9ca60e398cf35f182 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922145 Reviewed-by: Craig Hesling <hesling@chromium.org>
* stm32f4: undef CONFIG_CMD_CHARGENNamyoon Woo2021-06-101-0/+2
| | | | | | | | | | | | | | | | This patch excludes CONFIG_CMD_CHARGEN from stm32f4 build config set explicitly. stm32f4 has its own USB console implementation, which chargen doesn't support yet. The affected boards are polyberry, sweetberry and stm32f446e-eval. BUG=none BRANCH=all TEST=buildall Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: I0f3dadd55fa2c197fff32afbe3fecb773491003e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2951862 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32/flash-stm32h7: Use udelay() in flash_physical_erase()Patryk Duda2021-06-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replacing usleep() with udelay() fixes problem with Forced Hard Fault during rollback_entropy hardware unit test (more precisely, when rollback entropy is added). Function rollback_update() calls unlock_rollback() before erasing rollback region. Surprisingly, unlock_rollback() also disables interrupts to "minimize time protection is left open". Next flash_erase() is called and then flash_physical_erase(). If erase operation is not finished, we will call usleep() to yield CPU to some other task. It sounds good, but remember that interrupts are still disabled. To switch context we need to use SVCall exception (see svc_handler()) which is masked when interrupts are disabled. Sometimes sector was erased before we checked, so no usleep() was called. That's why it was not reproducing always. Why Forced Hard Fault occurs when calling SVC with disabled interrupts? First of all, we need to know that some exceptions have configurable priority, SVCall belongs to this group (full list can be found at 2.4.2 Exception types PM0253 Rev 5 p.40). Next thing is that we are using 'CPSID I' instruction to disable interrutps. The instruction actually sets PRIMASK register (3.12.2 CPS PM0253 Rev 5 p.176). When PRIMASK register is set it prevents activation of all exceptions with configurable priority (PM0253 Rev 5 p.25), so SVCall is masked too. OK! But why we get Forced Hard Fault? Hard Fault is 'Forced' when some other fault was escalated to Hard Fault (FORCED bit is set in HFSR register). 2.5.2 Fault escalation and hard faults PM0253 Rev 5 p.48 provides us information when escalation to Hard Fault occurs, among others it can occur when "A fault occurs and the handler for that fault is not enabled". BUG=b:170432597, b:180761547 BRANCH=none TEST=Connect icetower using microservo. sudo servod --board icetower ./test/run_device_tests.py --board dartmonkey --test rollback_entropy Make sure that test is passed and no Hard Fault occur. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I0dc1dae899b81574456a127db9c5e7a498a6f69e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939676 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* include/flash: rename the APIsTim Lin2021-06-098-83/+88
| | | | | | | | | | | | | | | | The names conflict when enabling both Zephyr's flash driver and CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h BUG=b:187192628 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* COIL: Rename CONFIG_SPI_MASTER to CONFIG_SPI_CONTROLLERCaveh Jalali2021-06-031-1/+1
| | | | | | | | | | | | | | | | This replaces the CONFIG_SPI_MASTERR config option with CONFIG_SPI_CONTROLLER. BRANCH=none BUG=b:181607131 TEST=make buildall passes; "compare_build.sh -b all" shows no difference Change-Id: I3c921085179294765baadf7074652978fe04a4ed Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932465 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org>
* stm32g4: ucpd: Clear tx interrupts before enableScott Collyer2021-05-271-26/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ucpd driver enables, then disables tx interrupts before and after each message is sent. This CL fixes an issue where tx interrupts weren't guaranteed to be cleared prior to enabling. This was leading to instances where the tx data byte interrupt wasn't firing when expected. The failure was exposed following a VCONN swap when VCONN is turned on. The UCPD driver will remove Rp from the CC line which has VCONN. The following PS_Rdy message would fail. Debugging this issue also led to observe that when Rp is removed for VCONN active CC lines, Rp would be applied again when Rp is adjusted by TCPM as part of collision avoidance. BUG=b:189293176 BRANCH=quiche TEST=Tested on quiche against kohaku host machine. Repro case was very consistent. Verified that failures were present without the fix in this CL. Then verified that after fixing interrupt issue, there were no hard reset/soft reset events follwoing VCONN swaps. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I289b5b5a60bbe7e880ff6b7f6fd9e5b0182f67a0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2917643 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* stm32g4: flash: Add DBANK support to option bytes WRPScott Collyer2021-05-273-60/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds support for the option bytes for dual-bank (DBANK) mode in category 3 devices. The MCU being used on honeybuns, is a category 3 flash device and DBANK mode is enalbed in the option bytes by default. When DBANK mode is enabled, then more than 1 WRP register is needed to protect the RW image. In this mode, WRP register can only protect 64 flash pages in one flash bank. BUG=b:183686750 BRANCH=quiche TEST= Case 1: HW WP active and code executing in RW > flashinfo Usable: 256 KB Write: 4 B (ideal 4 B) Erase: 2048 B (to 1-bits) Protect: 2048 B flash-phy: WRP_RO: start = 0, end = 31 flash-phy: WRP_RW: start = 32, end = 127 Flags: wp_gpio_asserted ro_at_boot ro_now all_now Protected now: YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY Case 2: HW WP active active and code executing in RO flashinfo Usable: 256 KB Write: 4 B (ideal 4 B) Erase: 2048 B (to 1-bits) Protect: 2048 B flash-phy: WRP_RO: start = 0, end = 31 flash-phy: WRP_RW: start = 127, end = 0 Flags: wp_gpio_asserted ro_at_boot ro_now Protected now: YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ Case 3: HW WP disabled > flashinfo Usable: 256 KB Write: 4 B (ideal 4 B) Erase: 2048 B (to 1-bits) Protect: 2048 B flash-phy: WRP_RO: start = 127, end = 0 flash-phy: WRP_RW: start = 127, end = 0 Flags: ro_at_boot Protected now: ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I72c03029b0231ee864afc967905c50acba4ba5de Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911738 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32/system: Wait for RVU bit clear before updating IWDG_RLRPatryk Duda2021-05-262-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC is not waiting for IWDG_RLR value to be updated in watchdog_init() function. It's intended behaviour because updating value can take much time (even 48ms) which is not desired during initialization. It's also allowed by documentation too: RM0433 Rev 7 Section 45.4.4 Page 1920 https://www.st.com/resource/en/reference_manual/dm00314099.pdf If several reload, prescaler, or window values are used by the application, it is mandatory to wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset before changing the prescaler value, and to wait until WVU bit is reset before changing the window value. However, after updating the prescaler and/or the reload/window value it is not necessary to wait until RVU or PVU or WVU is reset before continuing code execution except in case of low-power mode entry. Documentation clearly states that before next Reload Register update we are obligated to wait until RVU bit in IWDG_SR register is cleared. Setting IWDG_RLR register when RVU bit is set causes new value to be ignored. This is exactly the behaviour observed while running flash_write_protect hardware unit test. Time of Step 2 execution is short enough to perform hard reboot (all reboots between test steps are hard) when RVU bit is set. As a result setting IWDG_RLR to 1 is ignored and watchdog is reloaded with old value. This is why it takes very long to perform hard reset and watchdog trace is printed. Platforms affected by this change: STM32H7: nocturne_fp (dartmonkey) nucleo-h743zi STM32F4: hatch_fp (bloonchipper) nucleo-f411re nucleo-f412zg polyberry sweetberry stm32f446e-eval BUG=b:170432597 BRANCH=none TEST=Run flash_write_protect hardware unit test on icetower board using `./test/run_device_tests.py --board dartmonkey \ --tests flash_write_protect` Make sure that test passes and no watchdog traces appear. TEST=Run flash_write_protect hardware unit test on dragonclaw 0.2 board using `./test/run_device_tests.py --board bloonchipper \ --tests flash_write_protect` Make sure that test passes and no watchdog traces appear. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I2585dcbf3cb1a14107c7ae674c51999f082e3df7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2917115 Reviewed-by: Craig Hesling <hesling@chromium.org>
* stm32: Add helper function for H7 flash ctrl regsJosie Nordrum2021-05-114-105/+199
| | | | | | | | | | | | | | | | | | | Add helper function definitions for H7 to API added in chromium:2220735. This should enable flash_physical test to run on Dartmonkey. Refactor code to pull flash registers function declarations from flash-reg.h instead of flash-f.h BRANCH=None BUG=b:157692395 TEST=On dartmonkey ./test/run_device_tests.py -t flash_physical => pass Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I76846938748cbe77d534915856af0ebb7211d247 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2576799 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* panic.c: force sync before reenabling bus faultsJosie Nordrum2021-05-111-3/+0
| | | | | | | | | | | | | | | | | | Force a sync between data and instruction pipelines before allowing bus faults. Remove sync from flash-stm32h7.c BRANCH=None BUG=b:157692395 TEST=tested with crrev.com/c/2576799 Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: Id67324191b4447d9be10c0b5aecc87620aa69d1d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706039 Tested-by: Josie Nordrum <josienordrum@google.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Josie Nordrum <josienordrum@google.com> Auto-Submit: Josie Nordrum <josienordrum@google.com>
* usb-ep: Add config option to define VIDScott Collyer2021-05-021-1/+1
| | | | | | | | | | | | | | | | | This value was previously hardcoded to Google's VID. However, some products with USB-EP support may require a different VID to correctly support fwupd. BUG=b:181920029 BRANCH=quiche TEST=verified that fwupd works on baklava Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I23c36507a90428ab46cd5efde7d79581207bde74 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2848424 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32gx: ucpd: BIST mode control and correct nRetryCountScott Collyer2021-03-312-11/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | This CL implements the driver method to enable/disable BIST test mode in the ucpd driver. When this mode is enabled, the upcd driver only needs to send GoodCRC messages in response to BIST data messages which are received. This CL also fixes the value of nRetryCount to make it based off the port partner'd USB-PD version. BUG=b:181179550 BRANCH=None TEST=Manual Verified that nRetryCount fix enables TD.PD.LL.E3. Soft Reset Usage to pass. Verfied that adding BIST mode control enables TD.PD.PHY.E1. BIST Test Data to pass. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I251e1c3c235d976d934406cdb22df0c177c6f14b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2667241 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: ucpd: Fix tx hard reset and msg discard handlingScott Collyer2021-03-311-27/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL fixes the ucpd hard reset transmit path. There was code missing to set the ucpd event to send a hard reset. In addition, there was a code bug where wrong bit in tx_request was being cleared. This CL also adds message discard handling as required in the prl_tx state machine. There is now an event set when a message is received so the transmit state machine can discard a tx message that is being requested to be sent, or was discarded by the ucpd peripheral. This CL also adds ucpd state logging function which can be display via the existing command 'ucpd info'. BUG=b:181179550 BRANCH=None TEST=manual Connected to host machine (kohaku) and verified hard reset is sent after ec console command 'pd 0 hard' with TotalPhase For discard message fixes, used kohaku with custom FW to send a SVDM command, immediately following by get sink cap message. I then added variable delay in tcpmv2 svdm response path to force collisions in usb rev2.0 mode. By varying this delay, I was able to test various collision paths to ensure messages were being discarded when expected. In addition, I looked at console logs when running VDMU.e16 compliance test. > ucpd info cc1 = Rp cc2 = Rp Rp = Rp_3.0 cc1_v = 2 cc2_v = 1 rx_en = 1 pol = 0 ucpd: tx_state = TX_IDLE, tx_req = 00, timeout_us = -1 UCDP Task Log [0]: ACT_TCPM WAIT_CRC 00 00000020 026252441 1000 [1]: WAIT_CRC TX_IDLE 00 00000100 026252963 -1 [2]: TX_IDLE ACT_TCPM 01 00000002 026306381 -1 [3]: ACT_TCPM WAIT_CRC 00 00000020 026307170 1000 [4]: WAIT_CRC TX_IDLE 00 00000100 026307691 -1 Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I9f351c762069ee17684b6918bc3cca973439156a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2787240 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: ucpd: Move hbit clock config macros to .h fileScott Collyer2021-03-242-26/+29
| | | | | | | | | | | | | | | | | | | Honeybuns needs to preset Rd on both CC lines while in RO. But, it does not have a full usbc/pd stack. The ucpd driver file is not included either. However, ucpd needs some basic initialization so that Rd can be applied correctly. This CL moves the macros which are required to configure the ucpd clocks to the .h file. BUG=b:172493899 BRANCH=None TEST=make BOARD=quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I07614a941a05fa133ab4504d9241249066f41e29 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2772738 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Sam Hurst <shurst@google.com> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* chip/stm32: Rename field since "or" is reserved in C++Tom Hughes2021-03-161-1/+1
| | | | | | | | | | | | | | https://en.cppreference.com/w/cpp/keyword https://en.cppreference.com/w/cpp/keyword/or BRANCH=none BUG=b:144959033 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I8ac62e6fbcab8fe0c842c737d183b462899bd017 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2740563 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* chip/stm32: Remove duplicate macrosTom Hughes2021-03-163-171/+0
| | | | | | | | | | | | | | Re-defining a macro is an error in C++. BRANCH=none BUG=b:144959033 TEST=make buildall TEST=./util/compare_build.sh --boards all --ref1 HEAD --ref2 HEAD^ Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: If8329bc9e79e153961c8ddfb4ddb1c01cdb9b112 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2740562 Reviewed-by: Craig Hesling <hesling@chromium.org>
* ucpd: Add support to turn off type-2 BIST modeScott Collyer2021-03-161-6/+22
| | | | | | | | | | | | | | | | | | | This CL adds changes to the ucpd driver to support turning off BIST mode once it's been started. For ucpd, the peripheral has to be disabled and reset for this purpose. BUG=b:182436876 BRANCH=None TEST=Verfied that honeybuns can pass TDA.2.1.1.1: BMC-PHY-TX-EYE compliance test, which previously was failing because BIST type-2 mode was not being stopped. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ib6aa898ef5727dd5887e5d1c0b2eee94fdb366b3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2751328 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Add support for stm32g473xc variantScott Collyer2021-03-043-6/+67
| | | | | | | | | | | | | | | | | | This CL adds the stm32g473xc variant to the STM32G4 family. The primary change is that the internal flash is increased from 128 to 256kB. In addition, the stm32g431xb flash size is set back to its actual value of 128kB. BUG=b:167462264 BRANCH=None TEST=make -j BOARD=quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I163b6044d48425c70f9e6c5d7e352d5c1dd7df72 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2682783 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Add USB endpoint supportScott Collyer2021-03-045-4/+56
| | | | | | | | | | | | | | | | | | | This CL enables USB-EP for the STM32G4 family. It also fixes backup domain register access issues which are required for fw updates via USB. BUG=b:148493929 BRANCH=None TEST=Verified on quiche that STM32G4 enumerates as an USB endpoint and can be used successfully with fwupd. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I75e6b6e70e9ca2589ace76f0aa0facadd9e94142 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2268139 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* panicinfo: fix panicinfo double reportEric Yilun Lin2021-03-042-2/+14
| | | | | | | | | | | | | | | | | | | | | | Panicinfo is double report due to the panic flags is reset whenever a hard-reset triggered. This makes AP thinks there is a new panic happened, and reports it to the crashmon. We've seen a lot of crash reports due to the false alarms. The solution is recording the panic flags across hard-reset so we won't keep alarming the old panicinfo. BUG=b:181108236 TEST=1)test that on juniper with new EC RO/RW, and AP reboot won't cause the EC alarming a new panicinfo. 2)test that on juniper with soft-sync RW, and old RO, and AP reboot won't cause the EC alarm a new panicinfo BRANCH=kukui Change-Id: I6e0c33a1fcf210d9aa03ebd1cd79b84a7744c386 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2721327 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* servo_v4p1: Fix communication with ATmega32 keyboard emulatorMichał Barnaś2021-02-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Fix queue used in USART TX of STM32 interrupt handler. It was using producer queue instead of consumer, which resulted in no data transmitted through usart. BUG=b:179284396 BRANCH=main TEST=Flash servo_v4p1 and run servod without board parameter. There should be no error like: ServoUSBkm232Handler - ERROR - Atmega KB offline: failed to communicate. TEST=Flash servo_v4p1. Connect DUT charger to servo_v4p1 and servo to DUT. Run servod with board specified. Enable keyboard emulator: dut-control init_usb_keyboard:on Execute in terminal: socat readline $(dut-control atmega_pty | cut -d: -f2) Writing any data should result in random characters appearing on DUT. Signed-off-by: Michał Barnaś <mb@semihalf.com> Change-Id: Ia4fe26dcbd7146eb202b948a5f03c04b1c673001 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2673411 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32: assume no vbnvJack Rosenthal2021-02-033-34/+2
| | | | | | | | | | | | | | | | | | CONFIG_HOSTCMD_VBNV_CONTEXT is deprecated and removed. Cleanup preprocessor statements to assume it's never defined. This makes CONFIG_STM32_RESET_FLAGS_EXTENDED obsolete, since it's now always defined, so that gets removed too. BUG=b:178689388 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id040ce2ceca95ecde37de0014aafdbfd3087e00d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2668688 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* Remove CONFIG_HOSTCMD_VBNV_CONTEXTJack Rosenthal2021-02-021-10/+0
| | | | | | | | | | | | | | This is no longer set by any boards, and we don't intend to use it on future projects again. BUG=b:178689388 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I7aa64d52bc197778873e7eb880961c37fb9f34e6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2657721 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* spi: Pass in spi_device as argument to spi_enable instead of portTom Hughes2021-01-282-52/+35
| | | | | | | | | | | | | | | | | | | | | | Rather than passing in the port and iterating over the global spi_devices variable, pass in the specific spi_device that is being enabled/disabled. The spi_device_t struct has the port. This change makes the functions in spi.h more consistent since they now all take a spi_device_t*. This change is the first step in making the SPI configuration more dynamic. BRANCH=none BUG=b:177908650 TEST=git grep 'spi_enable(CONFIG' => no results TEST=make buildall TEST=Flash dragonclaw v0.2 and view console to verify FP sensor ID Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I64124e0ebcf898e88496acb77703b5f59ae931c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2654081 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-1517-31/+31
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* version: Rename version.h to cros_version.hYuval Peress2021-01-071-1/+1
| | | | | | | | | | | | | | | This change simply moves the include/version.h file over to avoid a naming collision with zephyr's version.h. BRANCH=none BUG=b:167392037 TEST=make buildall -j Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ib41b3c21817d5f81e713d3b550bc46a0d1c55cf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612772 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* chip/stm32/usb_hid_keyboard: Implement HID GET_REPORTNicolas Boichat2020-12-231-3/+9
| | | | | | | | | | | | | | | Implement HID GET_REPORT with INPUT type. BRANCH=nocturne,kukui BUG=b:174539061 TEST=With associated kernel CL: cd /sys/bus/usb/drivers/usbhid echo 1-1.1:1.0 > unbind; echo 1-1.1:1.0 > bind Change-Id: If62c92e55fa5454116816681c2ab46d5e796c4b5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2578620 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* stm32g4: ucpd: Add missing tcpci methodsScott Collyer2020-12-223-3/+103
| | | | | | | | | | | | | | | | | This CL adds a VCONN enabe/disable support function to remove the pull resistor and 2 addiltional functions which are required to complete the stm32gx tcpci driver. BUG=b:167601672 BRANCH=None TEST=verfied type-c attaches properly on quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I5a3732f15a5a0af9d372ae37475e9e8bdd3914b4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2588850 Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* stm32g4: ucpd: Add pd msg log and console debug commandsScott Collyer2020-12-221-3/+415
| | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds code to the ucpd driver which can used for additional debug information about both usbc and usb-pd information. The message log contains up to 64 entries which is sufficient to establish a connection and enter alt-dp mode. BUG=b:167601672 BRANCH=None TEST=Connect quiche on host port and validate debug commands: > ucpd info cc1 = Rp cc2 = Rp Rp = Rp_3.0 cc1_v = 1 cc2_v = 2 rx_en = 1 pol = 1 Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I2f50a6284336f21e833ecdff72746ff04c191b52 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531183 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
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