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* stm32g4: ucpd: Add pd msg log and console debug commandsScott Collyer2020-12-221-3/+415
| | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds code to the ucpd driver which can used for additional debug information about both usbc and usb-pd information. The message log contains up to 64 entries which is sufficient to establish a connection and enter alt-dp mode. BUG=b:167601672 BRANCH=None TEST=Connect quiche on host port and validate debug commands: > ucpd info cc1 = Rp cc2 = Rp Rp = Rp_3.0 cc1_v = 1 cc2_v = 2 rx_en = 1 pol = 1 Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I2f50a6284336f21e833ecdff72746ff04c191b52 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2531183 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-145-14/+13
| | | | | | | | | | | | | | | | | | | | There is an option in the task_set_event function which force the calling task to wait for an event. However, the option is never used thus remove it. This also will help in the Zephyr migration process. BUG=b:172360521 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* stm32g4: ucpd: Add support for USB-PD messagingScott Collyer2020-12-133-26/+729
| | | | | | | | | | | | | | | | | | | | | This CL adds routines required to support USB-PD messaging to the UCPD driver. UCPD is performs TCPC type functions, but is not a TCPC. UCPD does utilize the common TCPCI APIs as entry points called from the port's PD task. In addition, UCPD has its own task to manage more easily transmit requests from TCPM layer and GoodCRC messages which must be intiated in the UCPD driver itself. BUG=b:167601672 BRANCH=None TEST=verfied type-c attaches properly on quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I0c02bee4badc479125832a6b5a6fa156e998c201 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2247117 Tested-by: Scott Collyer <scollyer@chromium.org> Auto-Submit: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* stm32: low power configuration for STM32F4Vincent Palatin2020-12-021-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | As most of the peripherals were not implemented to support switching to 16-MHz HSI (e.g. high speed serial port requires a clock input > 24 Mhz), implement a simpler clock scheme than the dynamic between HSI and PLL used other platforms: - the PLL is disabled only when entering the low-power idle and the PLL locking time is added to wake-up time. - when the host is running (not suspended) we stay in a high power mode (~20mW). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, on bloonchipper, check we can still capture fingerprint. read the MCU power consumption: pp3300_dx_mcu_mw is 2.367 mW. BRANCH=fpmcu-bloonchipper Change-Id: Ic1fe015b2501bdea9779a2f63fab296f8812c315 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2555162 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: add STOP mode on STM32F4Vincent Palatin2020-12-021-2/+117
| | | | | | | | | | | | | | | | | Implement a low power idle mode using the STM32F4 STOP mode. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, on bloonchipper, check we can still capture fingerprint. read the MCU power consumption. BRANCH=fpmcu-bloonchipper Change-Id: I11249e9b68c989033263e34e1cde3f19ffe7c54c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2537631 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: fix RTC rounding error breaking alarmsVincent Palatin2020-12-021-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On STM32F4, when converting micro-seconds to the RTC sub-second counter value, the current computation in the us_to_rtcss() routine has a large rounding error which can even led to generate a negative value. When such a negative value is output and then programmed in the (unsigned) RTC_ALRMASSR register used to set the alarm precise sub-second timestamp, it might put a wrong value in the past. As a consequence when the RTC alarm is used a wake-up mechanism for the low power idle, it might never fired and trigger a watchdog reboot. An example of bad values on a STM32F412 with the RTC driven by the 32-kHz LSI: - RTC_PREDIV_A = 1 - RTC_FREQ = (STM32F4_LSI_CLOCK / (RTC_PREDIV_A + 1) = 16000 /* Hz */ - RTC_PREDIV_S = (RTC_FREQ - 1) = 15999 - US_PER_RTC_TICK = 1000000 / RTC_FREQ = 62 /* rounded from 62.5 */ When converting 996000 us, us_to_rtcss(996000) = RTC_PREDIV_S - (us / US_PER_RTC_TICK) = 15999 - (996000 / 62) = -65 returned as a uint32_t as 0xfffffffb. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, with the STOP mode enabled, we no longer see watchdog reboot due to the RTC alarm being set in the past and never firing. TEST=manual, verify that the output of the 'gettime' console command is not drifting compared to the wall clock when the low power idle using the RTC time is used. BRANCH=fpmcu-bloonchipper Change-Id: I53869539828bed9a5900d29407b5feba140b8217 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563684 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: add dynamic clocking for STM32F4Vincent Palatin2020-12-022-92/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow to transition between the PLL to run at full speed and the bare HSI (internal RC oscillator at 16Mhz) to save power. On HSI, as our sysclk frequency is low, we run all peripheral clocks undivided at the same frequency. Keep the configuration for other platforms running from the HSE (external crystal) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, verify the timers are working by checking the output of the 'gettime' console command against the wall clock. TEST=manual, verify the UART console works as expected. TEST=measure MCU power on bloonchipper in various modes through the INA: PLL 19.20 mW HSI 4.73 mW STOP 2.10 mW BRANCH=fpmcu-bloonchipper Change-Id: I1185e04c9a7819fec05dd643b7026116b146f3b8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2527049 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: update the timer pre-scaler on STM32F4Vincent Palatin2020-12-021-2/+3
| | | | | | | | | | | | | | | | | | | | | Add support for changing for the timer source clock frequency on STM32F4 by re-computing the timer pre-scaler value in the HOOK_FREQ_CHANGE callback. Preparatory work to implement power management switching between PLL and HSI as sysclk. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=b:130561737 TEST=manual, verify the output of the 'gettime' console command against the wall clock. BRANCH=fpmcu-bloonchipper Change-Id: Ia7dc24d3b1dbff816b1cebbc87492e678b987dfd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2527048 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* usb_hid_keyboard: implement vivaldi top row featureTing Shen2020-11-271-22/+73
| | | | | | | | | | | | | | | | | | This CL implements a feature report defined in [1] that describes the keyboard's top row layout. [1] http://doc/1NTxSGv3WA2Vn4dlPLOcvKBvPytWOF0UAcIYQaFctTug BUG=b:171156337 TEST=Verify feature report content using test code in CL:2530156. BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I28a93f1b926d58602eb66d1b090e89384cb09f77 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2522641 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* i2c_master: extend i2c_xfer_no_retry to also support large writestabilize-13605.B-masterTing Shen2020-11-171-4/+4
| | | | | | | | | | | | | | | | | This CL extends CONFIG_I2C_XFER_LARGE_READ to also support large (greater than 255 bytes) write. Related config name is also updated to reflect the behavior change, BUG=b:169651794 TEST=flash fw successfully on Zed. BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Icb889013da01f48708cd0227207561b8186bac63 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2537412 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* ucpd: Fix merge error with clock constantsScott Collyer2020-11-121-3/+3
| | | | | | | | | | | | | | | | | This CL fixes an issue with a rebase merge, UCPD_IFRGAP_HBIT_CNT had been changed to UCPD_IFRGAP_CNT in a previous CL. This CL removes HBIT. BUG=b:167601672 BRANCH=None TEST=make BOARD=quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ideff65872d744bc7e3b3cdfa8c5af37f4725be36 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2522649 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* hammer: support vivaldi keyboardTing Shen2020-11-101-1/+112
| | | | | | | | | | | | | | | | | | | | This CL implements vivald function row config for hammer keyboard. If CONFIG_USB_HID_KEYBOARD_VIVALDI defined, STM32 HID keyboard now returns an extra 32-bit data represents the status of action keys. Additionally, if board_vivaldi_keybd_config returns a non-null pointer, driver will convert function keys to action key according to the given config. BUG=b:171156337 TEST=verify keycode is correct in `evtest` BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ide3289fd2c1bb8859a74e97134e6113441cfb967 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508848 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* COIL: Rename CONFIG_I2C_PERIPHERALDiana Z2020-11-051-2/+2
| | | | | | | | | | | | | Rename CONFIG_I2C_PERIPHERAL and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I3f148e976f3a4d6a1dc6c58686368c056290d5d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: Rename CONFIG_I2C_CONTROLLERDiana Z2020-11-052-2/+2
| | | | | | | | | | | | | Rename CONFIG_I2C_CONTROLLER and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: Rename local i2c variables in stm32f4Diana Z2020-11-051-36/+36
| | | | | | | | | | | | | | Rename local i2c variables and related comments to the new controller/peripheral naming scheme. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ibb6a2bdfe47824be6412d999e6c4eb0303e6b421 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518658 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: Rename CONFIG_BOARD_I2C_ADDR_FLAGSDiana Z2020-11-051-8/+8
| | | | | | | | | | | | | Rename CONFIG_BOARD_I2C_ADDR_FLAGS and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I45d4945b5c1fa26c72d233fb9def4d9bdee1c9c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518657 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Replace I2C_GET_ADDR with I2C_STRIP_FLAGSYuval Peress2020-11-026-18/+18
| | | | | | | | | | | | | | | | | The new I2C_STRIP_FLAGS macro was added to avoid conflict with Zephyr's macro. This CL performs the migration to that new API. BRANCH=none BUG=b:172067439 TEST=make runtests -j and built for various boards: eve, volteer, arcada_ish, atlas, hatch, kohaku, nocturne, samus, and scarlet Change-Id: I0583b647435db96ec268f186252b367bdc4118a6 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2511097 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* atomic: rename atomic_read_clear to atomic_clearDawid Niedzwiecki2020-11-024-11/+10
| | | | | | | | | | | | | | | | | Rename atomic_read_clear to atomic_clear to be consistent with the rest of the atomic functions, which return the previous value of the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I2588971bd7687879a28ec637cf5f6c3d27d393f4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505143 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* COIL: Rename SLEEP_MASK_I2C_PERIPHERALDiana Z2020-10-313-6/+6
| | | | | | | | | | | | | Rename SLEEP_MASK_I2C_PERIPHERAL and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Idaeefda102c603a38f128d820ed1f647069eaeea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2511094 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: Rename CONFIG_HOSTCMD_I2C_ADDR_FLAGSDiana Z2020-10-313-16/+16
| | | | | | | | | | | | | Rename for CONFIG_HOSTCMD_I2C_ADDR_FLAGS and surrounding comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I49dc12753957da7baa1bb387e212d75c75e81d86 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2511093 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: Re-name local variables and references in i2c-stm32f0.cDiana Z2020-10-311-18/+18
| | | | | | | | | | | | | | Re-name i2c references to terms controller/peripheral BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I2afa76596890bd9d7e0c51cced76b0f7cc76257b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2493114 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
* chip/stm32: Fix transport detection in RO.Tom Hughes2020-10-301-18/+8
| | | | | | | | | | | | | | | | | | | | | | The FPSENSOR task only runs in RW, not RO, so IS_ENABLED(HAS_TASK_FPSENSOR) is false in RO. As a result, we were returning the wrong protocol information for bloonchipper boards with UART when running in RO. BRANCH=none BUG=b:171370392 TEST=none TEST=Using dragonclaw v0.2 and servo_micro: ./test/run_device_tests.py -t fpsensor_uart_ro ./test/run_device_tests.py -t fpsensor_uart_rw ./test/run_device_tests.py -t fpsensor_spi_ro ./test/run_device_tests.py -t fpsensor_spi_rw Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Iccf801ef453a5dc6d8a21df11af41c60818781b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508861 Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com> Reviewed-by: Yicheng Li <yichengli@chromium.org>
* COIL: Re-name to TCPCI_I2C_PERIPHERALDiana Z2020-10-281-5/+5
| | | | | | | | | | | | | Boards which don't use a TCPM will define TCPCI_I2C_PERIPHERAL. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: If93e533e059888e8ad5166b29c37bc2243f46947 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2481940 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tree: Use new atomic_* implementationDawid Niedzwiecki2020-10-278-15/+15
| | | | | | | | | | | | | | | | | | | | | | | It is done as a part of porting to Zephyr. Since the implementation of atomic functions is done for all architectures use atomic_* instead of deprecated_atomic_*. Sometimes there was a compilation error "discards 'volatile' qualifier" due to dropping "volatile" in the argument of the functions, thus some pointers casts need to be made. It shouldn't cause any issues, because we are sure about generated asm (store operation will be performed). BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I98f590c323c3af52035e62825e8acfa358e0805a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2478949 Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* chip/stm32: Only use a mutex when not in interrupt contextTom Hughes2020-10-091-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mutexes shouldn't be used in interrupt context. An ASSERT was added in mutex_lock to verify this commit e6956209119d2b2c1f45401855019e3a0a2f7dd5. There are cases where bkpdata_write can be called from an interrupt context, such as this stack trace that occurs when adding entropy from RO on dartmonkey/icetower (stack captured with Segger J-Trace): > rollbackaddent 1234 panic_assert_fail panic_output.c:132 mutex_lock task.c:889 bkpdata_write bkpdata.c:35 bkpdata_write bkpdata.c:24 bkpdata_write_reset_flags bkpdata.c:86 chip_save_reset_flags system.c:366 system_reset system.c:366 panic_reboot panic_output.c:114 report_panic panic.c:339 exception_panic panic.c:350 Validation of the fix was checked with the "rollback_region1" unit test, which failed before the change and works after. BRANCH=none BUG=b:170147314 TEST=./test/run_device_tests.py -b dartmonkey -t rollback_region1 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ie5509ec024e94b48c786199ccbb81ce93fafe547 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2462545 Reviewed-by: Edward Hill <ecgh@chromium.org>
* core: rename atomic_clear to atomic_clear_bitsDawid Niedzwiecki2020-10-061-2/+2
| | | | | | | | | | | | | | | | | | Change the name of atomic_clear to atomic_clear_bits to make to name more clear - the function clears only selected bits, but the name may suggest that it clears the whole variable. It is done as a part of porting to Zephyr, where atomic_clear zeros the variable. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: I7b0b47959c6c54af40f61bca8d9baebaa0375970 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428943 Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32g4: Initial UCPD driver for type-c functionalityScott Collyer2020-09-294-0/+582
| | | | | | | | | | | | | | | | | | | | | The STM32G4 contains a UCPD block that includes similar functions as a TCPC. This CL contains an initial version of the driver required to use this function. This CL adds register block definitions and the implementation of tcpci driver functions required to support type-c operation. This CL does not include support for USB-PD functionality. BUG=b:167601672 BRANCH=None TEST=verfied type-c attaches properly on quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I3e7912f33efa716501896b1f96b4c6d67db0f573 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213840 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* honeybuns: Increase flash size to work with RO onlyScott Collyer2020-09-291-1/+6
| | | | | | | | | | | | | | | | | | | | | We don't have enough flash space on to do a full RO + RW image. This CL simply adjusts the flash size define from 128k to 256k and only the RO image is only being used for development and HW verification. Note also that at this stage there is no support for RO -> RW jump other than using EC console command, so RO is the only image being executed. BUG=b:167462264 BRANCH=None TEST=make -j BOARD=quiche is successful. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Iec062f9f3be966c0653cbdafe72f5a160351cf07 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213839 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-298-13/+15
| | | | | | | | | | | | | | | | We will move to an API compatible with Zephyr's API. See the bug for complete rationale and plan. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id611f663446abf00b24298a669f2ae47fef7f632 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427507 Tested-by: Dawid Niedźwiecki <dn@semihalf.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Bloonchipper: Reduce usart transport's response size to 0x100Bhanu Prakash Maiya2020-09-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Bloonchipper firmware uses usart_host_command.c to communicate with Zork's AP. On AMD SoC we found there is a 256 byte UART FIFO limitation with Designware's UART IP. Typically DMA should have solved this issue but looks like Picasso and Dali, UART DMA is not working at expected. This is causing timeout issues with EC responses > 256 bytes. This patch will limit the response size to 256 bytes which ensures that AP RX packets always stay within FIFO limits. Currently UART based host command transport is only used by FPMCU Dragonclaw STM32 design. BRANCH=none BUG=b:160208269 TEST=1. Run bloonchipper binary on Zork FPMCU devices. 2. Check PCO/DALI do not throw UART DMA overrun interrupt. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Change-Id: I0b99d25cf7d2dd163d05c35585064ad5e61a91ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428203 Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@googlers.com> Tested-by: Bhanu Prakash Maiya <bhanumaiya@googlers.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@googlers.com> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@googlers.com>
* stm32g4: Update dma channels for USARTScott Collyer2020-09-081-6/+6
| | | | | | | | | | | | | | | | This CL adjusts the DMA channel assignment for the USART that's used for EC console. BUG=b:148493929 BRANCH=None TEST=verfied ec console works on quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I87aecdbc16667adc87e15f0158b71cfa39c706c6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213941 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Specify correct ARM core and CPU flagsScott Collyer2020-08-311-1/+2
| | | | | | | | | | | | | | | | The only change required for build.mk is to specify the correct ARM core and machine instruction set. BUG=b:148493929 BRANCH=None TEST=verfied image builds successfully. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I267dfbe54de153c8687f5048fdcccf65ac15678f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195551 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Add flash support for stm32g4 chip familyScott Collyer2020-08-314-83/+91
| | | | | | | | | | | | | | | | | | | This CL adds support for flashing stm32g4. The L4 family has the same flash module and so that was used as basis for G4 driver. This CL renames the l4 flash driver to capture this commonality. In addition, the flash register definitions in G4 registers file was updated appropriately. Previously, this section matched F4 requirements. BUG=b:148493929 BRANCH=None TEST=verfied usb-ep fw update completes successfully Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I6cc818c6329524924534b0566bd9d24145c86c72 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195547 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org>
* stm32l4: Refactor to use page instead of bank notationScott Collyer2020-08-312-31/+77
| | | | | | | | | | | | | | | | | | The L4 and G4 family share the same flash peripheral block. Therefore, the G4 can share the L4 driver. This CL adds macros which more closely track the TRM description of the flash module, especially w.r.t pages. There is no functional change for the L4 driver. BUG=b:148493929 BRANCH=None TEST=make -j BOARD=stm32l476g-eval is successful Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ie2c16ef2b8fa0e35f5945fb124765039f8ea22c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2376388 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Fix build issue with i2c driverScott Collyer2020-08-292-2/+1
| | | | | | | | | | | | | | | This CL fixes 2 minor issues which with the i2c driver file. BUG=b:148493929 BRANCH=None TEST=verfied honeybuns builds correctly. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ide6aafd4e4296891579fa138ec0d3e54a4ed9c6d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2376828 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* usbc: remove PD_EVENT_SM in favor of task_wakeJett Rink2020-08-211-1/+1
| | | | | | | | | | | | | | | | We have used both methods of waking up the PD tasks to process the next state: PD_EVENT_SM and TASK_EVENT_WAKE. They effectively do the same thing and it is more straightforward to only have one way to wake the task up with the sole purpose of re-evaluating the current state. BRANCH=none BUG=none TEST=No regressions on GRL testing. Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I0fa79b82223e6b97eede4130480156949d79f365 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2363466 Reviewed-by: Edward Hill <ecgh@chromium.org>
* task: Change mutex_lock() assertEdward Hill2020-08-151-7/+3
| | | | | | | | | | | | | | | | | | | Instead of asserting that task_start() has not been called, just return without doing any locking. This avoids the need to fix every caller of mutex_lock() to check task_start_called(). BUG=b:164461158 BRANCH=none TEST=Esc+F3+Power enters recovery, does not assert. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ic157d7e7041185a67f257f0f5710fd02e45cd77f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2357496 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* COIL: change usage of sanityDaisuke Nojiri2020-08-141-1/+1
| | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "sanity" with inclusive alternatives. BUG=b:163885307 BRANCH=None TEST=make -j buildall TEST=grep -ir sanity Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I487a50999d506a0337f1d3fbe173f193e5e4098a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2353516 Reviewed-by: Sam Hurst <shurst@google.com>
* stm32g4: Add I2C supportScott Collyer2020-08-132-11/+472
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the i2c driver for stm32g4 chip family. The i2c block for stm32g4 is very similar to that of stm32l4 chip family. The g4 driver is mostly copied from the L4 version of the i2c driver. However, the driver only currently supports master mode. BUG=b:148493929 BRANCH=None TEST=run i2scan on EC console > i2cscan Scanning 0 usbc................. 0x18. 0x19. 0x1a. 0x1b. 0x1c. 0x1d. 0x1e. 0x1f. 0x20. 0x21. 0x22. 0x23. 0x24. 0x25. 0x26. 0x27........................... 0x42.............................. 0x60....................... Scanning 1 usb_mst. 0x08. 0x09. 0x0a. 0x0b. 0x0c. 0x0d. 0x0e. 0x0f. 0x10. 0x11. 0x12. 0x13. 0x14. 0x15. 0x16. 0x17... 0x1a........................... 0x35............ 0x41......... 0x4a. 0x4b...................... 0x61...................... Scanning 2 eeprom......................................... 0x30................................ 0x50....................................... Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Id8b7472e579bae17360a0122fe2b12a333139cfa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2161580 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Fix max clock freq and flash wait stateScott Collyer2020-08-131-5/+5
| | | | | | | | | | | | | | | | | | | | | The clock frequency macro added in previous CL was missing the '0'. This CL fixes that error and makes a minor change to how the flash wait state value is configured. Previously, setting of the wait state field was disabling instruction/data cache until it was restored in the next instruction. This results in swd debugger not remaining attached. BUG=b:148493929 BRANCH=None TEST=verified console is working and debugger remains attached after setting wait state to the correct value. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I65e3a22e36de0bbf14926e5687a995b7e5717e7f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340695 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-121-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. Add check for task_start_called() for NPCX flash_lock, I2C port_mutex, pwr_5v_ctl_mtx, STM32 bkpdata_write_mutex. This was submitted CL:2309057, reverted CL:2323704, submitted CL:2335738, reverted CL:2341706. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I0aadf29d073f0d3d798432099bd024a058332412 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2343450 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* ec: change usage of dummySam Hurst2020-08-0512-34/+34
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* stm32g4: Set uart frequency and enable clocks for stm32g4Scott Collyer2020-07-311-3/+3
| | | | | | | | | | | | | | | | This CL adds changes to enable clocks and configure the uart speed for stm32g4 chip family. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I5600ed64867192fe77fd85fc3dbc0a63f912d738 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195550 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Modify channel select to use DMAMUX for stm32g4Scott Collyer2020-07-311-2/+15
| | | | | | | | | | | | | | | | | | The STM32G4 family chips have similar DMA engine as some other STM32 families and therefore most of DMA code can simply be used as is. However, the STM32G4 does have a DMAMUX and so the correct peripheral request must be set. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I2694881f97558ea7b904a9b83ee20d9ec813c273 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195549 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* spi: Use different hooks for SPI enable/disableWai-Hong Tam2020-07-301-0/+9
| | | | | | | | | | | | | | | | | | | If CONFIG_CHIPSET_RESUME_INIT_HOOK is defined, move the SPI enable/disable to different hooks, i.e. * RESUME_INIT instead of RESUME * SUSPEND_COMPLETE instead SUSPEND The SPI interface has to be enable earlier than other hooks to receive a host sleep event. BRANCH=None BUG=b:148149387 TEST=make buildall -j Change-Id: Ic56a7b5ef20fb8258487d1d350fc5f8a55e33049 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324989 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* stm: rtc: Prevent locking a mutex in interrupt contextWai-Hong Tam2020-07-301-1/+9
| | | | | | | | | | | | | | | | | In the RTC interrupt, it calls host_set_single_event() directly, that eventually tries to lock a mutex. Trying to lock a mutex in the interrupt context should be forbidden. So move the call to a deferred function. BRANCH=None BUG=b:162434716 TEST=Build the board scarlet, which uses stm and enables RTC host command. Change-Id: I3f5ab85549a801f4f5d72cf5661a65c9f9d28e0c Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2327249 Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
* stm32g4: Add clock enable logic for HW timerScott Collyer2020-07-291-0/+11
| | | | | | | | | | | | | | | | This CL adds clock enable support for stm32g4 family. BUG=b:148493929 BRANCH=None TEST=verfied that via scope that led toggle happens at 1 second window when using one second hook call. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ie3d353ec40206e93cfac7b8738166ffee6c8442c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195548 Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Add gpio supportScott Collyer2020-07-291-0/+66
| | | | | | | | | | | | | | | | | This CL adds stm32g4 chip specific changes. Most of gpio code can be reused as is. This file enables clocks and IRQs for supported GPIO banks. This was based on F4 family as the reference. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I47d0b08675b53597b5a0e938d576682e63cc59e0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195546 Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Clock module driverScott Collyer2020-07-291-0/+277
| | | | | | | | | | | | | | | | | | | | This CL adds support to configure rcc module for stm32g4. The driver from the F4 family was used as a reference. Support for RTC was not ported as it's not being used for honeybuns. The function wait_for_ready() was moved to the common clock file for the F-family so it would not need to be replicated for G4 as well. BUG=148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I980c8889965a2e5da401ccd6291079a0bdfa8e4f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195545 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Modifications required for system.cScott Collyer2020-07-291-1/+15
| | | | | | | | | | | | | | | | | This CL updates stm32 specific system.c for the stm32g4 chip family. A comment was added to clarify what's required for enabling the backup domain. In addition, debug mode and detection of a warm boot. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I8b5063419ae6dc1be165b8bb3754703c1e728ae9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195544 Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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