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* Keyborg: implement matrix scanningVic (Chun-Ju) Yang2014-04-301-0/+23
| | | | | | | | | | | | | | This implements dual chip matrix scanning. Now the scan result is only dumped to debug output. BUG=None TEST=Put a finger on the panel and see its shape. BRANCH=None Change-Id: I015c901b42e24fe4a6249c12c37bc5bfcb308c9f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/196468 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: handle plug polarityVincent Palatin2014-04-302-10/+16
| | | | | | | | | | | | | | | | | | | | Use the plug polarity detected by the ADCs to do the PD communication on the right CCx line. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28339 TEST=make buildall on Firefly, plug Zinger connector in both direction and see it can control it either way. on Fruitpie, use CC1 or CC2 and see it can communicate on both. Change-Id: I81cb00f164cb8194fba73b383014e81c37d975e2 Reviewed-on: https://chromium-review.googlesource.com/197520 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* pd: update policy, timeout and board callbacksVincent Palatin2014-04-301-10/+1
| | | | | | | | | | | | | | | | | | | | | | | Slightly modify interfaces for better sink-only devices implementation (eg Firefly) update the host mode management and the voltage selection and add a hook for board checks. Simplify the reception timeout and fix other timeout detections. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall and use with the follow-up firefly board configuration CL. Change-Id: I0240295764c8605793dc80a2fc21357af1740744 Reviewed-on: https://chromium-review.googlesource.com/195585 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: pd: add config option to use SPI master for USB PD trasmitAlec Berg2014-04-293-16/+96
| | | | | | | | | | | | | | | | | | | | | | | Added config option CONFIG_USB_PD_TX_USES_SPI_MASTER which switches to use SPI master for PD transmit. The advantage of SPI master mode is at the end of the tranmission, we don't have to send any dummy 0 bits. When the option is set, the CPU_CLOCK must be set to 38.4MHz, so that the SPI master can generate the correct clock frequency. BUG=chrome-os-partner:28309 BRANCH=none TEST=Tested by connecting two fruitpies together across CC1. One fruitpie has been modified such that the MISO and MOSI lines are swapped and is running PD TX in SPI master mode with 38.4MHz clock, while the other is running PD TX in SPI slave mode. On EC console ran pd charger on one board and pd dev on other board. Verified that communication works with no errors. Ran for 10 minutes in each configuration. Change-Id: Ib24030d34d95d59f4ac6c2dae98bf7adda1ada01 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197215 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: fix GPIO EXTINT maskingVincent Palatin2014-04-263-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | The external interrupts above 15 are not used for GPIO IRQ handling, but for special purpose interrupts from internal peripherals (e.g. RTC, comparator, wake-up ...). When processing the GPIO interrupts, we should explicitly skip those interrupts, else if a GPIO interrupt happens first followed by another EXTINT, the loop in gpio_interrupt() will try to process it and do an out-of-bound read of the exti_events array. This will retrieve a garbage handler triggering a memory fault. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:28296 TEST=on Firefly, press the buttons to trigger GPIO interrupts while there are a bunch of comparator interrupt on EXTIN21 (due to on-going USB PD communication). I no longer see HardFaults. Change-Id: Id90fab30215b0f7f8060c19de63a7ca8418b7b3c Reviewed-on: https://chromium-review.googlesource.com/197019 Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* Keyborg: chip-to-chip SPI communicationVic (Chun-Ju) Yang2014-04-241-0/+6
| | | | | | | | | | | | | | | | | | This implements a simple SPI driver for the two chips to exchange packets. There are both sync interface and async interface. Sync interface is easier to use, and async interface frees the CPU while the DMA takes care of the communication. BUG=None TEST=Hello test passed BRANCH=None Change-Id: I9823bad5cae6d1fa8f3658d17af4b998d3735a3e Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195533 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add STM32TS60 supportVic (Chun-Ju) Yang2014-04-205-0/+90
| | | | | | | | | | | | | | | | This chip got small flash and RAM, so the common runtime is disabled. Now the code only boots and print something every second to check debug console and timer are good. BUG=None TEST=Boot and see console output TEST=make buildall BRANCH=None Change-Id: I01150e8250a404628d1a3b81e677ac4c29782d7f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/195382 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: USB Power Delivery physical layerVincent Palatin2014-04-123-0/+497
| | | | | | | | | | | | | | | | | Implementation of the physical layer for USB Power Delivery communication using the STM32 chip. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: I2a4adeef572b97a284bf52ab9d14d23246c56d18 Reviewed-on: https://chromium-review.googlesource.com/189867 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: add support for stateful CRC-32Vincent Palatin2014-03-293-0/+145
| | | | | | | | | | | | | | | | | | | | | | | add support for CRC-32, it's using the USB variant for the constants and bit ordering (same polynom as Ethernet). This code is using an (evil) "stateful" design to be compatible with the hardware CRC controller : you should NOT do concurrent accesses without external locking (but it's good enough and ligthweight for current usage) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run interoperability testing against other 3rd parties USB implementations. Change-Id: I1a07b2c4e2e71e15f9d257611652061bcfb0de9c Reviewed-on: https://chromium-review.googlesource.com/189865 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: new I2C driver for STM32F0xx familyVincent Palatin2014-03-273-3/+289
| | | | | | | | | | | | | | | | | | The STM32F0xx family has a new I2C peripheral, let's add a new driver for it. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=On FruitPie, read TSU6721 registers and read the smart battery information. Change-Id: Ic49832205957559b4b6b647948b03f650a27ab04 Reviewed-on: https://chromium-review.googlesource.com/191210 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: add more register definitionsVincent Palatin2014-03-231-4/+220
| | | | | | | | | | | | | | | | add detailed registers for DAC, COMP, RI and CRC. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=none Change-Id: Ib456d1fbc72c2f6c658ea96e5a3ab72035b33ed2 Reviewed-on: https://chromium-review.googlesource.com/189864 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add STM32F03x configurationVincent Palatin2014-03-222-0/+45
| | | | | | | | | | | | | | | | | | Add STM32F03x as part of the STM32F0 family. STM32F031 will be used for devices requiring low-end parts. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=along with the following CLs, run on STM32F051 Discovery with limited RAM and Flash to mimic STM32F031. Change-Id: Ie95303eaf00ce53fe7c8d2ac84c19a983aadbf0d Reviewed-on: https://chromium-review.googlesource.com/189404 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* make the common runtime optionalVincent Palatin2014-03-221-2/+5
| | | | | | | | | | | | | | | | | | | | | In order to achieve really tiny firmwares, make our runtime (tasks, hooks, muxed timers, GPIO abstraction ...) optional. Add 2 new build options for it : CONFIG_COMMON_RUNTIME and CONFIG_COMMON_GPIO which are enabled by default, and ensure all the source files are built according to the right configuration variable. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall build a minimal board with no runtime. Change-Id: Icb621cbe0a75b3a320cb53c3267d6e578cd3c32f Reviewed-on: https://chromium-review.googlesource.com/189403 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: implement ADC support for STM32F0xxVincent Palatin2014-03-202-5/+266
| | | | | | | | | | | | | | | | | | | | | | Replace the stubs by an actual implementation for ADC and Analog watchdog support on STM32F0xx chips. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=manually read ADC values on STM32F072B discovery. TEST=read all ADC values at once. TEST=Enable watchdog and check it fires when the voltage goes out of range. TEST=read ADC value(s) while watchdog is enabled. TEST=Disable watchdog and check it's actually disabled. Change-Id: Ie6fbd1aa95a3d76394fa47803e8cfc24bf5e4562 Reviewed-on: https://chromium-review.googlesource.com/190710 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* stm32: add analog GPIO configurationVincent Palatin2014-03-203-1/+12
| | | | | | | | | | | | | | | | | Allow to setup a GPIO pin in analog mode on STM32 chips. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run comparators with GPIOs in analog mode on STM32L151 and STM32F072. Change-Id: Ie11dd8711e39ab191c96478c6d8c7b7e0dfa7ea4 Reviewed-on: https://chromium-review.googlesource.com/189863 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add 32-bit timer supportstabilize-5656.BVincent Palatin2014-03-143-1/+172
| | | | | | | | | | | | | | | | | | | | | Some STM32 variants have a 32-bit timer in addition the bunch of 16-bit timers. Add the option to use the 32-bit timer as the system clock source to lower the overhead of the timer code compared to a pair of 16-bit timers. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run the EC on STM32F072 Discovery board with 32-bit TIM2 as the clock source. Change-Id: If55c4e23a3f68dd8f6ca32e93f3a27c1743c767b Reviewed-on: https://chromium-review.googlesource.com/189861 Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: remove the conflict I2C2/GPIO config in nyan/big.Louis Yung-Chieh Lo2014-03-131-3/+0
| | | | | | | | | | | | | | After Alex's CL 8a9817a, the i2c driver no longer hardcodes the I2C port pin (Ya!). Remove the conflict pin setting in board files. BRANCH=nyan,big BUG=chrome-os-partner:26620 TEST=build and run on nyan board. Everything looks good. Change-Id: Iee2c5f10f642da7ad00f503b6e615cb6aa472459 Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189245 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32: flush write buffer before start DMA transfer.Louis Yung-Chieh Lo2014-03-111-0/+3
| | | | | | | | | | | BUG=chrome-os-partner:22849 TEST=Tested on peach-pit FAFT. No "checksum invalid" from cpu_uart.txt BRANCH=pit,nyan Change-Id: I64f4b636943158fab48892020980f784ca551e4f Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178087 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add support for STM32F0xx familyVincent Palatin2014-03-1113-17/+607
| | | | | | | | | | | | | | | | | | Add support for the STM32F0xx family of devices using a Cortex-M0 core and slightly newer peripherals than F1xx family. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run EC console on STM32F072B Discovery board. and pass all available unit-tests on target. Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735 Reviewed-on: https://chromium-review.googlesource.com/188983 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* force the compiler to use a valid register allocation for irq handlersVincent Palatin2014-03-117-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* stm32l: supports fake-hibernateLouis Yung-Chieh Lo2014-03-062-0/+122
| | | | | | | | | | | | | | | | | | We don't have available GPIO pin for power button as the hibernate (stand-by) wake-up source. Also, we don't want to do board change. So, put the EC in a decent infinite loop to pretend the hibernate mode and wait for particular wake-up event. This should be fine because the AP is already down before EC hibernates. BUG=chrome-os-partner:25435 BRANCH=Nyan TEST=see comment #6 of issue for detailed test steps. Change-Id: I2cae131789f9ca5808b60d5f2495222ca9016e7c Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186061 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Combined i2c unwedge code into one common functionAlec Berg2014-03-062-250/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactored the i2c unwedge code to place it in the common directory so that any EC chip can use it. Added to the STM32F and LM4 boards, code to automatically detect and unwedge the i2c bus at the start of an i2c transaction. Note that STM32L already had this ability. To enable unwedging of the i2c port though, the gpio pins for SDA and SCL must be defined in the i2c_ports[] array in the board.c file. This allows the i2c module to bit bang the unwedging for the given port. If SDA and SCL are not defined for the port, then the unwedge code will not run. BUG=chrome-os-partner:26315, chrome-os-partner:23802 BRANCH=none TEST=Manual testing on machines with different EC chips. Testing made extensive use of https://chromium-review.googlesource.com/66389 in order to force wedging of the i2c bus so that we can attempt to unwedge it. Note that you can easily test if the bus is wedged by running i2cscan. On pit and spring: On pit, after each of the following, I verified that the bus was automatically unwedged. On spring, the unwedge only runs at reboot, so, for the non-reboot wedge commands, I manually ran console command unwedge, and verified that the bus became unwedged. (1) Bit bang a transaction but only read part of the response. Command to wedge: i2cwedge 0x90 0 2 2 (2) Bit bang a transaction to do a "write" and stop while the other side is acking. Command to wedge: i2cwedge 0x90 0 1 (3) Same as (1) but do a reboot instead of returning and see that the unwedge works at init time w/ no cancelled transactions. Command to wedge: i2cwedge 0x90 0 6 2 (4) Same as (2) but do a reboot instead of returning and see that the unwedge works at init time w/ no cancelled transactions. Command to wedge: i2cwedge 0x90 0 5 On glimmer: Added code to call i2c_unwedge in accel_init(). Then tested unwedging the accelerometer with the following. One extra difficulty testing this with the accelerometer is that sometimes the bit you stop on is high, which means it won't be wedged at all, the next start transaction will reset the bus. So, sometimes running i2cwedge won't wedge the bus and sometimes it will depending on the acceleration data. (1) Big bang transaction to do a "read" of accelerometer and stop partway: i2cwedge 0x1c 0x0f 2 2 i2cscan to make sure bus is actually wedged i2cunwedge i2cscan to make sure bus is now unwedged. (2) Bit bang transaction to do a "read" and stop partway, then reboot: i2cwedge 0x1c 0x0f 6 2. i2cscan to verify that the bus is working after the reboot. Change-Id: Ie3328e843ffb40f5001c96626fea131c0f9ad9b1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188422 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Convert vboot hash calculation from task to deferred functionRandall Spangler2014-01-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vboot hash calculation takes ~350 ms during EC boot. Since the hash task is higher priority than the hook task, this starves all the hooks during boot. We could, in theory, fix that simply by swapping the priority of the hook and hash tasks. But then watchdog detection (in the hook task) wouldn't detect hangs in the hash task. A better fix (implemented here) is to convert the hashing operation to a series of deferred function calls. This gets rid of the hash task entirely, and allows all pending hooks and other deferred function calls to take place between each chunk of hashing. On STM32-based boards, we need to bump up the hook task stack size, since hashing is called from several layers deep in the hook task instead of at the top of its own task, but this is still a net win of several hundred bytes of SRAM. BUG=chrome-os-partner:24892 BRANCH=rambi TEST=Boot EC; look for "hash start" and "hash done" debug output. 'taskinfo' shows at least 32 bytes of unused stack for HOOKS task. 'hash ro' runs properly from EC console. Change-Id: I9e580dc10fc0bc8e44896d84451218ef67578bbe Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181954
* Move ADC console command to commonVic (Chun-Ju) Yang2013-12-202-36/+0
| | | | | | | | | | | | | | | | | | | We have three duplicated ADC read console command, and we are about to have the fourth. Let's consolidate them to a single implementation in common/. Note that we have to add a simple implementation of adc_read_all_channels() for LM4. BUG=chrome-os-partner:18343 TEST=Build all boards TEST=Read single channel TEST=Read all channels BRANCH=None Change-Id: I079c0b33ab6b81a188f309cf99875eb02e9d78a4 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180831
* cleanup: Remove checkpatch warningsRandall Spangler2013-12-194-17/+16
| | | | | | | | | | | | | | | | This make minor syntactic changes and renames some camel-cased symbols to keep checkpatch from complaining. The goal is to reduce the temptation to use 'repo upload --no-verify'. This is a big furball of find/replace, but no functional changes. BUG=chromium:322144 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180495
* Rename mixed-case config constantsRandall Spangler2013-12-168-31/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | This renames constants used in compiler conditionals to uppercase. BOARD_foo CHIP_foo CHIP_FAMILY_foo CHIP_VARIANT_foo CORE_foo Mixed-case constants are still defined by the makefile, but are now no longer used. I will make one more pass in a week or so to catch any that are part of someone else's CL, since otherwise this change might silently merge correctly but result in incorrect compilation. Then I will remove defining the mixed-case constants. BUG=chromium:322144 BRANCH=none TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no results (similarly for CHIP, CORE, etc.) Change-Id: I6418412e9f7ec604a35c2d426d12475dd83e7076 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179206 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* gpio: Make GPIO_INT_BOTH explicitly RISING|FALLINGRandall Spangler2013-11-232-4/+4
| | | | | | | | | | | | | | | | | | | | | | | For historical reasons on LM4, we defined GPIO_INT_F_BOTH separately from GPIO_INT_F_RISING and GPIO_INT_F_FALLING. This means that the code has weird checks like BOTH || (RISING && FALLING), which have propagated in error-prone ways across the other chips. Instead, explcitly define BOTH to be RISING|FALLING. Ideally, we would have called it GPIO_INT_EDGE to match GPIO_INT_LEVEL, but changing that now would be a big find-replace. Which might still be a good idea, but that is best done in its own CL. BUG=chrome-os-partner:24204 BRANCH=none TEST=build and boot pit, spring, and link; that covers STM32F, STM32L, and LM4. Change-Id: I23ba05a3f41bb14b09af61dc52a178f710f5c1bb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177643 Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* mec1322: initial commitVic (Chun-Ju) Yang2013-11-211-0/+2
| | | | | | | | | | | | | | | | | | | | This is the initial commit of mec1322 support. This includes: - Basic GPIO driver. Interrupt not supported yet. - Microsecond timer - UART driver The script to pack the firmware binary will be checked in in following-up CL. BUG=chrome-os-partner:24107 TEST=Build and boot on eval board BRANCH=None Change-Id: I9013c908049d1f740f84bb56abca51b779f39eef Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175716 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f: Disable UART receive DMARandall Spangler2013-11-193-2/+11
| | | | | | | | | | | | | | | | | | Not sure why, but it doesn't seem to work consistently on my Spring. Transmit works fine, but on some boots receive doesn't seem to pick up received characters. Rather than churning Spring to fix this, just disable receive DMA - which doesn't benefit Spring much anyway, because it never downclocks its core to 1 MHz. BUG=chrome-os-partner:24141 BRANCH=none TEST=Boot Spring; typing into console works. After 'apshutdown', typing still works (including arrow keys). Repeat 20 times. Repeat on Pit. Change-Id: I5d9875b583c8e2a38b9070c4dfa31fd5a982a144 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177352 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: Flush UART buffer before changing EC core clock speedRandall Spangler2013-11-191-1/+7
| | | | | | | | | | | | | | | | | Otherwise UART output gets garbled because there's a delay between changing core clock and the UART divider. Fortunately, the glitch is cosmetic and doesn't affect proper EC operation. BUG=chrome-os-partner:23982 BRANCH=none TEST=power on, power off on pit or nyan --> no UART glitch Change-Id: I32bef119b850a340fc616b83a4b088b20f17267f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177087 Reviewed-by: Yung-chieh Lo <yjlou@chromium.org> Tested-by: Yung-chieh Lo <yjlou@chromium.org> Commit-Queue: Yung-chieh Lo <yjlou@chromium.org>
* stm32: Don't use a stack buffer for i2c_read_string()Randall Spangler2013-11-072-17/+15
| | | | | | | | | | | | | | | | | | We read a counted string (byte 0 = count, bytes 1 - count = chars) and convert it to a null-terminated string. Since both have a 1-byte overhead, we can use the destination buffer instead of using a stack-based buffer. BUG=chrome-os-partner:23928 BRANCH=none (pit is affected, but battery console command isn't used on end user systems) TEST=battery command shows correct strings (SDI / 4302D40 / LiP), and doesn't stack overflow. Change-Id: Ic0f111cde2d57b41d6ce9287e0c771acc09a8869 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176116 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Move core-specific toolchain configuration to core/ directoryVincent Palatin2013-11-071-0/+3
| | | | | | | | | | | | | | | | This is preparatory work to introduce a second core architecture. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=./util/make_all.sh Change-Id: Icae8a7e475a4ba2a13f0d8f95629e8498a5a61da Reviewed-on: https://chromium-review.googlesource.com/175419 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* cortex-m: ensure we use the right subset of the instruction setVincent Palatin2013-11-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Cortex-M3 and Cortex-M4 are not using exactly the same instruction set. Cortex-M3 is using ARMv7-M ISA which is a subset of the ARMv7E-M used by the Cortex-M4 core (even though the delta is small). Let's restrict each core to the right subset of instruction by pushing the -mcpu/-march configuration in the chip specific area. Note: GCC 4.8 is now using the full ARMv7E-M instruction set and will emit "undefined instruction" on Cortex-M3 without this patch. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chromium:314194 TEST=build *and* run on Spring and Link. Change-Id: I2f9b87fec689e8d1097809cab437a2bd32dfa194 Reviewed-on: https://chromium-review.googlesource.com/175487 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Still more TODO commentsRandall Spangler2013-11-022-12/+12
| | | | | | | | | | | | | More of same. Comment changes only; no code changes. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: I8c42ed7d332cd9d461067e1aeac670855106cbcd Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175405 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Even more TODO commentsRandall Spangler2013-11-013-4/+14
| | | | | | | | | | | | | | | Update comments with more info, or remove if no longer applicable. No code changes. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: I5b56eeb500bc0f00e84e91ef99684f4b1b310972 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175418 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Update more TODO commentsRandall Spangler2013-11-013-10/+18
| | | | | | | | | | | | | | | Add bug links, reword, or remove as applicable. No code changes, just comments. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: Id55dd530c10091d7ab9d0f942f750168fca793b4 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175326 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Improve / remove more TODO commentsRandall Spangler2013-11-012-10/+7
| | | | | | | | | | | | | Add bug references. Remove one assert that can no longer be triggered. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I3f4d2e4f2f3343a8d0531cb0715d151eaa4d0b50 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175293 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Rename pwm_data.h to pwm_chip.hBill Richardson2013-10-283-2/+2
| | | | | | | | | | | | | | To conform to our mutating naming conventions, let's rename the chip-specific PWM header file to have the string "_chip" in it. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: I6584be8e54fd24c8638559817e150c707bc0edb5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174884 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: comments in adc modulesRandall Spangler2013-10-252-5/+10
| | | | | | | | | | | | No code changes, other than renaming a couple of static functions. BUG=none BRANCH=none TEST=build falco Change-Id: I29b835d273aa1aba66d9d40536eae2eb12207f66 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174530
* stm32l: fix ADC all channels conversionVincent Palatin2013-10-251-0/+1
| | | | | | | | | | | | | | | | | | | Reset the DMA status after the end of the conversions, else we will exit too early at the next call of the function and the values before they are actually transfered. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run "adc" command several times and always see proper value for each ADC. Change-Id: I7ad335fffa2da34a4b715e9f0c9927bf06baef8f Reviewed-on: https://chromium-review.googlesource.com/174397 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* cleanup: comments in i2c modulesRandall Spangler2013-10-252-11/+9
| | | | | | | | | | | | | No code changes; just update comments with bug links BUG=none BRANCH=none TEST=build all platforms Change-Id: I8b845f9c43315b7db5a746a16c6618c3ee96979d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174614 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: rename I2C_PORT_HOST to I2C_PORT_MASTERRandall Spangler2013-10-252-12/+12
| | | | | | | | | | | | | | | | | Previously, it was really confusing whether I2C_PORT_HOST meant the port where the EC was the master, or the port used to talk to the AP. No functional changes, just a global find/replace and some tidying of unused comments. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms; pass unit tests Change-Id: Ia591ba4577d3399729556e0234ba0db3a0e3c5ea Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174546 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Rename and move header filesRandall Spangler2013-10-233-2/+2
| | | | | | | | | | | | | | Device-specific headers belong in driver/ or chip/. The include/ directory should be for common interfaces. Code should not normally need to include driver-specific headers. If it does, it should use the full relative path from the EC project root (for example, drivers/charger/bq24715.h). Change-Id: Id23db37a431e2d802a74ec601db6f69b613352ba Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173746 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: Remove obsolete comment in STM32 GPIO moduleRandall Spangler2013-10-221-1/+0
| | | | | | | | | | | | | | USB A-A cable works fine downloading firmware on pit now, so this comment no longer applies. BUG=none BRANCH=none TEST=build pit Change-Id: I4f07108357ffcab590fd95ffb50955f60698a39e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174047 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cleanup: update comments with existing bug numbersRandall Spangler2013-10-221-1/+4
| | | | | | | | | | | | | | | Some of the comments no longer apply. Others needed more info. No code changes; just comment changes. BUG=none BRANCH=none TEST=build all platforms Change-Id: I1d52aa9a98427a78c9d9a8cf44934fb04c3c00c8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/174084 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* lm4: Use low speed clock in deep sleep.Alec Berg2013-10-211-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Changed the low power idle task to use the low speed clock in deep sleep. The low power idle task is currently only enabled for Peppy, Slippy, and Falco. This change decreases power consumption when the AP is not running. Note that the low speed clock is slow enough that the JTAG cannot be used and the EC console UART cannot be used. To work around that, this commit detects when the JTAG is in use and when the EC console is in use, and will not use the low speed clock if either is in use. The JTAG in use never clears after being set and the console in use clears after a fixed timeout period. BUG=None BRANCH=None TEST=Passes all unit tests. Tested that the EC console works when in deep sleep. Tested that it is possible to run flash_ec when in deep sleep and using the low speed clock. Change-Id: Ia65997eb8e607a5df9b2c7d68e4826bfb1e0194c Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173326 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* i2c: Add common i2cxfer console commandDuncan Laurie2013-10-212-179/+0
| | | | | | | | | | | | | | | | | This console command is useful during bringup to interrogate devices on the EC I2C interfaces. Ported from STM32 into the common file. This command now takes an additional argument for the port to be used. BUG=chrome-os-partner:23449 BRANCH=samus TEST=emerge-samus chromeos-ec, tested on samus Change-Id: I8308fbc2f34e369a20051dca9c5d43872f239777 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173837 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: add stm32l100 variantVincent Palatin2013-10-192-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | stm32l100 is mostly identical to stm32l151, excepted that the RAM is smaller (10kB instead of 16kB for the RB SKU), the EEPROM is smaller, there is no touch capability (but we are not using those 2 features). So, in the new stm32l100 variant configuration, we adjust the memory size to 10kB and keep the regular UART RX buffer size (512 B) rather than putting a 2kB buffer to fit in the new constraints. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run on discovery board reworked with stm32l100rct6 and Nyan reworked with stm32l100rbt6. Change-Id: Ifd78f59a102b3079f0f794af8058211dc724153d Reviewed-on: https://chromium-review.googlesource.com/173632 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: David James <davidjames@chromium.org>
* lm4: Add a low power idle task.stabilize-4825.BAlec Berg2013-10-153-46/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First implementation of a low power idle task for the LM4 chip. The low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a board.h file. This commit turns it on for Peppy, Slippy, and Falco only because those are the only boards tested. When using the low power idle task, the chip goes in to deep sleep when it can. Deep sleep disables clocks to most peripherals and puts the onboard flash and RAM into a low power mode. The chip is woken out of deep sleep using the RTC in the hibernate module. Increased the idle task stack size to handle more involved idle task. In board.c, the array of GPIO info can be used to select which GPIO points can wake up the EC from deep sleep. Currenlty selected are the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5. Additionally the port with the KB scan row GPIO point is also enabled to wake up the EC from deep sleep. Signed-off-by: Alec Berg <alecaberg@chromium.org> BUG=None BRANCH=none TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no noticeable side affects. Verified that the power consumed by the EC is lower when in S3, S5 and G3 by scoping the sense resistor powering the chip. Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726 Reviewed-on: https://chromium-review.googlesource.com/172183 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* rambi: Control LEDs using PWMRandall Spangler2013-10-081-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Rambi has a pair of LEDs which are attached to the PWM fan controller. Add support for them. Also add a generic 'pwmduty' command which can be used to get/set the duty cycle for any PWM channel. Also fix rounding errors in pwm module, so that set/get duty doesn't keep rounding down. BUG=chrome-os-partner:22895 BRANCH=none TEST=Boot rambi. LEDs are off. pwmduty -> both are 0% pwmduty 0 10 -> green LED on dimly pwmduty 1 10 -> red LED on dimly pwmduty 0 99 -> green LED on brightly pwmduty 1 100 -> red LED on brightly pwmduty 1 0 -> red LED off pwmduty 1 -1 -> red LED turns back on because fan controller is disabled pwmduty -> channel 0 at 99%, channel 1 disabled Build all platforms. Pass all unit tests. Change-Id: Ib0a6289a757554e696a9a0153a85bdc34e2ee2ae Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172094
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