summaryrefslogtreecommitdiff
path: root/chip/stm32l
Commit message (Collapse)AuthorAgeFilesLines
* stm32l: basic GPIO supportVincent Palatin2012-02-034-5/+90
| | | | | | | | | | | | No interrupt support yet. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on Discovery EC console, using "gpioget" and "gpioset" commands check we can switch the LED and read the button state. Change-Id: I01294643d3df070a535dab5a6be02c296487fca5
* correct typo for STM32L GPIO bit set/reset register (BSSR --> BSRR))David Hendricks2012-02-021-1/+1
| | | | | | | | | Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=none TEST=none Change-Id: I2f452e4f842ac3b67157f94c5e533b53d0d8baec
* stm32l: update clock settingsVincent Palatin2012-02-022-7/+27
| | | | | | | | | | | | | | | | Add a final wait to ensure the clock is ready before returning. Setup the Flash according to the manual recommendations. The low-speed oscillator and RTC are now done in the system module with other RTC inits. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run the EC firmware on the Discovery and manually exercise various path through the console. Change-Id: I4e6149b6fd55c8fc72dbdf6bfc4a10665e0246bd
* stm32l: implement reset cause and scratchpadVincent Palatin2012-02-021-3/+51
| | | | | | | | | | | | | | Allow to get proper reset reason. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=On the discovery board, try the reset button, the "reboot" command and a blocking wait, and see the proper reset reason displayed. Initialize the scratchpad register with "setscratchpad" command and check we can read it back after reboot. Change-Id: I1fe1eec4987f7c9816454de4fd3b4addda4ad05a
* stm32l: add watchdog supportVincent Palatin2012-02-023-0/+85
| | | | | | | | | | | | | | | | | | Use the Independant WatchDog. The Window WatchDog would provide a nice early warning interrupt before actually rebooting but the max period (128 ms) is probably too short for our purpose. The full GPIO support and the reboot cause detection will be implemented in later steps. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on Discovery board, do blocking waits of 500ms and 1500ms, and check the latter reboots the platform and the former does not. Change-Id: I26e4d8b26b733269b7811cc3b3a09daf98ea364a
* stm32l: add timer supportVincent Palatin2012-02-011-3/+110
| | | | | | | | | | | | | | | As the STM32L doesn't have any 32-bit timer, we use 2 chained 16-bit counters to emulate a 32-bit one : * TIM2 is the MSB half-word (Slave timer) * TIM3 is the LSB half-word (Master time) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run timer_calib and timer_dos on the Discovery board, and check waitms and gettime console functions against wall clock. Change-Id: I8917207384d967fd87321797856e3d58b237f837
* stm32l: ensure we transmit as soon as characters are availableVincent Palatin2012-02-011-0/+1
| | | | | | | | | | | | | Force starting the transmission immediatly when ordered by the UART buffering layer. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC console on Discovery and measure the timestamp of each characters on the serial port. Change-Id: I036a3fa0a60baa27de4ba0ceb386841a429535ac
* stm32l: avoid spurious USART interruptsVincent Palatin2012-02-011-3/+20
| | | | | | | | | | | | | | The TX empty interrupt needs an actual write to DR to be cleared. So, we de-activate it before filling the TX buffer to ensure the interrupt won't fire after the last write. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC console along with a lower priority task on Discovery board, and check the task is scheduled as expected. Change-Id: I56c33c6dd7ccfd238fd9d5910780d12945467010
* stm32l: add UART driverVincent Palatin2012-01-312-5/+61
| | | | | | | | | | | | simple UART driver to get the serial console on the USART3. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run on Discovery board and check we get the first message on the UART and the console is echoing the characters. Change-Id: Id85999a5ddbd75804e9317a1b8c2fd4afb89eb38
* stm32l: initialize clocksVincent Palatin2012-01-301-0/+40
| | | | | | | | | | | | | Run from internal clock at 16Mhz, but enable PLL to get a better precision. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run on discovery board and check software is still alive after clock initialization. Change-Id: I8425482825015adf96c30e67a9320d0df2f4f2b7
* Add register definitions for STM32L SoCVincent Palatin2012-01-301-0/+237
| | | | | | | | | | | | Define IRQs and register addresses for basic peripherals to do STM32L bringup. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=mostly untested, there should be typos over there... Change-Id: Ib6d90436e25be74f724112619cdae7acccfaf085
* add the skeleton for STM32L chip and discovery boardVincent Palatin2012-01-266-0/+238
All hardware drivers code is stubbed excepted a few configuration settings. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=discovery Change-Id: Ic9e88a0f51ab626679c8aeb6192272e66a3f79b8
View Lorry Controller Status