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* system: fix system_get_scratchpad APIYuval Peress2021-08-209-29/+29
| | | | | | | | | | | | | | | The current API for system_get_scratchpad mixes the status and the value being read. Update the signature to allow both. BRANCH=none BUG=b:195481980 TEST=make testall && zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I3a5f5ad523d507c53a5d474806f58afafb82e70c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074828 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* mchp: Update RPM-PWM registers and configurationmartin yan2021-08-193-12/+23
| | | | | | | | | | | | | | | Update RPM-PWM block's registers and configuration as POR, RPM based Fan Control Algorithm via RPM-PWM hardware block is not supported or validated in previous mchp projects. BUG=none BRANCH=none TEST=Tested on ADL RVP and MCHP1727 MECC system via UART console Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Ibe15dfbec4f2c2d4558d27c8b101345ad81a09f3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3100925 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip/mt_scp: restore fmeter valueTinghan Shen2021-08-191-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fmeter is used to measure the clock speed on SoC. SCP uses the fmeter with different config compared to kernel side clock driver. Restore the fmeter value to prevent wrong fmeter result for clock driver. BUG=b:184793035 TEST=check fmeter result by following commands echo 0 > /proc/sys/kernel/printk clkdbg() { echo $@ > /proc/clkdbg; cat /proc/clkdbg; } clkdbg set_parent vdec_sel mainpll_d4 clkdbg set_parent venc_sel univpll_d4 clkdbg fmeter WAS: 64: hf_fvenc_ck : 312000 65: hf_fvdec_ck : 273000 IS: 64: hf_fvenc_ck : 624000 65: hf_fvdec_ck : 546000 Change-Id: If4d93b9b4e05258d0ad5f96953a99fd74acb6070 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063107 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* TCPM: Rename enum tcpm_transmit_typeAbe Levkoy2021-08-182-8/+8
| | | | | | | | | | | | | | | Rename tcpm_transmit_type to tcpm_sop_type to reflect that it can be used for Rx as well. Describe it in comments. This prepares to consolidate enum pd_msg_type into this enum. BUG=b:155476419 TEST=make buildall BRANCH=none Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: Ife97d4ad51c48f2e832b94e007954919e236a309 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104290 Reviewed-by: Keith Short <keithshort@chromium.org>
* usb_hid_keyboard: fix incorrect sleep/lock key positionTing Shen2021-08-171-1/+2
| | | | | | | | | | | | | | | | | The position of SLEEP_KEY_MASK bit is not in its intended position because TK_* enum is 1-indexed. Fix this bug by shift the mask by 1. BUG=b:196934919 TEST=evtest BRANCH=trogdor Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I900636f032786510f7870948d1856d0bc4374800 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097478 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* chip/mt_scp: add define to support wait decode interrupt in scpYunfei Dong2021-08-121-0/+1
| | | | | | | | | | | | | | | Add define to support irq in scp: VDEC_CAP_IRQ_IN_SCP BIT(16). BRANCH=none BUG=b:184793035 TEST=make BOARD=cherry_scp Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Change-Id: I7d4583f7c4bce07c6fb4f22bd9152edb23fe9e05 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3054225 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
* chip/mt_scp: move video capability to chip specificTzung-Bi Shih2021-08-097-19/+75
| | | | | | | | | | | BRANCH=none BUG=b:185977882 TEST=make BOARD=asurada_scp -j && make BOARD=cherry_scp -j Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Id5eaa5ddc0e21c9b33a1a4197393de6c6ef331e6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3080541
* stm32/usb_hid_keyboard; implement new top row keysTing Shen2021-08-091-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the hid usage mapping from drivers/hid/hid-input.c: Page 0xB, Usage 0x2F -> KEY_MICMUTE Page 0xC, Usage 0x7C -> KEY_KBDILLUMTOGGLE BUG=b:194460146 TEST=Map the new keys to F1/F2 on homestar, and verify 1) kernal can get the expected key code. Event: -------------- SYN_REPORT ------------ Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value b002f Event: type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1 Event: -------------- SYN_REPORT ------------ Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value b002f Event: type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 0 Event: -------------- SYN_REPORT ------------ Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value c007c Event: type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), value 1 Event: -------------- SYN_REPORT ------------ Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value c007c Event: type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), value 0 2) `cat /sys/class/input/*/device/function_row_physmap` BRANCH=trogdor Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ibf342b881ee428598adaeb73a63bf242cd220004 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3073440 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* mchp: Optimize spi_flash_read() APImartin yan2021-08-061-0/+12
| | | | | | | | | | | | | | | | | | Optimize SPI flash read timing, MEC172x QMSPI controller controls CS# by hardware, it will add several system clock cycles delay between CS deassertion to CS assertion at the start of the next transaction, this guarantees SPI back to back transactions, so 1ms delay can be removed to optimze timing. BUG=none BRANCH=none TEST=Tested on ADL RVP and MCHP1727 MECC system via FAFT ECBootTime job save 720ms as EC performs 180KB RW code's SHA256 hash computation Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: I5cf9c668efb1cd008b91cdd8aa09f7351c017af0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074767 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: chip/lm4: Update terminologyCaveh Jalali2021-08-043-18/+21
| | | | | | | | | | | BRANCH=none BUG=b:163885307 TEST=compare_build.sh matches Change-Id: Ifdf9d33f9315e11c0c31a62b08864790b2fcaa5a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069988 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32/usb_hid_keyboard: fix feature report data sizeTing Shen2021-08-041-1/+2
| | | | | | | | | | | | | | | | | | | | The usb hid driver always send 60 bytes feature report to the host, this causes host side unhappy because the received data is larger than expected. Fix this bug by sending what we actually declared. BUG=b:195264416 TEST=# cat /sys/class/input/*/device/function_row_physmap C0224 C0227 C0232 C029F 70046 C0070 C006F C00E2 C00EA C00E9 BRANCH=trogdor Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I536e4518a76606a05c006d459d6ffbb61858c2d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066973 Reviewed-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* COIL: host: Update SPI terminologyCaveh Jalali2021-08-043-12/+12
| | | | | | | | | | | | BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: I37dd5c596bf758d4bd6d39f643ff731ff4a567ea Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069987 Reviewed-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Harry Cutts <hcutts@chromium.org>
* COIL: Change host interface option to CONFIG_HOSTCMD_SHIKeith Short2021-08-035-5/+5
| | | | | | | | | | | | | | Update SPI host interface config option for inclusive language. BUG=b:163885307 BRANCH=none TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I808d5960fa3e746626465bedc626a95e0f0aaa3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066271 Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* COIL: npcx: Update I2C terminologyCaveh Jalali2021-08-022-47/+57
| | | | | | | | | | | BRANCH=none BUG=b:163885307 TEST=compare_build.sh matches Change-Id: I50d4263e93945ec0f3fd2d655fd173aa8a666d8f Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060261 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* npcx: Make interrupt handler staticCaveh Jalali2021-08-021-1/+1
| | | | | | | | | | | | BRANCH=none BUG=none TEST=compare_build.sh matches Change-Id: Idd8bab55d02bafdbab6b0e136326ef47a464dc4c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060259 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: CH Lin <chlin56@nuvoton.com>
* pylintrc: Copy Chromium OS platform2's configCraig Hesling2021-08-025-0/+20
| | | | | | | | | | | | | | | | | | | | This requests that cros lint (and repo upload hook) use the new Chromium OS 4 space indent policy. Since legacy python scripts still use 2 space, I added pylint ignore statements to the individual files to disable indentation checking. Note: There are still valid pylint errors in some of these legacy scripts. BRANCH=none BUG=none TEST=cros lint util/*.py Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I439f5a87bc50f1f43a4996e574bbc0626922a88e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3064761 Reviewed-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* COIL: chip/it83xx: Rename SPI IRQ configCaveh Jalali2021-08-025-10/+10
| | | | | | | | | | | | | | | This renames the ITE chip specific SPI IRQ config from IT83XX_IRQ_SPI_SLAVE to IT83XX_IRQ_SPI_PERIPHERAL. BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: Ib7a7674e6cf4f0bf81ee47b5f60225f77236f578 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061913 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* COIL: chip/it83xx: Rename SPI MAX_FREQ configCaveh Jalali2021-08-023-7/+16
| | | | | | | | | | | | | | | | This renames the ITE chip specific SPI speed configuration from IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE to IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE. BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: If2fcb086a8c35cf43ce15dc0963f3febbaa25f45 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061912 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* COIL: chip/it83xx: Update SPI terminologyCaveh Jalali2021-08-023-39/+39
| | | | | | | | | | | | BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: I6f5ac12ff64fe870709dc91bca71e0901bed3420 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061911 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* COIL: npcx: Update SHI terminologyCaveh Jalali2021-08-011-5/+5
| | | | | | | | | | | | BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: I045ae5f148fe6233abf921d99f381b2cce6966ad Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060260 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx: i2c: don't check bus busy if transaction is ongoing.Dino Li2021-07-301-4/+9
| | | | | | | | | | | | | | | | | | | | | This CL fixes that i2c driver will prompt "I2C chx reset cause 1" issue when one i2c transaction is separated into at least three i2c_xfer and I2C_XFER_START flag is set at least two times. eg. - i2c_xfer with I2C_XFER_START flag - i2c_xfer with I2C_XFER_START flag <= this will cause reset - xxx - i2c_xfer with I2C_XFER_STOP flag BRANCH=none BUG=none TEST=no i2c reset on Asurada, Drawcia, and ADL-RVP. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I97161db0bb0c54de3ad55d82512a6a188036270f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058724 Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* npcx: Add alternate function option for PS2_2 & PS2_3Wealian Liao2021-07-286-6/+34
| | | | | | | | | | | | | | | | | | | | | NPCX alternate switch function uses the GPIO number to select which register should be set. Currently, we have a scenario to enable CONFIG_PS2 & use ADC5(GPIO37) or ADC6(GPIO34) with NPCX9. The CONFIG_PS2 condition hides the alternate table for ADC5/6. It makes GPIO37 & GPIO34 are both set to PS2 function. This CL adds NPCX_PS2_MODULE_2 & NPCX_PS2_MODULE_3 options to assign PS2 function for alternate pin explicitly. BUG=none BRANCH=none TEST=make buildall TEST=Enable CONFIG_PS2 & check ADC5/6 functionality. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: Id02fb8ecfd488db133351119be84c357dc18da15 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058151 Reviewed-by: caveh jalali <caveh@chromium.org>
* chip/mt_scp: move video encode/decode IRQ to group 8Tinghan Shen2021-07-231-6/+6
| | | | | | | | | | | | | | | | | The IRQ triggering frequency of video encode/decode IRQ is propotional to frame rate. Assign these IRQs with group 8 to prevent blocking IPI IRQ handler (group 7). BRANCH=none BUG=b:189300514 TEST=make BOARD=cherry_scp Change-Id: Iab7147fbecc02217656bef1493574461ad54cb29 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3010781 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
* chip/mt_scp: fix 8195 IRQ default polarityTinghan Shen2021-07-233-3/+6
| | | | | | | | | | | | BRANCH=none BUG=b:189300514 TEST=video_decode_accelerator_tests test-25fps.h264 Change-Id: Ia6e777fe7a349586c676b6991643676019598d7a Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3038014 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* it83xx: pwm: fix wrong index of pwm_channelsDino Li2021-07-211-3/+3
| | | | | | | | | | | | | BRANCH=none BUG=b:194047863 TEST=On spherion, no keyboard backlight blinking. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I847291268720bf12ca98b3e38e29a556ec038cd0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3043075 Tested-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: change stm32l431 flash layoutBossen WU2021-07-202-1/+54
| | | | | | | | | | | | | | | Due to increase of RW size, stm32l431 flash layout were change to RO: 124KB, PSTATE: 2KB, RW:130KB BRANCH=kukui BUG=b:188117811 TEST=make BOARD=munna; make buidall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I8cf2d2dbdc8a2ae5e95d1d54c6672796eb02fc02 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3037292 Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* mchp: Correct integrated SPI flash pins' configurationmartin yan2021-07-141-2/+2
| | | | | | | | | | | | | | | | | | | Corrected MEC1727 integrated SPI flash CS# (GPIO116) and CLK (GPIO117) alternative function as 1 (Internal SPI functionality) from 2 (General purpose SPI functionality). BUG=none BRANCH=none TEST=Tested on ADL RVP via EC UART console > sysjump RW: able to switch to RW from RO > sysjump RO: able to switch to RO from RW Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: I870925183e670022dc023812265a7ef496b5f255 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3021101 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* chip/mt_scp: add mt8195 irq supportTinghan Shen2021-07-134-113/+451
| | | | | | | | | | | | | | | | | Update IRQ definition for mt8195 and move IRQ definitions to chip-specific folder. BRANCH=none BUG=b:189300514 TEST=make BOARD=asurada_scp && make BOARD=cherry_scp Change-Id: I3bb4d97e374328fbe86d537b14cce11322365c10 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2940337 Tested-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* chip/mt_scp: change uart clock to ULPOSCTinghan Shen2021-07-131-1/+1
| | | | | | | | | | | | | | | | Change UART clock to ULPOSC to keep SCP console alive when system suspend. BRANCH=none BUG=b:189300514 TEST=make BOARD=cherry_scp Change-Id: I144354fe946808c7ec68da4ea33e4ad11a7bf11f Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3003345 Tested-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* chip/mt_scp: support mt8195 clockTinghan Shen2021-07-139-98/+622
| | | | | | | | | | | | | | | | | | Supports mt8195 clock and move chip-specific clock registers from common to chip-specific. BRANCH=none BUG=b:189300514 TEST=make BOARD=asurada_scp && make BOARD=cherry_scp Change-Id: I8ef058f6314652050dead46e7f48d3420bbdd1d1 Signed-off-by: Roger Lu <roger.lu@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939167 Tested-by: tinghan shen <tinghan.shen@mediatek.com> Tested-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* driver/tcpm/ite_pd_intc: separate pd interrupt to ite_pd_intcRuibin Chang2021-07-091-78/+1
| | | | | | | | | | | | | | | | | Separate pd interrupt functions to ite_pd_intc for easier maintenance on cros_ec and zephyr. And enable PD interrupt functions for zephyr. BRANCH=none BUG=none TEST=1.can zmake hayato and make asurada 2.PD port functions work on board hayato Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Change-Id: I67082bb442da7dfb669e23d8315d81f4abe7ba76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999358 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* stm32: clock: avoid division by zero worries.Bossen WU2021-07-021-4/+4
| | | | | | | | | | | | | | | In chip_config.h, PLLM / PLLN / PLLR was predefined as 0. It raise concern that frequency calculation would have division by zero issue. Redefine PLLM / PLLN / PLLR as 1 to remove such worry. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: If57aa40af29e0176762a981bd5b2dac9528b1144 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999412 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : flashBossen WU2021-07-012-7/+44
| | | | | | | | | | | | | | | stm32l431 related driver: flash-stm32g4-l4.c system.c The stm32l476g-eval is the only board which would be possibly impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I273954c75651b20de58db53eba7e7d0e4553763d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2978652 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : adcBossen WU2021-07-012-1/+258
| | | | | | | | | | | | | | stm32l431 related driver: adc-stm32l4.c adc_chip.h The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I0ce73ee9ab02e1cfd20a178628d935d24a1907ce Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975521 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : dmaBossen WU2021-07-011-6/+29
| | | | | | | | | | | | | | stm32l431 related driver: dma The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: Ia513875963c2c65f6b63605fc113f139656a4028 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975520 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : i2cBossen WU2021-07-011-19/+25
| | | | | | | | | | | | | | | stm32l431 related driver: i2c-stm32l4 The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: If6187e6f3c2f82ab118524444c1849108bb82f82 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975519 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* mchp: Correct assigning I2C controller to a portVijay Hiremath2021-06-302-3/+15
| | | | | | | | | | | | | | | | | | Corrected default assignment of controller to I2C port based on the number of I2C ports being used rather than the port in use. This avoids overlapping of I2C controller assignment when the I2C ports used are not greater than MCHP_I2C_CTRL_MAX. BUG=none BRANCH=none TEST=Tested on ADLRVP, default I2C controller assignment is correct. Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Change-Id: I875b0f7e94162f923325e9ed07e7549cc760fdf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2980432 Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Move I2C_CONTROLLER_COUNT and I2C_PORT_COUNT to chipmartin yan2021-06-302-0/+8
| | | | | | | | | | | | | | | | | | Move I2C_CONTROLLER_COUNT and I2C_PORT_COUNT to registers-mec172x.h and registers-mec152x.h from board.h, both are chip specific BRANCH=none BUG=none TEST=Tested adlrvpp_mchp1727 and sklrvp_mchp1723 adlrvpp_mchp1521 and sklrvp_mchp Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Icd91e9877e0053c83c1a73d10470ffefedd90a01 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2982390 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* stm32: add stm32l431 ec in chip/stm32 : uartBossen WU2021-06-301-4/+28
| | | | | | | | | | | | | | | stm32l431 related driver: uart The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I861d1cf38430d6b1b5d7c09bd565d727961a4128 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975168 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : watchdogBossen WU2021-06-301-1/+30
| | | | | | | | | | | | | | stm32l431 related driver: watchdog. The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I8488a3bfad31dadedc65078d29c117cfb2308f77 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975160 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : system / clock / timerBossen WU2021-06-307-498/+2575
| | | | | | | | | | | | | | stm32l431 related driver: system / clock / timer. The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: Idf335005d8188f6959835aa40179a6bd771c5114 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905165 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* chip/mt_scp: support MT8195 UARTTzung-Bi Shih2021-06-292-0/+10
| | | | | | | | | | | | | Supports MT8195 UART. BRANCH=none BUG=b:189300514 TEST=make BOARD=cherry_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I948e0208f664de72de027357d4ba7336715e92fa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993789 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* chip/mt_scp: move UART pinmux settings to chip specificTzung-Bi Shih2021-06-296-11/+67
| | | | | | | | | | | | | | | | The pinmux setting is chip-specific. Turns the common code into chip-specific. BRANCH=none BUG=b:191835814 BUG=b:189300514 TEST=make BOARD=asurada_scp && make BOARD=cherry_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I22b8171f42025f294392b0bf1a25a4153eb648f7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993788 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* stm32: rename CONFIG_STM32_SPI1_MASTER to …CONTROLLERHarry Cutts2021-06-252-9/+9
| | | | | | | | | | | | | In line with OSHWA terminology. BUG=b:181607131 TEST=make -j BOARD=hammer BRANCH=none Change-Id: I6d212e60d5aceb8497f00520b693006cc1af2d45 Signed-off-by: Harry Cutts <hcutts@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981123 Reviewed-by: caveh jalali <caveh@chromium.org>
* chip/mt_scp: move rv32i specific to common folderTzung-Bi Shih2021-06-2525-30/+39
| | | | | | | | | | | | | BRANCH=none BUG=b:191835814 TEST=make BOARD=asurada_scp && make BOARD=cherry_scp && make BOARD=kukui_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I35e9fd5f7d3e83d35d09a093be09b194c821f63e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2985060 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* chip/mt8192_scp: fix unknown type errorsTzung-Bi Shih2021-06-251-0/+2
| | | | | | | | | | | | | | | Fixes unknown type errors such as: chip/mt8192_scp/ipi_chip.h:40:2: error: unknown type name 'uint32_t' uint32_t signaled; BRANCH=none BUG=b:191835814 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: If6f0f94540e099e547d7015e82bb4dacb88ebd3b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2985059 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* chip/mt_scp: move mt8183 specific to sub-folderTzung-Bi Shih2021-06-2519-83/+108
| | | | | | | | | | | BRANCH=none BUG=b:191835814 TEST=make BOARD=kukui_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ic8387200a741a4e7ef99e13772231a0ec0bc1fc1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2984255 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* chip/mt_scp: remove unnecessary path when includingTzung-Bi Shih2021-06-251-1/+1
| | | | | | | | | | | BRANCH=none BUG=b:191835814 TEST=make BOARD=kukui_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: If269a412af3e6455672a3d3f5de3e5fe1e4a63d0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2984253 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* Fix compilation issues with nocturne SDKPatryk Duda2021-06-171-1/+2
| | | | | | | | | | | | | | | | | | | | | Compiler in nocturne cros SDK doesn't allow for variable declaration inside for loop. This patch removes variable declaration inside for loop in code which is used by nocturne board. This patch doesn't introduce any logical changes. BUG=b:160676144 BRANCH=none TEST=Make sure EC points to commit on cros/main. On nocturne SDK: cros_workon-nocturne start chromeos-ec emerge-nocturne chromeos-ec chromeos-bootimage Make sure that firmware compiles Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I75ff21d966d5e353d1f7873695127bac4357fb32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2965922 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* ish/heci: initialize msg.payload before using itPatrick Georgi2021-06-171-1/+1
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=one class of error less with gcc 11 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Change-Id: I7c0d2b28ae7805b390e485ff69ec0f6c2a7d5e98 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2959919 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
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