summaryrefslogtreecommitdiff
path: root/chip
Commit message (Collapse)AuthorAgeFilesLines
* Revert "npcx: ensure we don't unlock watchdog too soon"Caveh Jalali2019-09-124-32/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 031c5d2d62dd891622ded885756c03021e934ef2. Reason for revert: introduced compilation errors: chip/npcx/spiflashfw/npcx_monitor.c: In function 'sspi_flash_upload': chip/npcx/spiflashfw/npcx_monitor.c:290:2: error: implicit declaration of function 'watchdog_stop_and_unlock' [-Werror=implicit-function-declaration] watchdog_stop_and_unlock(); ^~~~~~~~~~~~~~~~~~~~~~~~ Original change's description: > npcx: ensure we don't unlock watchdog too soon > > We cannot unlock the watchdog timer with 3 watch dog ticks of touching > it per the datasheet. This is actually around 100ms so we should protect > against this. > > BRANCH=none > BUG=b:140207603 > TEST=eliminates cold reset issue. > > Change-Id: Iaef59dad9f5640d64d5d430aea87bd16c2efd30d > Signed-off-by: Jett Rink <jettrink@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1790302 > Reviewed-by: Scott Collyer <scollyer@chromium.org> > Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> > Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> > Reviewed-by: Furquan Shaikh <furquan@chromium.org> > Tested-by: Furquan Shaikh <furquan@chromium.org> > Commit-Queue: Furquan Shaikh <furquan@chromium.org> Bug: b:140207603 Change-Id: I540fa53c2c568cb789400d55b807a672b182302a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1799293 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* npcx: ensure we don't unlock watchdog too soonJett Rink2019-09-124-13/+32
| | | | | | | | | | | | | | | | | | | | We cannot unlock the watchdog timer with 3 watch dog ticks of touching it per the datasheet. This is actually around 100ms so we should protect against this. BRANCH=none BUG=b:140207603 TEST=eliminates cold reset issue. Change-Id: Iaef59dad9f5640d64d5d430aea87bd16c2efd30d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1790302 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* Fix typo on STM32 i2c driverMario Tesi2019-09-111-1/+1
| | | | | | | | | | | | | | On STM32 discovery board build fails due to a typo on chip/stm32/i2c-stm32l.c in assignement BUG=none Change-Id: I8e01006f70165b797472eb367e70aebb8dcb9502 Signed-off-by: Mario Tesi <mario.tesi@st.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1720392 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* chip/stm32/dma.c: don't overrun array sizePatrick Georgi2019-09-101-1/+2
| | | | | | | | | | | | | | | | | On smaller models there may not be 7 channels. Found by Coverity Scan #157523 BUG=none BRANCH=none TEST=none Change-Id: I8b494c6714dfd355875c5b6069b65519e91efcc9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1793584 Tested-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip/stm/i2c-stm32f4: Remove constant conditionalsPatrick Georgi2019-09-101-12/+7
| | | | | | | | | | | | | | | | | | rv_start is effectively constant (and 0) after goto xfer_exit, so the conditionals aren't needed. Found by Coverity Scan #157505 BUG=none BRANCH=none TEST=none Change-Id: Id7d2445615ae0f1230a9245f0baf9b9ea1d9a80a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1793582 Tested-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* g: allow I2CS operate without hardware resetsVadim Bendebury2019-09-051-15/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not always possible to rely on PMU for resetting the I2CS controller. Most of the AP firmware versions deploy the 'I2C unwedge' cycle when coming out of reset, but not all of them, this is why Cr50 needs to be able to recover on its own in case there was a crash and the I2C bus was left mid transaction with the H1 holding down the SDA line. A GPIO is dedicated to monitor the I2CS_SDA line during reset. If the line is kept low, it could be a sign of a 'wedged' controller. The g I2CS FSM will reset any time the I2C 'stop' condition is detected. The create the 'stop' condition the I2C_SCL input is disconnected from the bus and connected to an internal GPIO, then I2C_SCL level is set to 'high' and register inverting the I2C_SDA value is toggled, which looks like a transition from zero to one to the controller. thus creating the 'stop' condition. BRANCH=cr50, cr50-mp BUG=b:135772657 TEST=the test was ran on a Pyro device, which uses I2C for communication with H1 and which AP firmware does not deploy the 'I2C unwedge' cycle. Test instrumentation involved setting a Chrome OS startup file such that once booted, the AP starts continuously polling TPM for value of an NVMEM index, creating I2C traffic. The host workstation sends the 'apreset cold' command to the EC within a few seconds of Chrome OS coming up. First run a special Cr50 image which is not resetting I2CS using PMU on TPM restarts, is was not trying to unwedge the stuck I2C bus. On five experiments, it takes on average 32 reboots for until I2C bus is locked up and the DUT falls into recovery. Then loaded the Cr50 image with this patch and ran the test again, it survived for 150 cycles without a problem. Change-Id: Iffec33f97557e3acfd1cd5fb76ba158f8c23b608 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1730143 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: fix UART TX done logicVadim Bendebury2019-09-031-15/+3
| | | | | | | | | | | | | | | | | | | TX is done when both TX_IDLE and TX_EMPTY conditions are true. Fixing the check makes unnecessary the code which waited for another character time before proceeding when flushing the UART TX FIFO. BRANCH=cr50, cr50-mp BUG=b:140305442 TEST=added code to print a really long string before reset in the 'reboot' command, observed that the entire string is reliably printed before the reset. Change-Id: I0882d96ba9ca5412deb704ccdbc43e8cebeeeab5 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1779587 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* audio_codec: refactor I2S RXTzung-Bi Shih2019-09-031-0/+2
| | | | | | | | | | | | | | | | Refactor by the following items: - use more specific name "i2s rx" - use verbose symbol names to separate namespaces - remove unused TDM-related code BRANCH=none BUG=b:122027734, b:123268236 TEST=make BOARD=kukui_scp -j && make BOARD=npcx7_evb -j Change-Id: I8ccda5b5bbd9cf144bd68ba25249c8243b3086ac Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1564500 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cr50: added references to FIPS / NIST standards to cryptographic functionsVadim Sukhomlinov2019-08-294-22/+109
| | | | | | | | | | | | | Clarified standards compliance status for cryptographic functions. BRANCH=cr50 BUG=b:138574542 TEST=code compiles, unit tests pass Change-Id: I75ce155b53d1ce049e5063d2aaa1464b75f7d678 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1769420 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* mchp/espi: fix error condition handlingPatrick Georgi2019-08-281-7/+10
| | | | | | | | | | | | | | | | | As uint tidx can't be < 0 which can lead to overflow further down. (Found by Coverity Scan) BUG=none BRANCH=none TEST=none Change-Id: I63988be98a64292362cdc017beceac296ddde0dc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1768650 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
* mchp/i2c: Fix boundary checkPatrick Georgi2019-08-281-8/+8
| | | | | | | | | | | | | | | | | | It's an off-by-one and the same test is implemented properly in the following function, so use that. (Found by Coverity Scan) BUG=none BRANCH=none TEST=none Change-Id: Idfe3ae0f1128e430a0d52c151e264de86579c67a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1768649 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
* mtk_vcodec: Add the service for h264 decoderYunfei Dong2019-08-262-1/+8
| | | | | | | | | | | | | | | Fix the service to support h264 decoder. BRANCH=none BUG=b:123551776 TEST=build kukui_scp pass. Change-Id: Iccd6389a40239a6d6791543eeb522cc3e5fc3991 Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644186 Commit-Queue: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-2628-150/+157
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Revert "it83xx/intc:message id of pd packet repeat"Yilun Lin2019-08-251-47/+1
| | | | | | | | | | | | | | | | | This reverts commit bd19b03b128db664dfb5e6582810bd177b635408. With https://crrev.com/c/1757596/ merged, one doesn't need to handle repeated MessageID in TCPC. TEST=make buildall BUG=b:134556286 BRANCH=none Change-Id: I0f97e4e574b94ecbc23e5ee97ade7cc4da7f9020 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1763895 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* g: corrected division algorithm in DCRYPTO_bn_divVadim Sukhomlinov2019-08-231-0/+1
| | | | | | | | | | | | | | | Long division algorithm computes incorrect answer in rare cases causing valid RSA signatures to be rejected. BRANCH=cr50 BUG=b:137973895 TEST=tpm_test passes Change-Id: Ie8f39eed21443978734adbbf60b72d7701154c18 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1766088 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g: add vendor cmd to get/set the endorsement seedMary Ruthven2019-08-131-1/+64
| | | | | | | | | | | | | | | | We've had some eraseflashinfo issues that cause the endorsement key seed to get lost. Add a vendor command, so we can set the endorsement key seed if it's erased. BUG=b:138943966 BRANCH=none TEST=get/set endorsement key seed. Change-Id: Iee7d78e22f44786efd86b3ec68780a53e567705d Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1740075 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* dma: separate out DMA enable status from wait_for_bytesTom Hughes2019-08-136-26/+53
| | | | | | | | | | | | | | | | | | | | | | | When wait_for_bytes returns 0 when DMA is disabled, we can't differentiate between DMA being disabled and a transfer having completed when it has reached the end of the requested transfer. Separating out into separate functions lets us distinguish the two cases. The reason we didn't hit this in the past is that the requested receive size is generally larger than the actual amount we're sending. Since we know the amount that we're waiting for from the header, we would stop the transfer in software. BRANCH=none BUG=b:132444384 TEST=On DUTs with bloonchipper and dartmonkey: ectool --name=cros_fp testmaxtransfer TEST=make buildall -j Change-Id: I885161a3e04b7a12d597d8dc8691f599990bda8b Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1734010 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: i2c: adjust i2c bus frequency when it is set to 100kHz.Mulin Chao2019-08-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When npcx i2c module's bus frequency is set to 100KHz, it operates in normal mode and its bus frequency, fSCL, follows the formula listed below: fSCL = fCLK / (4*SCLFRQ), ie. SCLFRQ = fCLK / (4*fSCL) where fCLK is the source clock frequency of i2c module and SCLFRQ defines the SCL output period in SMBCTL2/3 registers. But integer division in this formula is equal to the floor of regular division if it isn't divisible. So far, all i2c modules' source clock frequency is 15MHz and if the desired i2c bus frequency is 100KHz, the SCLFRQ will be: SCLFRQ = fCLK/(4*fSCL) = 15MHz/(4*100kHz) = floor(37.5) = 37 And the actual i2c frequency is: fSCL = fCLK/(4*SCLFRQ) = 15MHz/(4*37) = 101.35KHz That's why we observe the i2c frequency is slightly higher than 100kHz. To fix this issue, this CL replaces integer division with the ceiling value of the formula to make sure bus frequency is lower than 100KHz and meet i2c spec when it operates in normal mode. BRANCH=none BUG=b:138350407 TEST=No build errors for npcx series. Measure the actual i2c bus which is configured to 100KHz after applying this CL. The actual frequency is 98.7 KHz on npcx5/7 evbs. Change-Id: I71e2c3090bc91c7b9945c01c04c9ac5ac656c893 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1741566 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* cr50: use dedicated region for info1 accessesVadim Bendebury2019-08-105-103/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The INFO1 flash space is used for various purposes (endorsement key seed, Board ID and flags, serial number, etc.). Accessing these spaces in INFO1 is accompanied by managing the flash region registers, each time opening a window of the appropriate size, with appropriate permissions, etc, In fact none of these spaces contain a secret, to simplify things and preventing situations when concurrent accesses change the flash range window settings lets dedicate previously unused Region 7 register file to providing always open read access to INFO1. Write access will be enabled/disabled as required. In prod images write accesses will always happen from the vendor command context. In DBG images CLI commands will also have write access to INFO1. INFO1 window is accessed by other H1 based devices as well, this is why it is necessary to enable the window in the common chip code. BRANCH=cr50, cr50-mp BUG=b:138256149 TEST=the firmware_Cr50SetBoardId test now passes on Mistral. Cq-Depend: chrome-internal:1577866, chrome-internal:1581327 Change-Id: Id27348f3b04191f1b3b60fd838d06009f756baa2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1730147 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: Make DMEM word writes explicitLouis Collard2019-08-091-85/+104
| | | | | | | | | | | | | | | | | | This change refactors access to DMEM during ECC operations to make all writes explicitly word writes. This is effectively a no-op, but should prevent against any future regressions. BUG=b:131807777 TEST=build and flash on soraka locally, ensure signature of known blob matches signature generated prior to this CL BRANCH=none Signed-off-by: Louis Collard <louiscollard@chromium.org> Change-Id: Ie24712c3f4a5dc15c8ad08cd50b9e8b9cdab2822 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1595928 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* mt_scp: Do not set cache-size in SCP FW.Yilun Lin2019-08-072-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | cache-size and way setting should be done in kernel driver side. Logical memory address will be shifted when cache size config changes. e.g. - 8 kb I-cache + 0 kb D-cache: logical address of I-cache 0x7e000~0x7ffff - 8 kb I-cache + 8 kb D-cache: logical address of I-cache 0x7c000~0x7bfff I-cache region moves starting address from 0x7e000 to 0x7c000, and it forces all the contents which was in 0x7c000~0x7dffff step back for 8KB. i.e. The logical address are changed by 8kb. This will break the loaded SCP firmware layout. As a result, we should configure the cache size before loading firmware and never re-configure it in SCP FW. BUG=b:137920815 TEST=Reboot kukui, and see SCP can successfully boot on first time. BRANCH=None Change-Id: I58342e8276b654a786864904cde980c6fc9ef781 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1725384 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org>
* mt_scp/ipi: only invoke interrupt when ipi readyYilun Lin2019-08-071-1/+1
| | | | | | | | | | | | | | | | | IPC interrupt should only be invoked when the task inited and informing AP that SCP is ready. TEST=Boot SCP, and doesn't see the process stack overflow. BUG=b:137920815 BRANCH=none Change-Id: Ibe926b77705718a986c3b090227328b569cd9b59 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1736411 Reviewed-by: Erin Lo <erin.lo@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org>
* ectool/trng: Add "rand" host command for testing RNGTom Hughes2019-08-061-2/+34
| | | | | | | | | | | | | | | | | | | | | This host command and corresponding ectool command allows us to generate random numbers with the MCU's RNG and process the resulting output with tools to validate the statistical randomness, such as dieharder (https://webhome.phy.duke.edu/~rgb/General/dieharder.php) and NIST SP 800-22 (https://csrc.nist.gov/publications/detail/sp/800-22/rev-1a/final). BRANCH=none BUG=b:124770147 TEST=ectool --name=cros_fp rand 1 > rand.bin; ls -la rand.bin TEST=ectool --name=cros_fp rand 536 > rand.bin; ls -la rand.bin TEST=ectool --name=cros_fp rand 537 > rand.bin; ls -la rand.bin TEST=ectool --name=cros_fp rand 99999999999999999999999999 Change-Id: Ic0bda4deae79fc7465671dcacfe8bbc9a066b5e5 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1726822 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* g: refactor pinmux state printing functionVadim Bendebury2019-08-021-10/+20
| | | | | | | | | | | | | | | | | | This refactoring improves optional parameter alignment, includes virtual pads in the output and shaves 44 bytes from the image size. BRANCH=cr50, cr50-mp BUG=none TEST=saved pinmux command output in files pm.before and pm.after, then verified that the following command produced no output $ diff -w <(sort pm.before) <(sort pm.after) Change-Id: I81c2fad8c9e87e05dd39c588340a82f83e3ab488 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1731138 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: add flash log entry for dcrypto failuresstabilize-12386.BVadim Bendebury2019-07-311-5/+13
| | | | | | | | | | | | | | | | We want to keep an eye on the dcrypto failures (which are never supposed to happen of course). Let's add logging a flash event so that the failures are visible through UMA. BRANCH=cr50, cr50-mp BUG=b:135772657 TEST=using additional code simulated a single failure, observed new flash log entry by running 'gsctool -a -L' on the DUT. Change-Id: Ib675bb1928166cadc069bf4be3b053a9cf837077 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1723097 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* common/system: refactor some confusing ifdefsJack Rosenthal2019-07-311-0/+3
| | | | | | | | | | | | | | | | | I had a hard time reading this section, so figured I may as well rewrite it to use IS_ENABLED while I was here. Gave CONFIG_{RO,RW}_HEAD_ROOM a default value of zero here, which makes the math work out for boards without it anyway. BUG=none BRANCH=none TEST=buildall Change-Id: I87dc2d73838c350088916b57aa51d5f368c5592f Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1727570 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* g: Force word writes for k during ECDSA signLouis Collard2019-07-311-4/+13
| | | | | | | | | | | | | | | | | | Functions that take p256_int* parameters may use byte writes when writing to those parameters. When writing to DMEM_ecc, we must use word writes; this change ensures that happens. BUG=b:131807777 TEST=build and flash to soraka locally, ensure k is populated successfully BRANCH=none Change-Id: I49462b10aa1203fe875417e9526f06b2efc068fb Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1592990 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g: reset and wipe dcrypto engine after timeout.Marius Schilder2019-07-291-22/+203
| | | | | | | | | | | | | | | | | | | In case of a timeout, we need to clean up state and make sure engine is ready for a subsequent call. Added dcrypto_test console command to test the various scenarios: stack overflow, infinite loop and cfi failure recovery. Signed-off-by: mschilder@google.com BUG=b:135772657 BRANCH=none TEST=run console command dcrypto_test; build and run cr53 Change-Id: I531a59de6f2cf6941c797aeeeabb10eb10f02c9b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1677229 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Commit-Queue: Marius Schilder <mschilder@chromium.org>
* chip/host: Add check for TEST_BUILD in trng.cCraig Hesling2019-07-271-0/+4
| | | | | | | | | | | | | | | | | | | Due to the possibly unnoticeable security vulnerability it would cause if the dummy host trng driver made it's way into production (non-test) code, this change adds a small check to ensure it is being used only in test or fuzz builds. This isn't as much of a concern for other dummy host drivers. For example, including a fake spi driver may simply manifest as broken feature. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I31138976566d39ed44d905bbb2c43c5f6decbaf4 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1722182 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/mt_scp/clock.c: enable pwrap_scp clockHsin-Hsiung Wang2019-07-262-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | During suspend, pmic wrap will be waken up by scp which is due to hw design. However, the clock of pmic wrap is 26mhz which would be turned off in the suspend mode, so we needs to change the clock of pmic wrap from 26mhz to ULPOSC. BRANCH=none BUG=b:135985700 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP alias rtcalm='echo "+15" > \ /sys/class/rtc/rtc0/wakealarm' rtcalm cat /proc/driver/rtc powerd_dbus_suspend TEST=Can resume in suspend. Change-Id: I07b9d76f574fe1007e20f185bb278e0884397176 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686990 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* i2c: don't scan i2c addresses less than 0x08Jett Rink2019-07-251-3/+2
| | | | | | | | | | | | | | | None of the existing i2c addresses in the EC code base are less than 0x08 and those addresses are reserved by the i2c and SMBus specification. BRANCH=none BUG=b:138156666 TEST=i2c bus scan with a smart battery doesn't "misbehave" any more and other devices can be detected properly. Change-Id: I561b082c4c7e3df7caaa33b6ef6ad467dabbd5a5 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1715326 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* hatch_fp: Add RDP (read protection) support to STM32F4Tom Hughes2019-07-244-2/+159
| | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:125419658 TEST=Remove "-U" flag in STM32MON_READ_FLAGS in flash_fp_mcu_common.sh flash_fp_mcu -r foo.bin => success hexdump foo.bin => valid data ectool --name=cros_fp flashprotect enable ectool --name=cros_fp reboot_ec flash_fp_mcu -r foo.bin => fails Add "-U" flag back to STM32MON_READ_FLAGS in flash_fp_mcu_common.sh flash_fp_mcu -r foo.bin => success hexdump foo.bin => all 0xFF Change-Id: Ic3ec18262e653b72baf239caa8db12186a63613c Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1692220 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: make i2c slave address uint16_t to be standardDenis Brockus2019-07-231-1/+1
| | | | | | | | | | | | | | | | | | | | EC code changed over to a 7-bit slave address and stored in a uint16_t to generically be able to handle 10-bit addresses, if they are ever needed, as well as common bit flags in the most significant bits. This code does not use more than the 8 least significant bits but to be EC consistent, I am making this 16 bits. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ic5f4b3500ae7b3c18380b188efbc37c01d58d7e9 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1714136 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* npcx7: UART: wait for Tx empty before enabling deep-sleepCHLin2019-07-234-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the original firmware (in the uart_buffering.c), it clears the SLEEP_MASK_UART immediately after it pushes all characters from its Tx buffer to UART's FIFO without checking the status of transmission. It may break the transmission because EC goes to deep sleep before UART TX (FIFO or shift register) becomes empty. This CL fixes it by: (1) Don't clear SLEEP_MASK_UART immediately when uart_tx_stop is called. (2) Enable the NXMIP (No Transmit in Progress) interrupt. (3) Clear SLEEP_MASK_UART in the UART interrupt handler when NXMIP is set. This fix only needs to apply to NPCX7 chips which have UART FIFO support. BRANCH=none BUG=b:137143640 TEST=No error for "make buildall" TEST=run 10 iterations of uart_stress_tester on yorp with command: ./util/uart_stress_tester.py /dev/ttyUSB2 -t 360; make sure no character lost in each iteration as below: ... INFO | UartSerial| /dev/ttyUSB2 | Detected as EC UART INFO | UartSerial| EC | Ready to test INFO | ChargenTest | Ports are ready to test INFO | ChargenTest | Test starts INFO | UartSerial| EC | Test thread starts INFO | UartSerial| EC | Test thread is done INFO | UartSerial| EC | 0 char lost / 4147200 (0.0 %) INFO | ChargenTest | PASS: lost 0 character(s) from the test INFO | ChargenTest | Test is done Change-Id: I97b1f572e8b9ebdb5102aa3e98ae2963d768b5b3 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703944 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* ish: fix snowball structure linker placementDenis Brockus2019-07-223-30/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following bug https://buganizer.corp.google.com/issues/136002955 indicates after my initial move of snowball to use the linker map instead of hard defined addresses that 0xFF801E80 was reading back as all zeroes. The change that was made for this is https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593 I double checked the map files and everything looked good. For some reason using the linker to map the location of this structure, the system does not run properly. If I remove the link map placement of this structure then the issue goes away. I looked at how aon_share was placed at the specific address in AON memory and this CL is doing the same thing and it is working. I think this is the way we should keep this fix and not try to get the linker map to place this structure where we want it. BUG=b:136002955 BRANCH=none TEST=make buildall -j TEST=verify soft reboot does not indicate power reset Change-Id: Ibb6dbd3a4414b5c546e99f5ad7e0409250de6256 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1707998 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-2015-153/+153
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-1915-171/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* chip/host: Add spi+trng support, and add gpio funcCraig Hesling2019-07-184-1/+85
| | | | | | | | | | | | | | | | | | | | This adds fake SPI Master and TRNG support to the host target. This change also adds the missing emulated gpio interface function. Although general purpose, these changes are setup for allowing fuzzing of the FPMCU specific host commands. Thus, they do not impact any outstanding code. BRANCH=none BUG=b:116065496 TEST=make buildall -j Change-Id: Icfc40e7bf8ee421a4c3ad15377fd56ae68c763d7 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684223 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Basic implentation of the Maxim Integrated MAX32660 within the EC OSJerry Bradshaw2019-07-1718-0/+6195
| | | | | | | | | | | Includes System Clock, Timer, Uart, Watchdog Change-Id: I195059c87d97e70c6a134304143613b86b623e22 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1647741 Reviewed-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Jerry Bradshaw <jerry.bradshaw@maximintegrated.com> Commit-Queue: Jes Klinke <jbk@chromium.org>
* cr50: provide separate environment variable to enable crypto testsVadim Bendebury2019-07-171-4/+0
| | | | | | | | | | | | | | | | | | | | Presently the CR50_DEV environment variable is overloaded, if its value is a number exceeding 1, it enables inclusion in the image of the dcrypto tests. To make things cleaner let's use a separate environment variable to add dcrypto tests to the image. Note that the tests still can not be enabled, as they do not fit into the flash code space. BRANCH=cr50, cr50-mp BUG=b:137659935 TEST=verified that image building with CRYPTO_TEST=1 fails due to exceeded code size. Change-Id: I550c219c1eefe01fbe035b85a1d5aae88ea439de Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704607 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* mt_scp: Trigger IRQ if has pending IPC when re-enable SCP_IRQ_IPC0.Yilun Lin2019-07-171-3/+18
| | | | | | | | | | | | | | | | | | | | Prevent a starved waiting IPC. IPC may be requested while SCP_IRQ_IPC0 is disabled, and this may result in AP dead waiting for a reply from SCP. This CL forces triggering the SCP_IRQ_IPC0 if seeing a pending IPC when re-enable the SCP_IRQ_IPC0. TEST=run factory front_camera_test for over 1 hr and see AP doesn't complains HC not respsonsed. BUG=b:136809224, b:136616282 BRANCH=None Change-Id: Ic36da774994f6c571c3b79fd6717562f8866b7df Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697884 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org>
* mt_scp: Drop TCM and L1 cache setting.Yilun Lin2019-07-172-8/+11
| | | | | | | | | | | | | | | | | | | | This config has been moved to kernel https://crrev.com/c/1687454 to correctly initialize L1 cache. We should drop the config in SCP side. Also, update the comment for CM4_MOD registers. TEST=Boot SCP with kernel https://crrev.com/c/1627394/10 BUG=b:132658087 BRANCH=none Change-Id: I37613533563acc00017f96a3d3009383057f072b Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703946 Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Erin Lo <erin.lo@mediatek.com> Commit-Queue: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org>
* stm32: Add known variants to registers filesCraig Hesling2019-07-175-0/+21
| | | | | | | | | | | | | | | | | | Although these registers files may support other variants, these listed variants are the only ones that are referenced throughout EC codebase. They were collected using the following grep line: grep -rIi 'variant.*stm32.' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I3691d8db5c2a6c1a94bb5df40edf12504c3fee7e Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700168 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Factor out stm32f7 family registersCraig Hesling2019-07-174-55/+1093
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extracts the STM32F76X variant from the STM32F4 family registers file. This also removed a redundant #ifdef CHIP_FAMILY_STM32F4 inside the F4 family register file. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash # Make dummy board for STM32F76X using STM32f7 fammily mkdir -p board/usestm32f7 printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f7\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk touch board/usestm32f7/board.h ./registers-extract.bash board-regs-new git checkout cros/master # Change family back to STM32F4 printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f4\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new # Expect only a difference in CHIP_FAMILY Change-Id: I5ff87e1c82c5d27d78c3ea62fed29d647a0f98db Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700167 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Add header guard and fix fmt/doc of registers header fileCraig Hesling2019-07-177-260/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | We enforce that all family specific registers file can only be included from registers.h. We add a brief history and rationale behind splitting registers.h into multiple family specific header files. We fix formatting of preprocessor conditionals and documentation. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash ./registers-extract.bash board-regs-new git checkout cros/master ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new [ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I5d5983eb1e0cf7fb46339cba2987d551ff6b16cc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693879 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Manually fix separate register filesCraig Hesling2019-07-165-92/+4
| | | | | | | | | | | | | | | | | | | | | | This fixes the CPP conditionals that could not be separated using the split script. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash ./registers-extract.bash board-regs-new git checkout cros/master ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new [ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I40eac114cd5ed7abe708cc51242a3b267aaaf118 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693876 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Split registers.h into independent filesCraig Hesling2019-07-157-2706/+6243
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the sort_file.bash script from this bit: http://go/bit/hesling/5840756455505920/7 $ git fetch "https://chromium.googlesource.com/chromiumos/platform/ec" refs/changes/78/1674678/6 && git cherry-pick FETCH_HEAD $ cp registers.h registers-split.h $ ./sort_file.bash chip/stm32/registers-split.h f0=chip/stm32/registers-stm32f0.h f3=chip/stm32/registers-stm32f3.h f4=chip/stm32/registers-stm32f4.h h7=chip/stm32/registers-stm32h7.h l=chip/stm32/registers-stm32l.h l4=chip/stm32/registers-stm32l4.h com=chip/stm32/registers.h Modified registers.h to include chip family specific header file. Modify copyright year of output files. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash ./registers-extract.bash board-regs-new git checkout cros/master ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new [ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: Ia7804e9a346ed94f881bd5583f5a4bf78422cb47 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1674679 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* arcada: ensure i2c transmit fifo is emptyLeifu Zhao2019-07-141-2/+3
| | | | | | | | | | | | | | | | | | | | Make sure transmit fifo is empty before disable i2c controller during transfer, otherwise the i2c write may fail for speed 100k, it also helps 400K and 1M. BUG=b:137218876 BRANCH=none TEST=tested on arcada Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I6f9fb9a71c28f2d3f9696340cc87fe3b72c25a02 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697061 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* ish: fix aon task not auto rebuild issue in increment buildHu, Hebo2019-07-122-13/+37
| | | | | | | | | | | | | | | | | | | | | aon task image build rules are lack of dependent rules of source code, so can't track the source code changes and trigger auto build. Refactor build rules for aon task to make sure always auto rebuild when aon task's source code and dependent header files update BUG=b:136691893 BRANCH=none TEST= ish aon task should always rebuild when it's code and dependent header files update Change-Id: I0d8c7c6a4a2b7e99d724b88b233e09a29b8facea Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688701 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* stm32h7: Fail build if CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE not usedTom Hughes2019-07-111-0/+3
| | | | | | | | | | | | | | | | As comment indicates, we're not sure that using RSS1 for the write protect PSTATE is safe. BRANCH=none BUG=chromium:888104 TEST=In nocturne_fp board.h file: #undef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE => Build fails with error as expected Change-Id: I0236381738e7ecf9b18a8d10dc7ba4b9dc370001 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693339 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
View Lorry Controller Status