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* npcx: add device id for npcx586g/npcx576gKevin K Wong2016-05-041-0/+4
| | | | | | | | | | | | BUG=none BRANCH=none TEST=version command shows the correct chip device id Change-Id: I312b343f97a99b3ff5ae7d6ec3606cff291b2b55 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/342130 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* apollolake: ignore PLTRST# from SOC unless RSMRST# is deassertedKevin K Wong2016-05-031-4/+3
| | | | | | | | | | | | | add optional chipset specific function to check if PLTRST# is valid BUG=chrome-os-partner:52656 BRANCH=none TEST=make buildall, able to boot to OS on amenia Change-Id: I7a2747c4f77f50393c3250c2ab0e1625e64e5a41 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/341732 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Enable jittery clockBill Richardson2016-05-034-0/+69
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:52576 BRANCH=none TEST=make buildall; try on Cr50 I manually tested both highsec and highperf variants, as well as forcing the bootrom init to run. All the bank registers were loaded with meaningful values, and none of the SPI or USB functionality showed any problems. Change-Id: Ia91ba98ef4c667aec74195c4a7bbf72a5d1c8b2d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342030 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: Reduce system stack sizeShawn Nematbakhsh2016-05-021-1/+1
| | | | | | | | | | | | | | | | Reduce system stack size to 1K to match other recent chips. BUG=None TEST=Build + boot on kevin. BRANCH=None Change-Id: I0be6e865ca03f4eef2ee7a99856df8257d7269d9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341850 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* g: enhance upgrade protocol to allow upgrade block restartsVadim Bendebury2016-05-021-3/+38
| | | | | | | | | | | | | | | | | | | | | With this new protocol version the target watches the size of the received messages while reassembling an upgrade block. If a message of the header size arrives and it is not the last message of the block, the target considers it a re-start of the block transfer by the host (presumably because a chunk was lost and the host did not receive a confirmation of the block transfer in the preceding block transfer attempt.) BRANCH=none BUG=chrome-os-partner:52586 TEST=the upgrade command on the host reports target running protocol version 2, upgrades on B1 board still run smoothly. Change-Id: I2e16c1be5135c0b5a4f09ea293f09ecabf59ecb3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341630 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: verify that first message of each upgrade block is rightVadim Bendebury2016-05-021-11/+13
| | | | | | | | | | | | | | | | | | | When a new upgrade block starts, the host sends first a 12 byte message including the block size and header. The target must verify that the message is of the proper size and the contents make sense (the header is not all zeros). It also should drain the USB queue completely in case it holds a message of a different size. BRANCH=none BUG=chrome-os-partner:52856 TEST=upgrade still works fine on B1 Change-Id: I80538a3a1a5d507a84bd21b868a3db626bc6a4b0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341619 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: upgrade - improve verification of the first upgrade messageVadim Bendebury2016-05-021-6/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | When an upgrade transfer starts, the target expects to receive a 12 byte transfer start message from the host, carrying an empty payload of all zeros. The target and host can be out of sync for whatever reason, so when the target is expecting a transfer start message, the host can be sending a chunk of a code block instead. In this case the target pulls just 12 bytes off the receive queue, leaving the rest of the chunk there, which even more complicates error recovery. This patch makes sure that when expecting the upgrade transfer start message the target extracts all receive data from the queue, no matter how many bytes have been received, and then verifies that the size matches the expected size, and that the payload is all zeros, to confirm that the message is indeed the transfer start message. BRANCH=none BUG=chrome-os-partner:52586 TEST=cr50 firmware upgrade still works fine on B1 Change-Id: If5ec86d0385f97f0f361635b3903cea3a962b707 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341618 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: introduce versioning and backwards compatibility of usb_upgradeVadim Bendebury2016-05-021-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original version of usb_upgrade does not provide for any error recovery and also does not support any protocol version notion. Real life experience has shown that error recovery is essential, it needs to be introduced as a protocol enhancement. We want to stay backwards compatible though, so there is a need for protocol versioning. In the original version of the protocol target response is always the same: a 4 byte number which is the error code (and zero means no error). This patch modifies response to the very first packet from the host, the startup packet. The startup response is 8 bytes long. The first 4 bytes is still the same as before, the second 4 bytes carry the protocol version supported by the target, an integer in network byte order. Thus, receiving a 4 byte reply to the startup message tells the host that the target is running protocol version zero, 8 byte reply carries the actual version number in the last 4 bytes. The USB transfer function on the host is enhanced to accept responses shorter then expected, when allowed. BRANCH=none BUG=chrome-os-partner:52856 TEST=usb_updater can successfully update both old and new cr50 images, properly reporting protocol version as 0 or 1 respectively. Change-Id: I9920d2708b21f29615282161fc0eb027018f9378 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341617 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: drop: always start with USB facing external portVadim Bendebury2016-05-021-3/+8
| | | | | | | | | | | | | | | | | | | | | We want to be able to communicate with the chip no matter what the hardware conditions are, otherwise it is easy to lose the ability to re-program it from the external connector. With this patch the chip always comes up with the USB interface exposed and will stay in this mode until debug cable is pulled out. After that it will honor subsequent cable plug ins/pull out events as designed. BRANCH=none BUG=chrome-os-partner:52281,chrome-os-partner:50700 TEST=Suzy-q reliably creates serial interfaces when the chip is programmed with the code including this patch. Change-Id: I608fb1912f1b2e88f7a207cbfff145760da1a4e4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341580 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: fix debug messages not to include two newlinesVadim Bendebury2016-05-021-6/+6
| | | | | | | | | | | | | | The CPRITS() macro adds newline to all strings, there is no need to explicitly add newlines. BRANCH=none BUG=none TEST=usb upgrade debug messages do not span two lines any more Change-Id: I1991214ddaa5945bedba861d67b392973f6a3d0f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341615 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: recover from usb_upgrade interruptionsVadim Bendebury2016-05-021-1/+27
| | | | | | | | | | | | | | | | | | | | | The usb upgrade protocol is very fragile, any error while transferring data causes the state machine on the target to lock up, and the only way to resume the upgrade is to power cycle the device. With this patch USB callbacks which happen more than 5 seconds since the previous callback would be considered a start of new transfer, thus allowing to attempt a new upgrade without the power cycle. BRANCH=none BUG=chrome-os-partner:52856 TEST=the following script allows to upgrade successfully: $ while not ./extra/usb_updater/usb_updater build/cr50/ec.bin; do sleep 6; done Change-Id: Ibe1078cf62073ce89a31416522b0d6917bc923b9 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341572 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add basic rbox supportMary Ruthven2016-04-294-0/+127
| | | | | | | | | | | | | | | | | This change modifies the behavior of RBOX by blocking the key0 and key1 output, when the power button is pressed. It also adds support for printing debug statements when various RBOX interrupts are triggered. BUG=none BRANCH=none TEST=On cr50 test board verify key0 and key1 out are not asserted unless the power button is pressed. Change-Id: I67a3c1b8009279015bdc87bcf0995cffa9ab6f03 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341470 Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Move board-specific rdd stuff out of chip/g/Bill Richardson2016-04-292-7/+4
| | | | | | | | | | | | | Poking GPIOs is something that belongs in board/ not chip/ BUG=none BRANCH=none TEST=make buildall; test on Kevin Change-Id: I798053c3760415ed787800d37eb81c765b826399 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341065 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* STM32: Add HSE and PLL to clock source selectionDaisuke Nojiri2016-04-293-50/+263
| | | | | | | | | | | | | | | | | | | This patch adds HSE and PLL as a system clock oscillator for STM32L4. This allows us to drive the chip at a higher frequency (up to 80 MHz), which is necessary to big-bang GPIO ports accurately. BUG=none BRANCH=tot TEST=make buildall. Verified console works on STM32L476G-Eval using HSE, PLL-HSE, PLL-HSI, PLL-MSI as an oscillator. Verified console runs soundly with different frequencies from 20 Mhz to 80 Mhz. Verified frequencies using oscilloscope on MCO (Microcontroller Clock Output) port up to 50 MHz. Change-Id: I493cdb6c323eb4e6a1560f6d030935c1950b1a2a Reviewed-on: https://chromium-review.googlesource.com/341275 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* STM32: Set UART clock sources to SYSCLKDaisuke Nojiri2016-04-292-3/+13
| | | | | | | | | | | | | | | | Since uart_freq_change assumes we drive UARTs at system clock, we need to set UARTs clock sources accordingly. This will allow us to clock up the chip without worrying about prescaler values set for HCLK and PCLK or the on/off status of HSI. BUG=none BRANCH=tot TEST=make buildall. Verified LPUART on stm32l476g-eval. Change-Id: I02898921e31b68cacbc2235a29c47a212c350afe Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341260 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pwm: Add PWM_CONFIG_DSLEEP config flagShawn Nematbakhsh2016-04-277-21/+50
| | | | | | | | | | | | | | | | | | | Add PWM_CONFIG_DSLEEP PWM config flag, which can be set to keep a channel active during low-power idle / deep sleep. Currently it's supported by npcx and mec1322. BUG=chrome-os-partner:52783 BRANCH=glados TEST=Manual on chell w/ subsequent commit + CONFIG_LOW_POWER_S0. Verify KB backlight does not flicker during idle. Change-Id: Ib9df5879aaa7dfa5764de1583496de84d40d2bb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341002 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* g: i2c slave driverVadim Bendebury2016-04-272-0/+233
| | | | | | | | | | | | | | | | | | | | | | | A fairly detailed description of the driver is included in the comments in the file. As of this submission the setup is fairly brittle, as clock stretching is not yet enabled, and there is no guarantee that the slave will prepare the data for the master in time. More testing will be required and enhancements will be added in the future. BRANCH=None BUG=chrome-os-partner:40397 TEST=with the rest of the patches applied, an i2c app running on the desktop allows read and write TPM registers using the USB-FTDI-I2C cable connected to the B1 board. Change-Id: I46b13d360ca92271702268f9088193b5ada583be Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340519 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* servo_micro: add gpio mode get and setNick Sanders2016-04-271-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO console commands currently only show input voltage level, and can only set level on predefined outputs. This change allows GPIOs to be cycled between output, input, and alternate function, as well as displaying the mode and asserted level (if any) in gpioget. This change creates CONFIG_CMD_GPIO_EXTENDED as the internal gpio interface needs to be changed to support this, and I can't test the other architectures. It may be worthwhile to add this for all, or not. This change is also necessary also for servo micro JTAG and PD UART support, as several pins are tied together on the flex and stm32 outputs need to be variously active or in high-z depending on mode. BUG=chromium:571477 TEST=gpioget <0|1|IN|A|ALT>; gpioget; BRANCH=None Change-Id: Iba32992db6244ee1e654db840d1c9c11dd2a0993 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338885 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* UART: Remove enable/disable interrupt functionsAnton Staaf2016-04-278-92/+5
| | | | | | | | | | | | | | | | These were not being used and complicate changes to the UART API. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I73e256f09f7ea72f0cc4831cc7ce391a7125e555 Reviewed-on: https://chromium-review.googlesource.com/340841 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: enable AP and EC flash accessstabilize-8249.BMary Ruthven2016-04-261-0/+7
| | | | | | | | | | | | | | | | | | | | | The cr50 SPI master can control the external AP and EC SPI ROM. This change adds support for doing spi_transactions, but does not use the SPI transactions for anything except console commands. This support will be used for flashing the AP and EC through CCD. For now AP and EC flash select must be done manually using the spi_flash_select console command. Flash select should be disabled after use, because it will prevent the system from booting. BUG=chrome-os-partner:50701 BRANCH=none TEST=Enable spi_flash commands. Select AP ROM and verify spi_flashinfo, read, erase, and write commands work properly. Select EC ROM and verify the same commands. Change-Id: I16c55015794f8513effe0fa5712488a84bed2627 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339844 Reviewed-by: Shawn N <shawnn@chromium.org>
* STM32: Support LPUART consoleDaisuke Nojiri2016-04-254-2/+32
| | | | | | | | | | | | | | | This patch adds support for console on LPUART (low power UART). It is wired to the USB type B port on the board, which is also one of the power sources. So, using LPUART simplifies the set up. BUG=none BRANCH=tot TEST=Verified console works on stm32l476g-eval. make buildall Change-Id: Iccf697cfabdcb7e1362d8453708eb79610d2e0cb Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340101 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Bring up STM32L476G-EvalDaisuke Nojiri2016-04-2510-16/+371
| | | | | | | | | | | | | This patch adds initial set of files to bring up STM32L476G-Eval board. BUG=none BRANCH=tot TEST=Tested console. make buildall && make tests Change-Id: I0c0f73f31e84099746fced4214c5ed7f45468cef Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340100 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* STM32: Add dma_select_channelDaisuke Nojiri2016-04-254-0/+38
| | | | | | | | | | | | | | | dma_select_channel selects which stream (peripheral) to be used on a specific channel. Some STM32 chips simply logically OR requests, thus do not require this selection. BUG=none BRANCH=tot TEST=make buildall && make tests. Verified on stm32l476g-eval. Change-Id: I7b64b78bdec80658992f58cb4c94ade972a1081c Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/340107 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* CR50: add support for RSA key generationnagendra modadugu2016-04-204-2/+489
| | | | | | | | | | | | | | | | | Prime generation uses a sieve to amortize division with small primes. Otherwise this a standard Miller-Rabin implementation. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I9f84d1f9c911f6146e4bd80296f75157a191552d Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/335222 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* CR50: add support for P256-ECIES (hybrid encryption)nagendra modadugu2016-04-195-0/+207
| | | | | | | | | | | | | | | | | | Add support for P256 based hybrid encryption, and corresponding tests. Where hybrid encryption is: P256 based DH + AES128 + HMAC-SHA256. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 CQ-DEPEND=CL:336091,CL:339561 TEST=ECIES tests in test/tpm/tpmtest.py pass Change-Id: Ie091e278df72185a6896af0e498925e56404f87e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/337340 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* CR50: remove DCRYPTO_p256_points_mul, add DCRYPTO_p256_point_mulnagendra modadugu2016-04-192-41/+10
| | | | | | | | | | | | | | | | | | | points_mul (variable time) is only necessary for ECDSA verification, and is not required as part of the public dcrypto API. Replaced wih (constant time) point_mul, and add corresponding parameter checks to the tpm2 interface call _cpri__EccPointMultiply. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm/tpmtest.py pass Change-Id: I4ec885c147755e8a645c51b9a461b81c3a3b310f Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/338851 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* CR50: add support for RSA key "testing"nagendra modadugu2016-04-194-4/+294
| | | | | | | | | | | | | | | | | | | | | | Implement _cpri__TestKeyRSA, which computes the modulus and private exponent given a pair of primes, or computes the second prime and private exponent given the modulus and one prime. The _cpri__TestKeyRSA call is used to determine whether the components of an RSA key match each other. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm/tpmtest.py pass Change-Id: I2c68d844f4bab207588cbda5c962b09078519a1a Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/330466 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* CR50: move AES CTR implementation to dcryptonagendra modadugu2016-04-192-0/+36
| | | | | | | | | | | | | | | | AES CTR will be necessary to implement hybrid encryption and hence needs to be a part of the dcrypto library. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests in test/tpm/tpmtest.py pass Change-Id: I5dffe5d3a15748614db36aebdbcd50bde31bfdb2 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/339561 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* snoball: Add support for proto 0.9 boardShawn Nematbakhsh2016-04-192-2/+13
| | | | | | | | | | | | | | | | This board uses a different stm32f0 MCU and has significant architectural changes. BUG=chrome-os-partner:50549 BRANCH=None TEST=`make buildall -j`, verify snoball boots to console Change-Id: I842a3efc5e179b33bbf0441e8d4ea07fa006e3fe Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329439 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: shi: Remove excessively verbose printsShawn Nematbakhsh2016-04-192-14/+18
| | | | | | | | | | | | | | | | | Remove verbose prints (most of which are printed in ISRs) by default to eliminate SHI console spam. BUG=chrome-os-partner:52372 BRANCH=None TEST=Verify console isn't spammy while SHI is in use on kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0dbd43e01f37980bc0e9d14fa6349a7ecb8c6f47 Reviewed-on: https://chromium-review.googlesource.com/339493 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: shi: Remove support for V2 host protocolShawn Nematbakhsh2016-04-191-168/+4
| | | | | | | | | | | | | BUG=chrome-os-partner:52372 BRANCH=None TEST=Verify V3 host command interface is still functional. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I75e684f3fbce764965ddac47b8314ed298086d74 Reviewed-on: https://chromium-review.googlesource.com/339472 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: shi: Don't enable GPIO_SHI_CS_L GPIO interrupt until S0Shawn Nematbakhsh2016-04-191-5/+26
| | | | | | | | | | | | | | | | | | Prior to going to S0, GPIO_SHI_CS_L may be low, which can cause glitches in the SHI HW unit. Enable the GPIO interrupt in S0, and disable it when leaving S0. BUG=chrome-os-partner:52222,chrome-os-partner:52217 BRANCH=None TEST=Manual on kevin. Verify 'ectool version' succeeds with subsequent kernel / ectool patches. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie3494122c2486429d3f648ab9220daf5dd34f812 Reviewed-on: https://chromium-review.googlesource.com/338857 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Deferred: Remove hard coded number of deferredsAnton Staaf2016-04-198-24/+0
| | | | | | | | | | | | | | | | | | | | | | | | Previously the maximum number of deferred routines was specified by the the default maximum number of deferred routines you had to override this, and if you wanted fewer, you still payed the price of having the defer_until array statically allocated to be the maximum size. This change removes that define and instead creates the RAM state of the deferred routine (the time to wait until to call the deferred) when the deferred is declared. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j manually test on discovery-stm32f072 Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc Reviewed-on: https://chromium-review.googlesource.com/335597 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip: it83xx: add USBPD moduleDino Li2016-04-185-6/+143
| | | | | | | | | | | | | | | | | | | Add USBPD module for it8320 emulation board BRANCH=none BUG=none TEST=manual plug zinger adapter, connect uart console and type commands: pd 1 dev [20|12|5] pd 1 charger pd 1 swap power and check PD states Change-Id: I9ca1822deeb4b4dce1279a09490ed4175890cf3a Signed-off-by: Leon-Lee <leon.lee@ite.com.tw> Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/326230 Reviewed-by: Shawn N <shawnn@chromium.org>
* Deferred: Use deferred_data instead of function pointerAnton Staaf2016-04-189-28/+30
| | | | | | | | | | | | | | | | | | | | | Previously calls to hook_call_deferred were passed the function to call, which was then looked up in the .rodata.deferred section with a linear search. This linear search can be replaced with a subtract by passing the pointer to the deferred_data object created when DECLARE_DEFERRED was invoked. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None CQ-DEPEND=CL:*255812 TEST=make buildall -j Change-Id: I951dd1541302875b102dd086154cf05591694440 Reviewed-on: https://chromium-review.googlesource.com/334315 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: fix usb console LF handlingVadim Bendebury2016-04-181-13/+9
| | | | | | | | | | | | | | | | | | | | | | | It was observed that when connecting to the CR50 console over USB, there the line feed (LF) characters are not supplemented by carriage return (CR), which causes weird console output. Detailed examination has shown that uart_putc() does not do the right thing itself and also bypasses __tx_char() used by uart_puts(), which does the right thing. The simplest solution is to have uart_putc() re-use all the smarts of uart_puts(). BRANCH=none BUG=none TEST=verified that usb console output does not suffer from the "lost CR" syndrome any more. Change-Id: I2a1f84b2524c41eb6e84186141b0b9ac55e87ee0 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339217 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Cr50: Add DIO_PULL_UP and DIO_PULL_DOWN flagsBill Richardson2016-04-152-8/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In board/*/gpio.inc, we can specify pullups and pulldowns on pads connected to GPIOs, like so: GPIO(SOME_BUTTON, PIN(0,0), GPIO_INPUT | GPIO_PULL_UP) This adds flags to do the same thing for pads that connect to internal periperals: PINMUX(FUNC(UART0_RX), A1, DIO_PULL_UP) BUG=chrome-os-partner:51410 BRANCH=none TEST=make buildall; manual test on Cr50 I added these flags to the gpio.inc file and tested the result: PINMUX(FUNC(I2C0_SCL), B0, DIO_INPUT | DIO_PULL_UP) PINMUX(FUNC(I2C0_SDA), B1, DIO_INPUT | DIO_PULL_DOWN) The "pinmux" console command showed that the new flags took effect: Before: 400600a0: DIOB0 0 IN 400600a8: DIOB1 0 IN After: 400600a0: DIOB0 0 IN PU 400600a8: DIOB1 0 IN PD Change-Id: I1d212331431ef67b2f1bcece8729d092b9ad5ba8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339254 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* cr50: enable AP and EC UART in CCD MODEMary Ruthven2016-04-152-21/+29
| | | | | | | | | | | | | | | | | When the debug cable is plugged in enable the EC and AP UART output. Disable the output when the cable is disconnected so servo can use the UARTs. BUG=chrome-os-partner:52322 BRANCH=none TEST=Verify commands can be sent to the EC UART through usb when suzy q is connected. Verify servo can interact with the EC UART when suzy q is not connected. Change-Id: I2ce0e9da464b24e295e732aa638bfc32323cc72d Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338858 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* amenia: enable BMM150 compassKevin K Wong2016-04-151-0/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=accelinfo return data from compass Change-Id: Ib64ca8a06071744294c0bc88bbb18f1445d71780 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331656 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Update the USB VID:PID:subclass constantsBill Richardson2016-04-153-17/+5
| | | | | | | | | | | | | | | | | | | | | | | The device-specific subclass used for Non-HC firmware updates is in the spreadsheet now, so we can rename the macros to be "official". BUG=chrome-os-partner:49962 BRANCH=none TEST=make buildall; test on cr50 make BOARD=cr50 (plus whatever signing magic works for you) make -C extra/usb_updater ./extra/usb_updater/usb_updater build/cr50/ec.bin (sudo if needed) Note that you may need to rebuild ec.bin in order to see any difference after the update. If the A & B images are identical, the RO bootloader always picks A. Change-Id: I385ce89a9abe2059d52da2d82a0b92b9b3e3c93f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339220 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chip: it83xx: Add i2c channel d/e/f functionEli Hsu2016-04-144-95/+637
| | | | | | | | | | | | | | | | | | | | | | | [board] 1. Add i2c channel d/e/f setting. 2. Add i2c channel d/e/f pin definition. [chip] 3. change i2c port number. 4. Add i2c channel d/e/f function. 5. Add i2c channel d/e/f interrupt. 6. Add i2c channel d/e/f registers. Signed-off-by: Eli Hsu <eli.hsu@ite.com.tw> BRANCH=none BUG=none TEST=Test by console command "i2cscan","i2cxfer" and "battery" Change-Id: I928f333ec129924795c3b594ad6a2bfdd0b3d220 Reviewed-on: https://chromium-review.googlesource.com/336560 Commit-Ready: Eli Hsu <eli.hsu@ite.com.tw> Tested-by: Eli Hsu <eli.hsu@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: add support for HKDF (RFC 5869)nagendra modadugu2016-04-143-0/+88
| | | | | | | | | | | | | | | | | Add support for SHA256 based HKDF key derivation as specified in RFC 5869. This change includes test vectors from the RFC. BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=tests under test/tpm2 pass Change-Id: I7d0e4e92775b74c41643f45587fc08f56d8916aa Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/336091 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* cr50: Detect debug cable and switch the PHYMary Ruthven2016-04-134-4/+89
| | | | | | | | | | | | | | | | | This adds support for RD Detection on cr50. It can be used to detect a debug device and signal the controller to switch from the AP PHY to the to CCD PHY. When RDCC1 and 2 no longer detect the debug device, then the controller switches back to using the USB to AP PHY. BUG=chrome-os-partner:50700 BRANCH=none TEST=change the value on RDCC1 and RDCC1 and check that the usb controller connects to the right PHY. Change-Id: Ice01a45a31fe1932945f89df2e3b851f4d287a17 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338454 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* chip: it83xx: disable sleep while fan control loop ongoingDino Li2016-04-131-6/+10
| | | | | | | | | | | | | | | | | This change is required for support 'CONFIG_LOW_POWER_S0'. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. fanset 5555, EC enter doze mode only and fan control is functional. 2. fanset 0, EC will enter deep doze mode properly. Change-Id: I3780b12ef54713258769616bfed0155c865c0725 Reviewed-on: https://chromium-review.googlesource.com/338750 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* apollolake: ignore PLTRST# from SOC unless RSMRST# to soc is deassertedKevin K Wong2016-04-131-0/+8
| | | | | | | | | | | | | | | signals output from SOC should be considered invalid until EC has de-asserted RSMRST# to SOC. BUG=none BRANCH=none TEST=make buildall, able to boot to OS on amenia Change-Id: I15aee314263e3f1b41c45fb719249cd2579a6bc7 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331654 Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: default to CCD PHYMary Ruthven2016-04-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | While kevin is still in development default to connecting to the CCD PHY instead of the AP PHY. This will automatically enable CCD instead of having to rely on things working to detect the debug accessory and switch to the proper PHY. We also disable the TX lines to the AP and EC, in case servo is connected. To turn them on manually, use these console commands: rw 0x40060040 74 rw 0x400600c8 78 pinmux gpiocfg BUG=chrome-os-partner:50700,chrome-os-partner:52281,http://crosbug.com/p/52322 BRANCH=none TEST=hook up suzy q to kevin. Run 'lsusb -vd 18d1:5014' and check that a device appears. Change-Id: Ic2802430680adc6186982022c995ee6f452b45fd Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338680 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Trybot-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Enable RW FW updates over USBBill Richardson2016-04-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | This enables the Cr50 to accept RW firmware updates over USB. BUG=chrome-os-partner:50707, chrome-os-partner:50712 BRANCH=none TEST=make buildall; test on Cr50 Build and run the extra/usb_updater utility. Watch the console, and observe that the Cr50 updates and reboots into the new image correctly. Note that you'll have to rebuild the ec.bin image in order for the update to take effect. Just reflashing the same image doesn't cause the bootloader to change its selection. All the previously existing endpoints continue to function normally. Change-Id: I7bd22eae803c2ceeb14a767c06d3d5c9f1ac7c7a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338089 Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Add userspace tool to update RW FW over USBBill Richardson2016-04-121-0/+4
| | | | | | | | | | | | | | | | | | | | | | | This adds a standalone linux utility to deliver RW firmware updates to the Cr50 over USB. It prepares update blocks required by the firmware upgrader, and then fragments and transfers the blocks though the USB channel. The blocks are reassembled on the target and passed to the upgrade module for integrity verification and programming. BUG=chrome-os-partner:50712 BRANCH=none TEST=make buildall; test on Cr50 as follows: sudo extra/usb_updater/usb_updater build/cr50/ec.bin The Cr50 doesn't yet accept firmware updates that way, so there's no functionality to test just yet. Change-Id: I1c698fd0c553c936d58ff16a2acaa05ae05bc857 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338088
* Cr50: New usb_upgrade module for RW updatesBill Richardson2016-04-125-0/+445
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This re-factors the existing firmware upgrade facility, which worked as a TPM command extension. The same code processing upgrade blocks prepended by the truncated SHA1 and the load address is now used by both extended TPM command and the USB upgrader. To accommodate USB communications using a smaller message payloads a reassembly layer is introduced which accumulates short USB payloads into a single block which can be passed to the firmware upgrade routine. USB encapsulation adds one 4 byte header at the beginning of the block to hold the total block size. The reassembly layer keeps receiving USB messages, concatenating their payloads until the full block is received. A config option is added to make sure the module is not compiled when not needed. BUG=chrome-os-partner:50707 BRANCH=none TEST=make buildall; test on Cr50 - with the rest of the patches applied it is possible to upgrade firmware using the USB utility on the host.. Change-Id: Ib30b381c4ab196ea9d352f3c6b8f46dc23ddd599 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/338087
* chip: it83xx: disable USB module's clock at defaultDino Li2016-04-111-1/+2
| | | | | | | | | | | | | | | | | The GPIOH.5/6 are reserved for USB module and the clock is disabled before configuring it. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Clock is disabled at default. Change-Id: If679ab3de13019f19a936b9a412b20973fb8989f Reviewed-on: https://chromium-review.googlesource.com/338066 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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