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* chip/stm32/clock-stm32l4: Fixed clock cmd documentationJes B. Klinke2023-02-051-2/+2
| | | | | | | | | | | | | | | | | | Looking at the code, it is apparent that the "pll" parameter to the "clock" console command is valid whether STM32_HSE_CLOCK is defined or not (though the effect may be slightly different). This CL updates the documentation to list "pll" as a valid option also when STM32_HSE_CLOCK is not defined. BUG=none TEST=make BOARD=hyperdebug Change-Id: I7da89c15b44fbc3dad2a5fe129b0e361d7f50714 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4216263 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org> Tested-by: Jes Klinke <jbk@chromium.org>
* chip/stm32/dfu_bootmanager_main: Add memory barrierJes B. Klinke2023-02-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | ARM Cortex documentation calls for an ISB instruction to be executed immediately after modifying the stack pointer, see for instance: https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/programmers-model/core-registers It would seem that instruction prefetch will "anticipate" stack pointer movements by counting the push and pop instructions, and that the prefetch queue needs to be cleared if the stack pointer is manually changed. Our particular code executes does not use the stack pointer, but executes a register jump, which I assume will also clear the prefetch queue. So in all likelihood, the barrier instructions is not required here, but we could as well add it, as the documentation calls for it. BUG=none TEST=make BOARD=hyperdebug, observe DFU upgrading still works Change-Id: I2a0609670b3554a39057b429fc2e0cd1201d185c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4216262 Reviewed-by: Brian Nemec <bnemec@google.com> Commit-Queue: Jes Klinke <jbk@chromium.org> Tested-by: Jes Klinke <jbk@chromium.org>
* ec: Use chromite isort configJeremy Bettis2023-02-034-0/+4
| | | | | | | | | | | | | | | | | | Remove the .isort.cfg from platform/ec and use the one from chromite instead. This should be compatible with cros format. BRANCH=None BUG=b:267757300 TEST=Ran firmware_builder.py Change-Id: Ice4955b6995bd1f9380e97f58e89efb7c1e8aeb1 Signed-off-by: Jeremy Bettis <jbettis@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4221928 Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* chip/stm32: Modification to DFU for STM32L5Jes B. Klinke2023-01-253-18/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32L5 series behaves the same as STM32L4 to a large degree, so this CL adds code to enable RTC clock on L5 using the same register bits as on L4. The "backup registers" however, sit in a new "Tamper" component on L5, and not in the RTC component as on L4. This CL adds register declarations for the TAMP component. Lastly, jumping to the ROM bootloader with C function pointer call, as was done in jump_to_dfu(), does not work on the STM32L5 ROM bootloader (at least not on my Nucleo-X552EZ board.) The flaw seems to be that an ARM vector table contains a reset vector, and separately contains an initial value for the stack register. The previous code made no attempt at setting the stack point as the bootloader expected, and depending on how the EC code (and the STM ROM bootloader) is compiled, this may or may not work. This CL adds assembly code to set the stack pointer to the value given in the ROM header, before performing the jump. BUG=b:192262089 TEST=Upgrade firmware on STM32L5 based Nucleo board using dfu-util Change-Id: I2a871f0eaf9ea9f4c27c75ccb472cd4ff9616524 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4190164 Reviewed-by: Brian Nemec <bnemec@google.com> Tested-by: Jes Klinke <jbk@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org>
* chip/stm32: Correction to EXTI register declarations for STM32L5Jes B. Klinke2023-01-243-13/+60
| | | | | | | | | | | | | | | | | | Originally, I copied STM32L4 declarations for STM32L5, making adjustments for base addresses, and other obvious differences. It turns out that the external interrupt controller has som subtle changes to its registers. Most notably the EXTICR registers (used for selection which external pin is routed to which of the 16 edge detection "engines") have been moved from the SYSCFG component into EXTI component. BUG=b:192262089 TEST=Observe edge detection working on HyperDebug (based on STM32L5) Change-Id: I4ad4f2559c60bef73a29812ebac1316cfa389a3e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4166670 Commit-Queue: Jes Klinke <jbk@chromium.org> Tested-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mchp: Remove undefined behavior in espi msvw handlersDustin L. Howett2023-01-231-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code in espi_msvw[12]_interrupt relies on undefined behavior today. __builtin_ctz is specified as returning values in the range [0, 31], but we are checking for 32. This behavior may be unexpected compared to the CTZ/CLZ instruction on ARM, which use the value 32 to indicate that there are no ones in the provided input. GCC 11+ optimizes the two loops below into infinite loops, as it can see that the condition will never be met. After this change, the disassembly of espi_mswv1_interrupt can be confirmed to contain an exit behind a branch. ... // r4 is loaded with girq24_result and has bits successively cleared 1a: b90c cbnz r4, 20 <espi_mswv1_interrupt+0x20> 1c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} 20: fa94 f5a4 rbit r5, r4 ... BUG=None BRANCH=main TEST=Examined the disassembly for espi_msvw[12]_interrupt; see above Change-Id: I68a5c753233a17b6b0fb61a31f1eeccf78c00aba Signed-off-by: Dustin L. Howett <dustin@howett.net> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4114450 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org>
* chip/stm32: Fix copy/paste errorJes B. Klinke2023-01-181-2/+2
| | | | | | | | | | | | | | | | Existing code for extracting chip independent EC pin flags from stm32 registers suffered from a copy/paste error, meaning that it could never recognize interrupt triggering on a falling edge. BUG=none TEST=make BOARD=hyperdebug Change-Id: I4c752b092bfd3c6ea70192006a9453e0b81b0d9b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4166669 Tested-by: Jes Klinke <jbk@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org>
* tree: Replace "unsigned" with "unsigned int"Andrea Grandi2023-01-0412-58/+60
| | | | | | | | | | | | | | | | | Fix checkpatch error: > Prefer 'unsigned int' to bare use of 'unsigned' BUG=b:262047616 TEST=./util/compare_build.sh -b all -j 120 => MATCH BRANCH=none Change-Id: Ibf82332a1e1ea0a0a03d3993336e24883e495e05 Signed-off-by: Andrea Grandi <agrandi@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4126483 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* npcx9: SHA256: Fix the code definition of enum ncl_statusJun Lin2022-12-191-3/+3
| | | | | | | | | | | | | | | | | | | The coding of the enum ncl_status is not correctly defined in the SHA256 chip driver. This CL fixed it to meet the actual return code from the SHA ROM API. BRANCH=none BUG=b:155771688 TEST=manually dump and check the return value from SHA ROM API. Change-Id: Iee3ec5c7102ddc93f7afda6523c59393a5a0047a Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4113813 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
* chip/stm32: Add register declarations for OctoSPIJes B. Klinke2022-12-091-0/+291
| | | | | | | | | | | | | | | | The STM32L5 series of chips have a SPI controller capable of using up to eight data lines for fast transfers, primarily with SPI flash chips. This CL adds declarations of register addresses and bits. BUG=b:192262089 TEST=Flashed OpenTitan FPGA via HyperDebug OctoSPI Change-Id: I33d16ba493756cf338353a5f0952be97070720d6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4087327 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Tested-by: Jes Klinke <jbk@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org>
* chips/stm32/usb_spi: Allow boards to handle non-standard SPI bussesJes B. Klinke2022-12-092-1/+27
| | | | | | | | | | | | | | | | | | The STM32L5 series has a special "OctoSPI" controller, which differs from the standard spi controllers in capabilities and means of programming. Rather than adding drivers for OctoSPI to the common EC code, this change allows special-purpose drivers for HyperDebug to be implemented in its board directory. BUG=b:192262089 TEST=Observed HyperDebug forwarding to OctoSPI controller Change-Id: Ia31eefcb53b08cc23aa0f14a8899bc227a88ea0c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077429 Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Tested-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jes Klinke <jbk@chromium.org>
* chips/stm32/usb_spi: Forwarding to multiple spi devicesJes B. Klinke2022-12-092-8/+30
| | | | | | | | | | | | | | | | For devices similar to Servo Micro, in case of multiple entries in spi_devices, this change allows the USB host to request which device its transaction requests are to be forwarded to. BUG=b:192262089 TEST=HyperDebug board forwards to two SPI busses Change-Id: Ic94e66a8d7f5502c3016a26a1beb24236b3c4893 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077428 Commit-Queue: Jes Klinke <jbk@chromium.org> Tested-by: Jes Klinke <jbk@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec: Support logging system boot time infoRajesh Kumar2022-12-073-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL add support logging system boot time and hostcommand to get boot time info. EC logs elapsed time (in micro second) info since boot for different signal events,that can be used to calculate system boot time in cold boot and warm boot scenarios. Below are the events when EC logs time info ARAIL EC turns on A-RAIL RSMRST EC releases RSMRST# ESPIRST ESPIRST received PLTRST_LOW PLTRST# asserted PLTRST_HIGH PLTRST# deasserted EC_CUR_TIME EC current time cnt increments on every warm reboot and reset to 0 on cold reboot BUG=b:249163956 BRANCH=none TEST='ectool boottime' AP console command is used to fetch data 'reboot' on AP console to trigger warm reboot 'apshutdown' on EC console to trigger cold reboot Signed-off-by: Rajesh Kumar <rajesh3.kumar@intel.com> Change-Id: I47abe3f8a0b7ab43f2af11bf8387c006ba383020 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4081566 Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Tested-by: Li-Yu Yu <aaronyu@google.com> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* Revert "ec: Support logging system boot time info"Piotr Pawliczek2022-12-033-17/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit c8325ba18b9f4d5b1f3f3bc739e83d8f591308cf. Reason for revert: broke at least 9 cq builds (https://ci.chromium.org/ui/p/chromeos/builders/cq/cq-orchestrator/b8795833246203447793/overview) Original change's description: > ec: Support logging system boot time info > > This CL add support logging system boot time and hostcommand to get > boot time info. > EC logs elapsed time (in micro second) info since boot for different > signal events,that can be used to calculate system boot time in cold > boot and warm boot scenarios. > > Below are the events when EC logs time info > > ARAIL EC turns on A-RAIL > RSMRST EC releases RSMRST# > ESPIRST ESPIRST received > PLTRST_LOW PLTRST# asserted > PLTRST_HIGH PLTRST# deasserted > EC_CUR_TIME EC current time > cnt increments on every warm reboot and reset to 0 on > cold reboot > > BUG=b:249163956 > BRANCH=none > TEST='ectool boottime' AP console command is used to fetch data > 'reboot' on AP console to trigger warm reboot > 'apshutdown' on EC console to trigger cold reboot > > Signed-off-by: Rajesh Kumar <rajesh3.kumar@intel.com> > Change-Id: I15fedbde252e0452270ef0e3fd4391bf624169f1 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3794612 > Reviewed-by: Boris Mittelberg <bmbm@google.com> > Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Bug: b:249163956 Change-Id: Ie83026c4a3a38c3dd24522901233f06e03430a54 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077335 Reviewed-by: Jonathon Murphy <jpmurphy@google.com> Commit-Queue: Piotr Pawliczek <pawliczek@chromium.org> Tested-by: Piotr Pawliczek <pawliczek@chromium.org>
* ec: Support logging system boot time infoRajesh Kumar2022-12-023-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL add support logging system boot time and hostcommand to get boot time info. EC logs elapsed time (in micro second) info since boot for different signal events,that can be used to calculate system boot time in cold boot and warm boot scenarios. Below are the events when EC logs time info ARAIL EC turns on A-RAIL RSMRST EC releases RSMRST# ESPIRST ESPIRST received PLTRST_LOW PLTRST# asserted PLTRST_HIGH PLTRST# deasserted EC_CUR_TIME EC current time cnt increments on every warm reboot and reset to 0 on cold reboot BUG=b:249163956 BRANCH=none TEST='ectool boottime' AP console command is used to fetch data 'reboot' on AP console to trigger warm reboot 'apshutdown' on EC console to trigger cold reboot Signed-off-by: Rajesh Kumar <rajesh3.kumar@intel.com> Change-Id: I15fedbde252e0452270ef0e3fd4391bf624169f1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3794612 Reviewed-by: Boris Mittelberg <bmbm@google.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* board: Sort header filesJeremy Bettis2022-12-011-1/+3
| | | | | | | | | | | | | | | | | | | | Sort all includes in board with the clang-format rules used by the zephyr project. BRANCH=None BUG=b:247100970 TEST=zmake build -a TEST=./twister --clobber -v -i TEST=make -j72 buildall_only runtests TEST=zmake compare-builds -a Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I6ad72b167cbb768a64c338fa633eb4bf5a401897 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4060360 Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
* chip: Sort header filesJeremy Bettis2022-11-29140-321/+313
| | | | | | | | | | | | | | | | | | | | Sort all includes in chip with the clang-format rules used by the zephyr project. BRANCH=None BUG=b:247100970 TEST=zmake build -a TEST=./twister --clobber -v -i TEST=make -j72 buildall_only runtests TEST=zmake compare-builds -a Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I13454e38fa3766aa0ba26a058075f51965b8462e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4053346 Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* ec: IWYU Add missing includesJeremy Bettis2022-11-243-1/+5
| | | | | | | | | | | | | | | | | | | | | | | Add "chip/stm32/usb_hw.h" for usb_uint Add <stddef.h> for size_t Switch from board.h to config.h BRANCH=None BUG=b:247100970 TEST=zmake build -a TEST=./twister --clobber -v -i TEST=make -j72 buildall_only runtests TEST=zmake compare-builds Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I8d6c7cb89cd54812b90afd9ec06d81f8122fbdc7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4053345 Reviewed-by: Tomasz Michalec <tmichalec@google.com> Commit-Queue: Tomasz Michalec <tmichalec@google.com> Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* npcx9: fix SHA256 ROM API table addressJun Lin2022-11-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | It was found that the hardware SHA256 accelerator is broken. This is caused by the table address of SHA ROM API changed from 0x100 to 0x13C since the ES2 chip. This CL fixed the issues described above. BRANCH=none BUG=b:155771688 TEST=burn the same RW image; #define/#undef CONFIG_SHA256_HW_ACCELERATE; verify the RW hash value is the same in the console message. TEST=with the test CL:2455022, move test patterns in test/sha256.c to board/npcx9_evb/test_sha256.c; pass all test patterns. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I12ce8531a925f02474f66d90bf7efd950b3eeba3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4033807 Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Boris Mittelberg <bmbm@google.com> Tested-by: CH Lin <chlin56@nuvoton.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* chip/ish: fix system shutdown in D0i3Li Feng2022-11-154-40/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | ISH should set PMC LTR(Latency Tolerance Reporting) for DMA operation. Without doing this, we observed system shutdown during D0i3. This CL set LTR to 2ms before DMA operation and set LTR to a large number after DMA operation is completed to enable SOC to go into the lowest possible power state. BUG=b:234136500 BRANCH=none TEST=on Nirwen platform, ISH enter D0i3 host loading case, and also stitching to coreboot case; S0i3 is hit and no shutdown. Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Signed-off-by: Li Feng <li1.feng@intel.com> Change-Id: Ib0fe907470774998dda29a40197d6c18ad6372f1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4003320 Code-Coverage: Haribalaraman Ramasubramanian <haribalaraman.r@intel.corp-partner.google.com> Reviewed-by: Kyoung Kim <kyoung.il.kim@gmail.com> Reviewed-by: Haribalaraman Ramasubramanian <haribalaraman.r@intel.corp-partner.google.com> Commit-Queue: Kangheui Won <khwon@chromium.org> Tested-by: Haribalaraman Ramasubramanian <haribalaraman.r@intel.corp-partner.google.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
* tree: Remove CONFIG_STM_HWTIMER32Tom Hughes2022-11-111-3/+1
| | | | | | | | | | | | | | | | | | | | | CONFIG_STM_HWTIMER32 was used to choose between a 32-bit timer and 16-bit timer. The 16-bit timer code was removed in https://crrev.com/c/3388064, so we no longer need this config. Command used: git grep --name-only CONFIG_STM_HWTIMER |\ xargs sed -i '/CONFIG_STM_HWTIMER32/d' BRANCH=none BUG=b:214423235 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I89da8915cd5a467975cd8f90e734ea2b11f18cb3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3388065 Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Reviewed-by: Patryk Duda <patrykd@google.com>
* tree: Remove stm32/hwtimer.cTom Hughes2022-11-102-483/+13
| | | | | | | | | | | | | | | | | | | | | | | | stm32/hwtimer.c simulates a 32-bit timer with two 16-bit timers. The only boards still using this file were "discovery" and "twinkie". "twinkie" is an STM32F072B, which has support for 32-bit timers (TIM2 and TIM3). See Section 18 "General-purpose Timers": https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1-stm32f0x2-stm32f0x8-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf. "discovery" is an STM32L152RC, which is a "Category 3" product that has the 32-bit timer TIM5. See Section 17 "General-purpose Timers" and "Table 3. STM32L15xxx product categories": https://www.st.com/resource/en/reference_manual/cd00240193-stm32l100xx-stm32l151xx-stm32l152xx-and-stm32l162xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf. BRANCH=none BUG=b:214423235 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I41b3a54bbbbce5d0dfee178b6fa87ff492646ce1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3388064 Reviewed-by: Patryk Duda <patrykd@google.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* npcx: avoid invalid VW signal indexBoris Mittelberg2022-11-101-0/+3
| | | | | | | | | | | | | | Prevent possibility of array[-1] access BUG=b:64477774 BRANCH=none TEST=none Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: I130b7d3872f857dc6e8dabca3f07d0d919b7ce64 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4018487 Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* chip/mchp: Fix clang compilation errorTom Hughes2022-11-071-1/+6
| | | | | | | | | | | | | | | | | | | | | When building with clang, it fails with: chip/mchp/lfw/ec_lfw.c:310:2: error: non-ASM statement in naked function is not supported uart_puts("EXCEPTION!\nTriggering watchdog reset\n"); ^ chip/mchp/lfw/ec_lfw.h:25:41: note: attribute is here void fault_handler(void) __attribute__((naked)); ^ BRANCH=none BUG=b:172020503 TEST=./util/build_with_clang.py Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: If998119e285b3a068623909a373f3ebaf426b2e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3977110 Reviewed-by: Eric Yilun Lin <yllin@google.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* chip/mchp/lfw: Discard ARM.* sectionsfactory-brya-15231.B-mainTom Hughes2022-11-042-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Linking with clang/lld fails since it tries to include .ARM.exidx in the VECTOR region: ld.lld: error: section '.ARM.exidx' will not fit in region 'VECTOR': overflowed by 328 bytes We don't need the exception index table or exception table (see https://crrev.com/c/3857943). This matches the behavior in our other linker scripts: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/core/cortex-m/ec.lds.S;l=745;drc=84b2904dead700e10073080c54e69ea162d8a7c5 This change does not affect the gcc/ld build (identical output before and after). BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I65df11f3ab0c439ea3d4ce2805afaac942b22a0e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3989667 Reviewed-by: Diana Z <dzigterman@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* chip/ish: implement full config in pm_initLi Feng2022-11-042-2/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Both ISH shim loader and main firmware have PM initialization. Main firmware doesn't do a full configuration because some are done in shim loader. This is working fine if we use host loading main firmware scheme. We observed problem in IPAPG if stitching main firmware to coreboot and skip shim loader. This CL modifies pm_init to fully configure PM. So ISH main firmware functions correctly in both loading methods. BUG=b:234136500 BRANCH=none TEST=make buildall TEST=on ADL-P RVP, ISH enter IPAPG state in host loading case, and also stitching to coreboot case. Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Signed-off-by: Li Feng <li1.feng@intel.com> Change-Id: I603e2f107fdce672ac12bac9d848820f58474910 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3985606 Reviewed-by: Kyoung Kim <kyoung.il.kim@gmail.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com> Commit-Queue: Reka Norman <rekanorman@chromium.org>
* chip/mchp/lfw: Specify region for paddingTom Hughes2022-10-312-2/+2
| | | | | | | | | | | | | | | | | | | | | Linking with clang/lld fails since it assumes the region .fill should use is VECTOR: ld.lld: error: section '.fill' will not fit in region 'VECTOR': overflowed by 328 bytes This change does not affect the gcc/ld build (identical output before and after). BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ieeff37fc13befe495dbc567b4be363da07a75c3a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3989666 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* npcx: flash: FLASH_BANK_SIZE shouldn't depend on FLASH_ERASE_SIZEJun Lin2022-10-281-1/+5
| | | | | | | | | | | | | | | | | | | The flash bank definition is used to check the protection block. There is no reason to define it following the flash erase size setting. This CL sets the smallest flash bank size to 64KB, which is 1/8 of 512KB or 1/16 of 1MB flash. BRANCH=none BUG=b:254877499 TEST="BOARD=npcx9_evb make", use console command flashwp/flashinfo to check the flash protection. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I9dfdc4083e2aa0a198ff882ecaa7794bb6ac5ad5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3980704 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: CH Lin <chlin56@nuvoton.com> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* gpio: npcx: fix incorrect report from gpio_get_flags_by_maskJun Lin2022-10-241-4/+6
| | | | | | | | | | | | | | | | | | | | | | The current driver reports the configured level regardless of the GPIO's direction (input/output). It should report it only when the pin in question is an output. Also, it should read the level from the PxDOUT register instead of the PXDIN register. BRANCH=none BUG=b:254739925 TEST=build npcx9_evb with CONFIG_GPIO_GET_EXTENDED and CONFIG_CMD_GPIO_EXTENDED defined, check the report form `gpioget` console command is correct. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I1f40bb757c1a012697374b294b57934608d5e293 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3967955 Tested-by: CH Lin <chlin56@nuvoton.corp-partner.google.com> Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Andrew McRae <amcrae@google.com> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* tree: Enable warning for fallthrough in switch statementsTom Hughes2022-10-192-0/+2
| | | | | | | | | | | | | | | | | | | | | | | The EC code has generally been good about adding comments about intentional fallthrough in switch statements, but there were a few cases without comments (e.g., https://crrev.com/c/3949622). Enabling -Wimplicit-fallthrough generates a compiler warning if the fallthrough is not annotated with __attribute__((fallthrough)). For convenience, we add a "__fallthrough" macro for this attribute. See https://clang.llvm.org/docs/AttributeReference.html#fallthrough and https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html. BRANCH=none BUG=b:253644823 TEST=make buildall LOW_COVERAGE_REASON=legacy code Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I9f4d6049f4507a25ce706675d159b70e28b4b825 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3957420 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* it83xx: espi: reset pltrst# virtual wire signal during espi resetDino Li2022-10-172-0/+5
| | | | | | | | | | | | | | | | | | | | EC software reset doesn't reset pltrst# by default. This change was made to reset pltrst# during espi reset. So Ampton won't get stuck after watchdog reset. BRANCH=octopus BUG=b:235443631 TEST=Ampton won't get stuck after watchdog reset. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ice77a902185046757d6b7bc70edee53eb81e64dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3959261 Commit-Queue: Henry Sun <henrysun@google.com> Reviewed-by: luluboy luluboys <luluboy5208@gmail.com> Reviewed-by: Diana Z <dzigterman@chromium.org> Tested-by: Luluboy Jian <luluboy_jian@asus.corp-partner.google.com> Tested-by: luluboy luluboys <luluboy5208@gmail.com> Reviewed-by: Luluboy Jian <luluboy_jian@asus.corp-partner.google.com>
* tree: Remove chip/mec1322 and referencesTom Hughes2022-10-1728-5315/+0
| | | | | | | | | | | | | There are no longer any boards that use chip/mec1322. BRANCH=none BUG=none TEST=CQ passes Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ie03535c6c62c61c86fc2714ec4e7bc48eb0e2d79 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3953934 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* chip/mchp: Fix return typeTom Hughes2022-10-141-1/+1
| | | | | | | | | | | | | | | | | | | When building with clang it warns: chip/mchp/lpc.c:966:9: error: implicit conversion from enumeration type 'enum ec_error_list' to different enumeration type 'enum ec_status' [-Werror,-Wenum-conversion] return EC_SUCCESS; ~~~~~~ ^~~~~~~~~~ BRANCH=none BUG=b:172020503 TEST=CC=clang make BOARD=reef_mchp Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I680cea90f72d3743ef4b92e13e57e63557cba702 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3953490 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* include/compiler.h: Add generic macro for disabling compiler warningsTom Hughes2022-10-131-7/+3
| | | | | | | | | | | | | | These macros are easier to read and use than the underlying pragmas. BRANCH=none BUG=b:172020503 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I2f67cbb3f83230b7e1a6a4512471bbd2bec0498f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3872552 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* tree: Remove CONFIG_SOFTWARE_PANICTom Hughes2022-10-123-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | It's always enabled in the core/<core>/core_config.h files. The following script demonstrates that it's enabled in all boards: for board in `make print-boards`; do make print-configs board="${board}" | grep -q CONFIG_SOFTWARE_PANIC if [ $? -ne 0 ]; then echo "${board} failed" exit 1 fi done BRANCH=none BUG=none TEST=make buildall Cq-Depend: chromium:3943248 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: If683b244f17b48bedf3699f2b24e83b5ad6e849e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3933255 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* chip/stm32: Remove self-assignmentTom Hughes2022-10-121-2/+2
| | | | | | | | | | | | | | | | | | | When building with clang it warns: chip/stm32/clock-stm32l4.c:400:9: error: explicitly assigning value of variable of type 'uint32_t' (aka 'unsigned int') to itself [-Werror,-Wself-assign] val = val; ~~~ ^ ~~~ BRANCH=none BUG=b:172020503 TEST=CC=clang make BOARD=hyperdebug Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ie4fae7251747d27b96ed08c3ef166fddd5411b9a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3947822 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* ish: add HOSTCMD task checkLi Feng2022-10-081-1/+2
| | | | | | | | | | | | | | | | | | | | | host_packet_receive() is defined when HOSTCMD task is enabled; so add a check of HOSTCMD; otherwise there is build error for board which doesn't enable HOSTCMD task. One of ISH solutions is to provide power management functionalities. It powers on ISH and puts it in deep sleep. HOSTCMD task is disabled in this case to avoid waking up ISH periodically. BUG=b:234136500 BRANCH=none TEST=build tglrvp_ish Signed-off-by: Li Feng <li1.feng@intel.com> Signed-off-by: Guangfu Hu <guangfu.hu@intel.com> Change-Id: I64cd6ad4d292847d477f08708ece4d41b4e94650 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3892628 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Keith Short <keithshort@chromium.org>
* ec: Don't declare forward decls as weakJeremy Bettis2022-10-072-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a function in a header is marked as weak (test_mockable), that tells the linker that it is ok for the symbol to be missing. We never want that. If a function implementation is marked as weak, that tells the linker it is ok to use a non-weak symbol instead of this one. This is what we want when we are trying to override functions. Remove all test_mockables from headers, except for one inline function that I wasn't sure what to do with. BRANCH=None BUG=None TEST=make -j$(nproc) runhosttests buildall && zmake build -a && \ ./twister -v -i --clobber LOW_COVERAGE_REASON=Added stub get_ap_reset_stats() for tests that don't care about that function, and it's always unused. Change-Id: Ic00a897131c93ef134544f26a8e368ce1f78a5de Signed-off-by: Jeremy Bettis <jbettis@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3935720 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Tristan Honscheid <honscheid@google.com> Tested-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Tristan Honscheid <honscheid@google.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* mt_scp: Add support for mt8186 decoderYunfei Dong2022-09-305-0/+58
| | | | | | | | | | | | | | | | | | | | | | 1. Add vdec ipi service interface 2. Add supported capability 3. Add ectasklist for mt8186 lat architecture 4. Separate mt8186 and mt8183 using define 5. Fix venc and mdp build error when add mt8186 driver 6. Fix cros_license_check errors BRANCH=none BUG=b:218771968 TEST=build corsola_scp pass Signed-off-by: kyrie wu <kyrie.wu@mediatek.corp-partner.google.com> Signed-off-by: Mingjia Zhang <mingjia.zhang@mediatek.corp-partner.google.com> Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> Change-Id: I9d458a8c92ee27366ae03c3386d5682f62f5693b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3379786 Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org>
* mt8195/mt_scp: enable av1 decoder driverXiaoyong Lu2022-09-301-1/+1
| | | | | | | | | | | | | | enable av1 decoder driver in mt8195 platform. BUG=b:205889935 TEST= av1/vp9/h264/vp8 fluster test pass Signed-off-by: Xiaoyong Lu <xiaoyong.lu@mediatek.corp-partner.google.com> Change-Id: Ie58827559cb144d7ef63545d3c4ff2bbb70db603 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3585271 Reviewed-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> Tested-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com>
* Update license boilerplate text in source code filesMike Frysinger2022-09-12481-481/+481
| | | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* config: rename HOSTCMD_ESPI_* to HOST_INTERFACE_ESPI_*Michał Barnaś2022-09-096-22/+23
| | | | | | | | | | | | | | | Rename ESPI additional configs to match the name of base config that selects ESPI as HOST_INTERFACE. BUG=b:195416058 BRANCH=main TEST=zmake testall && make buildall Change-Id: I137449a1a58b1ea0d9794ebc0900e1b68413819d Signed-off-by: Michał Barnaś <mb@semihalf.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3291744 Reviewed-by: Sam Hurst <shurst@google.com> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
* stm32f0.h: update number of channels per controllerJosie Nordrum2022-09-062-9/+10
| | | | | | | | | | | | | | | | | Define only channels valid for each chip. Remove reference to channel 7 when setting callbacks for DMA channels 4+. BRANCH=None BUG=b:233240524 TEST=make buildall -j Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: I0258498cc075817b7ee59963482bc6a391853a90 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3656369 Reviewed-by: Bobby Casey <bobbycasey@google.com> Commit-Queue: Josie Nordrum <josienordrum@google.com> Reviewed-by: Craig Hesling <hesling@chromium.org> Tested-by: Josie Nordrum <josienordrum@google.com>
* tree-wide: const-ify argv for console commandsCaveh Jalali2022-09-0145-64/+64
| | | | | | | | | | | | | | | | | | | | | | | This updates the API for console commands from "int cmd(int argc, char **argv)" to "int cmd(int argc, const char **argv)" which is more accurate and in line with common convention. BRANCH=none BUG=b:244387210 TEST="make buildall" passes TEST="zmake build -a" passes TEST="util/compare_build.sh -b all" passes TEST="./twister -v -T zephyr/test" passes Cq-Depend: chrome-internal:4960125 Cq-Depend: chrome-internal:4959932 Change-Id: I57de9f35b85b8f3c7119df36aefb2abf25d2625f Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3863941 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* mtk_scp: Enable I/D-cache for mt8186Allen-kh Cheng2022-08-261-2/+8
| | | | | | | | | | | | | | | | | | | 1. Enable cache mapping on scp boot. 2. Add interrupt disable/enable to prevent preempt when setting cache range. BRANCH=none BUG=b:218771968 TEST=Boot kukui scp and open cam ok make BOARD=corsola_scp -j ALLOW_CONFIG=1 Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> Change-Id: I8d586afc33cba55d388d553dd2a2fc2047089553 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3853765 Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Wei-Shun Chang <weishunc@chromium.org>
* mtk_scp: Enable uart1 for mt8186Allen-kh Cheng2022-08-261-0/+5
| | | | | | | | | | | | | | | | Enable uart1 for mt8186 scp. BRANCH=none BUG=b:218771968 TEST=Boot kukui scp and open cam ok make BOARD=corsola_scp -j ALLOW_CONFIG=1 Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> Change-Id: Ib53ed293764727b33fe4e4a49abce451724fc689 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3853766 Reviewed-by: Wei-Shun Chang <weishunc@chromium.org> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org>
* mtk_scp: Fix mt8186 clock issues for system suspendAllen-kh Cheng2022-08-264-13/+41
| | | | | | | | | | | | | | | | | | | | | | | | | 1. We have to disable VREQ SEL in mt8186. Pmic Wrap will be unable to enter Eint Mode if this is not the case. 2. Change the name of the function from clock_init() to scp_enable_clock() and include the clock register setting for system suspension in clock_init(). 3. Restore the previous register values of the clock while measuring the ulpos 0/1 clock frequency. 4. Remove the unnecessary clock macro values BRANCH=none BUG=b:214978483 TEST=Boot kukui scp and open cam ok make BOARD=corsola_scp -j ALLOW_CONFIG=1 Signed-off-by: Allen-kh Cheng <allen-kh.cheng@mediatek.corp-partner.google.com> Change-Id: I08a9ab68dd53aad90b68d885f0c13e7bc4e82706 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3853764 Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Commit-Queue: Hsin-Yi Wang <hsinyi@chromium.org>
* npcx: fan: Introduce CONFIG_FAN_BYPASS_SLOW_RESPONSE for slow response fanDevin Lu2022-08-231-1/+2
| | | | | | | | | | | | | | | | | | | | | CL:3539776 fine tune the fan control to avoid fan pwm is too aggressive for slow response fan. However, this fan control mechanism will affect normal response fan with another device. Add a new CONFIG_FAN_BYPASS_SLOW_RESPONSE for option. BUG=b:237237424 BRANCH=none TEST=On Redrix. Test FAN is working with expected rpm while startup. TEST=make buildall Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Change-Id: I9c5388dbfe983b9a5f37f7bcb9217e92eab833ba Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3840993 Tested-by: Devin Lu <devin.lu@quantatw.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Devin Lu <devin.lu@quantatw.com> Reviewed-by: CH Lin <chlin56@nuvoton.com>
* chip: npcx: fix the format of NPCX_ALT_TABLE in gpio_chip-npcx5.hJun Lin2022-08-191-72/+72
| | | | | | | | | | | | | | | | | | The format of the table NPCX_ALT_TABLE in gpio_chip-npcx5.h is messed up after applying clang-format. This CL changes it back to the original layout for better reading. Also, surround the table with /* clang-format off */ and /* clang-format on */ to pass CQ check. BRANCH=none BUG=none TEST=pass "make buildall" Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: Ic6efe9bbc83575ea172af84f92e5f07f714400d5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3826716 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
* chip: npcx: fix the format of NPCX_ALT_TABLE in gpio_chip-npcx7.hJun Lin2022-08-191-93/+93
| | | | | | | | | | | | | | | | | | The format of the table NPCX_ALT_TABLE in gpio_chip-npcx7.h is messed up after applying clang-format. This CL changes it back to the original layout for better reading. Also, surround the table with /* clang-format off */ and /* clang-format on */ to pass CQ check. BRANCH=none BUG=none TEST=pass "make buildall" Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I7e4533517f2615fbeb3512f7f7eddfaf22160355 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3826715 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
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