summaryrefslogtreecommitdiff
path: root/chip
Commit message (Collapse)AuthorAgeFilesLines
* Merge remote-tracking branch 'cros/main' into firmware-gwc-fsiScott Collyer2021-11-23112-369/+481
|\ | | | | | | Change-Id: Id9b5b5cb1db7428cd9f12452d73842d8c1f2705a
| * config: rename CONFIG_HOSTCMD_SHI to CONFIG_HOST_INTERFACE_SHIKeith Short2021-11-195-9/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename CONFIG_HOSTCMD_SHI to CONFIG_HOST_INTERFACE_SHI. This makes the host interface selection configs distinct from configs used to enable/disable specific host commands. BUG=b:195416058 BRANCH=main TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I35959149554f58c8911459dcd025720b6d66eb32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095843 Tested-by: Michał Barnaś <mb@semihalf.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
| * config: rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPIKeith Short2021-11-1920-56/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename CONFIG_HOSTCMD_ESPI to CONFIG_HOST_INTERFACE_ESPI. This makes the host interface selection configs distinct from configs used to enable/disable specific host commands. BUG=b:195416058 BRANCH=main TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I7f52614ca9a0dd54cc7e96e51bba40453564198e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095842 Tested-by: Michał Barnaś <mb@semihalf.com>
| * config: rename CONFIG_HOSTCMD_LPC to CONFIG_HOST_INTERFACE_LPCKeith Short2021-11-197-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename CONFIG_HOSTCMD_LPC to CONFIG_HOST_INTERFACE_LPC. This makes the host interface selection configs distinct from configs used to enable/disable specific host commands. BUG=b:195416058 BRANCH=main TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I6d8722cd314aa7801ea11c1ead5ef6bdd113fd58 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095841 Tested-by: Michał Barnaś <mb@semihalf.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
| * config: rename CONFIG_HOSTCMD_HECI to CONFIG_HOST_INTERFACE_HECIKeith Short2021-11-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename CONFIG_HOSTCMD_HECI to CONFIG_HOST_INTERFACE_HECI. This makes the host interface selection configs distinct from configs used to enable/disable specific host commands. BUG=b:195416058 BRANCH=main TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I2a9e490c2fd6f54f7ab9be809ed2711aa3244409 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3095840 Tested-by: Michał Barnaś <mb@semihalf.com> Reviewed-by: Aaron Massey <aaronmassey@google.com>
| * chip/npcx: Disable linker section check warningTom Hughes2021-11-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When linking with clang (lld), it complains that the .header and .text virtual memory address (VMA) overlaps: ld.lld: error: section .header virtual address range overlaps with .text >>> .header range is [0x10070000, 0x1007003F] >>> .text range is [0x10070000, 0x10095DDB] However, in this case it appears that it's ok that the header overlaps with the text section, since the bootloader uses the header to copy the firmware from flash to RAM (the header itself is not copied). BRANCH=none BUG=b:172020503 TEST=CC=clang make BOARD=elemi TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ic2a7058c85bbcb90c69d2b372f6d33930ac4d212 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3207346 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
| * ite: Fix SRAM size for ITE81302-512Andrew McRae2021-11-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The ITE81302-512 has 60Kb of SRAM. BUG=b:204231736 TEST=make -j buildall BRANCH=none Change-Id: I64f3a41c6df1738cdbb409c8098f485e8e224bb7 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276027 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
| * ite: Add support for ITE81302-512 variantAndrew McRae2021-11-121-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for 512Kb version of ITE81302BX. Required for rework of drawlat to support Nereid zephyr support. BUG=b:204231736 TEST=make -j buildall BRANCH=none Change-Id: I54b3fe0957c0f20a711682e380ef83b95d26a2b3 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3276025 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
| * tree: Make DECLARE_IRQ routine staticTom Hughes2021-11-0884-220/+266
| | | | | | | | | | | | | | | | | | | | | | | | | | For consistency, make all IRQ handler routines static. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I43dc4dd0a8cd593d6eb761768acc5c7b6b95e22b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3227265 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
| * chip/npcx: Fix monitor compilation with clangTom Hughes2021-11-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disable LTO when compiling the monitor header since clang will generate an LLVM IR bitcode file instead of an ARM object file. objcopy then fails since it doesn't recognize the file type. This shouldn't result in any loss of optimization since these are single .c files that are not being linked. Also add a DISCARD section in the linker script to fix the clang (lld) warning: ld.lld: error: no memory region specified for section '.ARM.exidx' This should be safe since there is no ".ARM.exidx" section in npcx_monitor.elf generated by gcc before this change as shown by arm-none-eabi-objdump -h build/brya/chip/npcx/spiflashfw/npcx_monitor.elf Go ahead and discard any other ".ARM.*" sections as well since we do that in our other EC linker scripts. Details on these sections can be found in https://developer.arm.com/documentation/ihi0044/h/?lang=en#sections under the "Sections" section. BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I784d7a9e69989b330f58f89ae3a901d459e7cd21 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3243010 Reviewed-by: Edward Hill <ecgh@chromium.org>
| * npcx: flash: Refactor flash_get_status()Wealian Liao2021-11-031-50/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NPCX internal flash status register 1/2 always read the same time. This CL merges flash_get_status1() flash_get_status2() into 1 function. This improves the performance by eliminating duplicate mutex/tri-state/function call operations. BUG=none BRANCH=none TEST=Set status register & check it by 'flashchip' console command Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I0efe3d0c9461b5e9daae8e29115c511d5dbf90ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3247742 Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
| * npcx: flash: Fix physical_get_protect_flags()Wealian Liao2021-11-031-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Protecting status register by /WP works when SRP0 is enabled. The getting protect flags function should check SRP0 & QE for EC_FLASH_PROTECT_ERROR_INCONSISTENT flag. This CL adds the following: 1. SRP0 & QE bits check for npcx flash. 2. EC_FLASH_PROTECT_ERROR_UNKNOWN flag BUG=none BRANCH=none TEST=Protect a range & don't set the SRP0. Check flag by `flashinfo`. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: Iae8645aca7b0d9176e625de3656a35e675df3ef2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3246882 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
| * CEC: move mkbp event to the cec taskZhuohao Lee2021-11-031-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The interrupt context can't call the function which contains the mutex. In order to fix this problem, we move the send_mkbp_event to the task level and add two events TASK_EVENT_OKAY, TASK_EVENT_FAILED to indicated the okay/failed event. BUG=b:204138787 BRANCH=None TEST=`cec-ctl --playback -S -d 0` without ec crash Change-Id: Ifae592c2161e78cd2a1be4af6e0a30b615ae9f37 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3251219 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
| * chip/stm32/usb_spi.c: Fix bug crippling full duplexJes B. Klinke2021-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It seems that the logical condition of an ifdef had been accidentally negated. Furthermore, in cases where full duplex support is present, the control flow should reach the final else branch of the if statement, which it previously would not when a full duplex transaction was requested. These two mistakes makes it such that SPI full duplex forwarding from USB cannot work on e.g. servo v4 (and on the future HyperDebug board that I am working on.) I have tested this change as part of my HyperDebug code under development, as well as tested that the change compiles on servo_micro. I have not attempted full duplex transactions on servo micro, as I do not currently have a setup that I can use to easily verify. Looking at the code, one can convince oneself that behavior can only change in cases where the code would previously either reject a transaction explicitly, or silently drop it resulting in USB timeout. Signed-off-by: Jes B. Klinke <jbk@chromium.org> BUG=b:192262089 BRANCH=None TEST=make BOARD=servo_micro Change-Id: I5767d91c5b1ada4e54eec7ecd0512345448288e7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3253432 Commit-Queue: Jes Klinke <jbk@chromium.org> Commit-Queue: Brian J. Nemec <bnemec@chromium.org> Tested-by: Jes Klinke <jbk@chromium.org> Auto-Submit: Jes Klinke <jbk@chromium.org> Reviewed-by: Brian J. Nemec <bnemec@chromium.org>
| * chip/mt_scp: mt8195: change S3 clock source to 26MTinghan Shen2021-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The power consumption criteria of SCP in S3 stage cannot be meet by low speed ULPOSC clock. Change it to 26M which will be closed by SPM, so that SCP core will stop running at S3 stage and meet the criteria. BRANCH=None BUG=b:199444513 TEST=scp console stops response in S3, and resume when leave S3. Change-Id: If2adbf85c0096e98a6ad5d8ff9772aad04192bca Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3247735 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
| * chip/mt_scp: support disable/enable WDTTinghan Shen2021-10-293-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since cherry SCP has to reduce power consumption in S3 state, cherry SCP is going to stop running under S3 state. However, SCP WDT is default using 32k clock and cannot change it by design. SCP has to support disable/enable WDT to meet the S3 plan. BRANCH=None BUG=b:199444513 TEST=test enable/disable WDT ok Change-Id: I6c1de9718ec558a5cd8495adc0c7b3f59d2846d7 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3247734 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
| * Revert "chip/mt_scp: disable uart irq in S3 state"Tinghan Shen2021-10-293-32/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reason for revert: SCP still encounters WDT timeout after doing more test. This patch doesn't solve the issue. Original change's description: > chip/mt_scp: disable uart irq in S3 state > > According to the latched PC/LR in a S3 watchdog timeout case, > SCP is handling UART IRQ when watchdog timeout. > Before find out the reason of triggering UART IRQ, disable UART IRQ in > S3 state to prevent handling it. UART IRQ is enabled when resumed. > > BRANCH=None > BUG=b:199444513 > TEST=SR test >4000 times on 5 devices. > > Change-Id: I06a4c31ecb9a82978bee8deb04315a11778253f0 > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3235729 > Tested-by: TingHan Shen <tinghan.shen@mediatek.corp-partner.google.com> > Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> > Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> BRANCH=None BUG=b:199444513 TEST=make BOARD=cherry pass Change-Id: Iffeb88dc21567dff82604d156d575a28df262d02 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3247733 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
| * chip/mt_scp: dump 8195 panic information on console channelTinghan Shen2021-10-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Save the panic information on DRAM to keep it available at next reboot. This requires a new non-cacheable DRAM MPU with RW permission. Besides panic information, also checks the WDT latch registers that will latch PC/SP/LR when triggered SCP WDT timeout. BRANCH=None BUG=b:199444513 BUG=b:189356151 TEST=see exception log at /var/log/cros_scp.log on tomato board Change-Id: Ief9db8ec8b5b83805c21370d6be8ff49a8bb98df Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3250076 Reviewed-by: Rong Chang <rongchang@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
| * npcx: flash: Disable flash QE bit at initWealian Liao2021-10-271-31/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In NPCX9 production devices, the flash status register’s quad enable bit (non-volatile) will be set by default. When the QE bit of Status Register-2 is set for Quad I/O, the WP# signal is not supported since this pin is used as IO2. This CL clears the QE bit at init to make sure WP# support is enabled. BRANCH=none BUG=none TEST=Set QE bit & reboot the ec. Check the QE bit is disabled. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: Ic07403f1f1ac0e7f3362ef94670608ee25d77f51 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3246881 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
| * chip/mt_scp: disable uart irq in S3 stateTinghan Shen2021-10-263-2/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the latched PC/LR in a S3 watchdog timeout case, SCP is handling UART IRQ when watchdog timeout. Before find out the reason of triggering UART IRQ, disable UART IRQ in S3 state to prevent handling it. UART IRQ is enabled when resumed. BRANCH=None BUG=b:199444513 TEST=SR test >4000 times on 5 devices. Change-Id: I06a4c31ecb9a82978bee8deb04315a11778253f0 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3235729 Tested-by: TingHan Shen <tinghan.shen@mediatek.corp-partner.google.com> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* | Merge remote-tracking branch 'remotes/m/master' into fw-quiche-merge-yellow-bangScott Collyer2021-10-1973-303/+728
|\ \ | |/ | | | | | | Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Idf74bda59e3a4706adcea9310c2780d142e797aa
| * chip/mchp: Fix license textTom Hughes2021-10-195-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | The cros_license_check presubmit is complaining. BRANCH=none BUG=b:172020503 TEST=none Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I56657835cb96492e4984f7734e96b8436c3a543b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229798 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * tree: Files should end with single newlineTom Hughes2021-10-1836-36/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the checks that runs as part of "repo upload" looks for a single newline at the end of each file. I'm getting warnings about this when I touch files that do not follow this, even though I didn't add the extra newlines. This commit fixes all files by running the following: for f in $(find . -name '*.[ch]'); do printf '%s\n' "$(cat ${f})" > ${f}; done BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ia3ece5b64b549d21ca11708791368002bb6e9b0e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3229797 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
| * chip/stm32: Include gpio_chip.h when using gpio_interruptTom Hughes2021-10-188-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These files call gpio_interrupt(), but were not including the function declaration. BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Iaaedce2a4668dd05581aaa237344cd520c7eb715 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3227263 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
| * chip/npcx: Remove unused GPIO interrupt functionTom Hughes2021-10-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the interrupt handlers are made static (see followup commits), the compiler complains that this function is unused (there is no corresponding DECLARE_IRQ): chip/npcx/gpio-npcx9.c:182:15: error: '__gpio_wk2fg_interrupt' defined but not used [-Werror=unused-function] GPIO_IRQ_FUNC(__gpio_wk2fg_interrupt, WUI_INT(MIWU_TABLE_2, MIWU_GROUP_6)); BRANCH=none BUG=b:172020503 TEST=./util/compare_build.sh -b all -j 120 => MATCH Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I3f58cdcb9b2e113fb9dd079a3e157bf8336b71d5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3227262 Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
| * tree: Make all console commands staticTom Hughes2021-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all of the console commands were already static. This change makes all of them static for consistency. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I0ac46358b6fbafa65504c648ce4de0365cdbf723 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3224372 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * tree: Make all host commands staticTom Hughes2021-10-151-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Almost all of the host commands were already static. This change makes all of them static for consistency. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I8330e85e6d64a039f08d7620eed1fe897f436567 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3221786 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
| * chip/stm32: Avoid out of bounds array access on TCPCI_MSG_TX_BIST_MODE_2Tom Hughes2021-10-131-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang warns: chip/stm32/ucpd-stm32gx.c:797:5: error: array index 582424 is past the end of the array (which contains 7 elements) [-Werror,-Warray-bounds] ucpd_txorderset[TX_ORDERSET_SOP]; ^ ~~~~~~~~~~~~~~~ chip/stm32/ucpd-stm32gx.c:127:1: note: array 'ucpd_txorderset' declared here static int ucpd_txorderset[] = { The if clause handles SOP -> Cable Reset and the only type that does not handle is TCPCI_MSG_TX_BIST_MODE_2. That case is a "don't care" for sync packets as it's just a continuous 1/0 bit pattern. BRANCH=none BUG=b:172020503 TEST=make CC=arm-none-eabi-clang BOARD=baklava Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ia2b73bcbf7eabe2de480633d4e65b8df55137e2e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3198206 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
| * core: Fix flash size calculation when linking with lld (clang)Tom Hughes2021-10-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The map file generated by lld has a different format than the gnu linker (ld). (We save this map file into build/<board>/<image>/ec.<image>.map during the build.) Instead of trying to parse the different formats in the .map file, use the .smap file (the output of "nm"), which has the values of the symbols and has the same format whether using lld or ld. We need to add a new "__flash_size" symbol so that we can use that symbol to get the size from the .smap. This add flash sizes to a few boards that previously didn't have it: asurada_scp, cherry_scp, and kukui_scp, since the previous logic was always looking for FLASH and these use IROM. BRANCH=none BUG=b:172020503 TEST=make buildall -j TEST=make CC=arm-none-eabi-clang BOARD=elemi TEST=bcompare build_before_change build_after_change => only difference between space_free_flash.txt and space_free_ram.txt files in the two builds is that this change adds the space_free_flash.txt files for asurada_scp, cherry_scp, and kukui_scp. Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I7c64b6ba9bceeeb4044559188c1c1bebbf60471d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3179314 Reviewed-by: Keith Short <keithshort@chromium.org>
| * core/cortex-m: Disable warning in vecttable.c when building with clangTom Hughes2021-10-081-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | See the description in commit c1cc2d919e9f21adc0f992dcac00f6e8b282616d. These files copied the same logic. BRANCH=none BUG=b:172020503 TEST=make buildall TEST=CC=arm-none-eabi-clang make BOARD=servo_micro Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I1d59b3a7eb6e71451313d70fe421880a08dad4b0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3183392 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
| * chip/stm32: Proper declarations for USB clock and SRAM on L5Jes B. Klinke2021-10-083-122/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32L5 series has a few more flags to control power and clock to the USB block. Add code to enable all of them from clock_enable_module(). BUG=b:192262089 TEST=Compile with hyperdebug board (from later in the chain) BRANCH=none Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Change-Id: Idd9f31bcb9461686c401f8bdcb306e61858a9966 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3133815 Reviewed-by: Scott Collyer <scollyer@chromium.org>
| * stm32: usb-ep: Add Windows OS Extended Compat ID descriptorScott Collyer2021-10-071-4/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds changes required so that Windows OS will recoginize STM32 USB-EP as registered device and avoid the yellow exclamation point warning in the systray. BRANCH=quiche BUG=b:196174088 TEST=Verfied with Baklava that there is no "yellow exclamation" warning when connected to a Windows OS host machine. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I1fa4fa0d01f3447f8350264f7253849fdfb89336 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3150055 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
| * chip/npcx: Fix return typeTom Hughes2021-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ip/npcx/shi.c:1079:9: error: implicit conversion from enumeration type 'enum ec_error_list' to different enumeration type 'enum ec_status' [-Werror,-Wenum-conversion] return EC_SUCCESS; BRANCH=none BUG=b:172020503 TEST=make CC=arm-none-eabi-clang BOARD=coachz Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Id83c5d74dfc479f02c0260ac4f0086eab5d901fb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3206479 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * chip/npcx: Fix enum typeTom Hughes2021-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang reports that the enum types do not match: chip/npcx/lpc.c:967:9: error: implicit conversion from enumeration type 'enum ec_error_list' to different enumeration type 'enum ec_status' [-Werror,-Wenum-conversion] return EC_SUCCESS; common/power_button_x86.c:523:9: error: implicit conversion from enumeration type 'enum ec_error_list' to different enumeration type 'enum ec_status' [-Werror,-Wenum-conversion] return EC_SUCCESS; BRANCH=none BUG=b:172020503 TEST=make CC=arm-none-eabi-clang BOARD=aleena Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I25d1526d58e1e8558153592be7174a8448c130f5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3202998 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * chip/stm32: remove unused variableTom Hughes2021-10-041-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang warns: ip/stm32/usb_hid_keyboard.c:378:21: error: unused variable 'hid_current_buf' [-Werror,-Wunused-variable] static volatile int hid_current_buf; ^ BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I88b424cbc8930bf2d7d6c0856d81104cbd4d3561 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3198203 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * chip/ish: Fix return typeTom Hughes2021-09-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang warns that the types do not match: chip/ish/host_command_heci.c:140:9: error: implicit conversion from enumeration type 'enum ec_error_list' to different enumeration type 'enum ec_status' [-Werror,-Wenum-conversion] return EC_SUCCESS; BRANCH=none BUG=b:172020503 TEST=none Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ief6c5ecb4a6850a5560357f6f9c7cb7c5bd22797 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193272 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * chip/stm32: Make function definition and declaration matchTom Hughes2021-09-292-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "test_mockable_static" is static, but the declaration created by DECLARE_IRQ is not static. The mismatch generates a compiler warning when building with clang: chip/stm32/clock-f.c:325:6: error: unused function '__rtc_alarm_irq' [-Werror,-Wunused-function] void __rtc_alarm_irq(void) BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I39e2de93b057b5565c54ffb83e1633a13db1ce46 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172039 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
| * npcx: Correct the image copies indication bits for npcx9Jun Lin2021-09-284-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07 of the MDC register) to indicate what the current image copy is. In npcx9, these two bits are used by the booter. We need to change them to another two empty scratch bits which are not used by the booter. BUG=b:165777478, b:200642229 BRANCH=none TEST=pass "make buildall" TEST=check the related bits changed by "sysump ro" and "sysjump rw" TEST=jump to RW & check sysinfo after reset-pin/watchdog/debug reset Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I9801efe7fe7645e7b81df9c5cc69372df0a178a8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3178700 Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Yuval Peress <peress@google.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
| * chip/mt_scp: Declaration needs to come before definitionTom Hughes2021-09-274-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are already disabling -Wignored-attributes to work around the declaration and definition order issue: error: attribute declaration must precede definition [-Werror,-Wignored-attributes] However, although there are no compiler errors, the linker (lld) will still fail: ld.lld: error: undefined symbol: clock_control_irq >>> referenced by clock.c:347 (src/platform/ec/chip/mt_scp/mt8183/clock.c:347) >>> lto.tmp:(irq_13_handler) ... ld.lld: error: undefined symbol: clock_fast_wakeup_irq >>> referenced by clock.c:355 (src/platform/ec/chip/mt_scp/mt8183/clock.c:355) >>> lto.tmp:(irq_44_handler) Tested with the compare_build.sh script to validate that the resulting binaries are identical. BRANCH=none BUG=b:172020503 TEST=CC=arm-none-eabi-clang make BOARD=kukui_scp -j TEST=./util/compare_build.sh --boards all -j 50 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ib622fb98784a4c3ad3c199c72ee7604c7f709d6c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3182621 Reviewed-by: Diana Z <dzigterman@chromium.org>
| * it83xx: clock: fix sequence to set PLL control registerDino Li2021-09-271-6/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We change event timer's clock to 32.768kHz before entering low power mode. And will restore the clock to 8MHz (by checking PLL control register's setting in ISR) when chip wake up from the low power mode. So we need to ensure the setting is taken into PLL control register before wfi instruction. The original implementation can't ensure event timer’s clock is restored to 8MHz when chip wake up. So we fix it. This also fix wfi (wait for interrupt) instruction fail issue on RISV-V core chips when a timer count down to zero (MTIP@mip is set to 1 until HW reload timer counter). Once CPU executed wfi instruction, CPU should stay there until interrupt is fired or MEIP@mip is non-zero. But currently, HW checks entire mip value (should check MEIP@mip only) to decide whether or not to ignore wfi instruction. The issue will cause EC premature wake from idle task even there is no interrupt fired. BRANCH=asurada, icarus BUG=none TEST=-On asurada, increase CPU clock to 96mhz. Plug out/in type-c adapter to wake chip up from low power mode, no pre-watchdog warning fired. (x100) -buildall Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I72bb2566c5b22bc132ab304a38a5a1b5b968e463 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3168672 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
| * npcx/i2c: Implement chip_i2c_[gs]et_freqCaveh Jalali2021-09-261-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements missing I2C driver functions to get or set the I2C bus speed on NPCX family chips. BRANCH=none BUG=b:201039003 TEST=with follow-on patches, switched I2C bus speed between 400 kHz and 1 MHz. Change-Id: Ie0d8de1ca2c4884e52f5fe947ad19a50b0c76fb9 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3170292 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * npcx/i2c: Track configured I2C port speedCaveh Jalali2021-09-251-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds code to the npcx I2C driver to keep track of the speed setting used to configure the port. This can be used to determine the current speed setting without decoding chip registers. BRANCH=none BUG=b:201039003 TEST=with follow-on patches, switched I2C bus speed between 400 kHz and 1 MHz. Change-Id: Ib7a61e23ec406deff80afead2e2aa6b64578ea1d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3181502 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * npcx/i2c: Rename variable for clarityCaveh Jalali2021-09-251-5/+5
| | | | | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:201039003 TEST=buildall passes Change-Id: I5b34e5266f28452d30d76489e4afaef4cb2287e2 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3181501 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * npcx/i2c: Refactor i2c_freq_changedCaveh Jalali2021-09-251-74/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This splits the implementation of i2c_freq_changed() into a per-port worker function and a top-level iterator function. This change makes i2c_port_set_freq() available to set a port's I2C speed. BRANCH=none BUG=b:201039003 TEST=with follow-on patches, switched I2C bus speed between 400 kHz and 1 MHz. Change-Id: Ifb5613ac3a59cbd64f01f3a396f978db5e77d9f1 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3170291 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| * chip/mt_scp: Fix return typeTom Hughes2021-09-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clang complains that the types do not match: chip/mt_scp/mt8183/ipi.c:349:9: error: implicit conversion from enumeration type 'enum ec_error_list' to different enumeration type 'enum ec_status' [-Werror,-Wenum-conversion] BRANCH=none BUG=b:172020503 TEST=make buildall -j TEST=CC=arm-none-eabi-clang make BOARD=kukui_scp -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I14e850f5e2ace5c3f3e59c7bc2aa90b3eaf92a9d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3182620 Reviewed-by: Edward Hill <ecgh@chromium.org>
| * Revert "npcx: correct the image copies indication bits for npcx9"caveh jalali2021-09-214-24/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 20222d48571fa44c76fdb0ededd0ed042e9f8244. Reason for revert: brya thinks it's in EC-RW when it's really still in EC-RO. Original change's description: > npcx: correct the image copies indication bits for npcx9 > > In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07 > of the MDC register) to indicate what the current image copy is. > In npcx9, these two bits are used by the booter. We need to change them > to another two empty scratch bits which are not used by the booter. > > BUG=b:165777478 > BRANCH=none > TEST=pass "make buildall" > TEST=check the related bits changed by "sysump ro" and "sysjump rw" > > Signed-off-by: Jun Lin <CHLin56@nuvoton.com> > Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119 > Tested-by: CH Lin <chlin56@nuvoton.com> > Reviewed-by: caveh jalali <caveh@chromium.org> > Auto-Submit: CH Lin <chlin56@nuvoton.com> > Commit-Queue: caveh jalali <caveh@chromium.org> Bug: b:165777478 Change-Id: I24cdfec0d5c8cd998f087525ae21b2a3daea43a7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172266 Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Tested-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
| * npcx: correct the image copies indication bits for npcx9Jun Lin2021-09-174-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07 of the MDC register) to indicate what the current image copy is. In npcx9, these two bits are used by the booter. We need to change them to another two empty scratch bits which are not used by the booter. BUG=b:165777478 BRANCH=none TEST=pass "make buildall" TEST=check the related bits changed by "sysump ro" and "sysjump rw" Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Auto-Submit: CH Lin <chlin56@nuvoton.com> Commit-Queue: caveh jalali <caveh@chromium.org>
| * chip: it83xx/gpio: condition for adding judgmentTim Lin2021-09-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there is an I/O expander driver for keyboard, there is no need to enter the keyboard_raw_interrupt(). BUG=b:199337186 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: Ie24f5b5592325a76d9a36a689657bdd2e05c8fb1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3151046 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
| * chip/stm32: UART declarations for STM32L5 seriesJes B. Klinke2021-09-082-1/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | STM32L5 can have up to four UARTs, one more than previous Lx series. These files were copied from usart-stm32l.{h,c}, modified only by making one more copy of the appropriate declarations. BUG=b:192262089 TEST=Compile with hyperdebug board (from later in the chain) BRANCH=none Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Change-Id: I8bd2d13de67fc74b59c16a79a87fd4615912be09 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3133814 Reviewed-by: Scott Collyer <scollyer@chromium.org>
| * chip/stm32: Factor family specific clock logic out of usb.cJes B. Klinke2021-09-085-32/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The register for enabling USB register clock appears to have been identical across F0, F3, and G4 families, but for L5 it is different. Rather than having #ifdef in usb.c (as I recently committed), this CL will move the clock logic into clock_enable_module() where it arguably belonged all the time. Additionally: Some of the chip families make use of a clock_mask in their implementation of clock_enable_module(), but since the module_id enum has more than 32 value, until now, some values (among those MODULE_USB) would result in overflow, causing new_mask to be identical to clock_mask, and the USB case could have never been reached. BUG=b:192262089 TEST=Compile servo_v4 without linker errors BRANCH=none Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Change-Id: I7c29339f45eb513e3e78f662797a70543912c8c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130733 Reviewed-by: Scott Collyer <scollyer@chromium.org>
View Lorry Controller Status