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* cleanup: Fix gcc 5.2.1 compile errorsShawn Nematbakhsh2015-11-111-0/+2
| | | | | | | | | | | | | | | BUG=chromium:552006 BRANCH=None TEST=`make buildall -j` and also verify panic reporting works on glados_pd. Change-Id: Ic9f1ec6b5297389df0d46bb38a67c156901ed956 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311253 Commit-Ready: Shawn N <shawnn@gmail.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it8380dev: Modify port 80 service routineEli Hsu2015-11-112-4/+4
| | | | | | | | | | | | | | | | | Change the parameter name. Change the output length of console command - port80. Signed-off-by: Eli Hsu <eli.hsu@ite.com.tw> BRANCH=none BUG=none TEST=console command port80 Change-Id: I8da3f7ec30f16ceea17a8f4fec55162f73a4b28b Reviewed-on: https://chromium-review.googlesource.com/311960 Commit-Ready: Eli Hsu <eli.hsu@ite.com.tw> Tested-by: Eli Hsu <eli.hsu@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Tweak debug message for clarityBill Richardson2015-11-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until we update the naming for our various images in the Makefiles, let's change the bootloader message slighty, so that instead of seeing two "RO" images: CR50 RO, 20151104_41733@78962 Valid image found at 0x00044000, jumping --- UART initialized after reboot --- [Reset cause: power-on] [Image: RO, cr50_v1.1.4008-957a842 2015-11-07 00:28:37 wfrichar@wintermute4.mtv. corp.google.com] [0.000897 Verifying RW image...] we see the bootloader, and then what we've been calling the RO image, and then the RW image: cr50 bootloader, 20151104_41733@78962 Valid image found at 0x00044000, jumping --- UART initialized after reboot --- [Reset cause: power-on] [Image: RO, cr50_v1.1.4008-957a842 2015-11-07 00:28:37 wfrichar@wintermute4.mtv. corp.google.com] [0.000897 Verifying RW image...] BUG=none BRANCH=none TEST=make buildall, try it No new functionality, just a different message on the console. Change-Id: Ia8dce600c7d159416dc6dabbbf0c0cc4129a988d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311831 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Fix uart_tx_flush() to really flushBill Richardson2015-11-101-2/+3
| | | | | | | | | | | | | | | | | | We were just checking to see if the UART TX unit was idle. We also need to be sure there aren't any bytes in the TX FIFO that haven't been clocked out yet. BUG=none BRANCH=none TEST=make buildall, manual Before, "crash watchdog" would truncate the trace dump as it rebooted. Now it doesn't. Change-Id: Icff828445801ce61a0a8f296b3d3e9fb300b7efc Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311299 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Workaround for watchdog permission problemsBill Richardson2015-11-102-9/+20
| | | | | | | | | | | | | | | | | | | | When we lower the runlevel for security purposes, the standard ARM watchdog interrupt is no longer enough to cause a full reboot. We'll manually trigger a system reset instead. For now, it's a soft reset. Should it be hard? BUG=chrome-os-partner:47289 BRANCH=none CQ-DEPEND=CL:310975 TEST=make buildall, manual From the console, run "crash watchdog". After a second or to, the watchdog trace dump appears and the system reboots. Change-Id: I99fcaf19b32728563e3b051755d65267cc11156c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311298 Reviewed-by: Nagendra Modadugu <ngm@google.com>
* it8380dev: modify hwtimer's commentDino Li2015-11-101-1/+1
| | | | | | | | | | | | | | Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make buildall -j Change-Id: Id161c84437e8d6edc2ec1a4cde292f642d08b853 Reviewed-on: https://chromium-review.googlesource.com/311333 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: make customized RO workVadim Bendebury2015-11-102-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch completes introduction of building of proper RO and RW images for cr50. A few small mods were required: - both RO and RW images have to be signed, using the same dedicated signer, but with different keys, dev_key.pem is not needed any more. - the RW image offset is not at the half of available flash, a chip specific value of 16K is used instead. The suggested new image layout is as follows: +----------------------------------------+ | 1KB RO signature header. | +----------------------------------------+ - - | 15KB RO image. | - - +========================================+ | 1KB RW-A signature header. | +----------------------------------------+ - - - - | 239K RW-A image. | - - - - +========================================+ - - | 16 KB NVRAM, shared | - - +========================================+ | 1KB RW-B signature header. | +----------------------------------------+ - - - - | 239K RW-B image. | - - - - +========================================+ BRANCH=none BUG=chrome-os-partner:43025 TEST=The combined image (build/cr50/ec.hex) is successfully loaded and started by the spiflash utility from the latest FPGA tarball. Corrupting a byte in the generated image in the RW section causes failure to verify. Change-Id: I41a05168b0d4e9f88efa1003f261b6dd03972a24 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311422 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: allocate signature headers in both RO and RW imagesVadim Bendebury2015-11-101-0/+1
| | | | | | | | | | | | | | | | With the proper RO in place, RW must be signed in the same manner, as RO. This patch makes sure that there is room in the RW header for the signature. BRANCH=none BUG=chrome-os-partner:43025 TEST=with the rest of the patches applies the RO successfully boots up the RW. Change-Id: I1538195e0181c23c874ddd300887cf5da8c5a867 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311421 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: RO Loader implementationVadim Bendebury2015-11-1012-5/+858
| | | | | | | | | | | | | | | | | | | | | | | This code is a port of the sample loader application included in the FPGA update. Only the pieces relevant to straight verification and boot were ported. The loader generates a hash, inputs to which are the image body, state of fuses and state of flash INFO region, and the output is the value, which will unlock the region for execution, if it is correct. Only one image load is attempted, the image is supposed to be located in the flash at the offset of CONFIG_RW_MEM_OFF. BRANCH=none BUG=chrome-os-partner:43025 TEST=with the rest of the patches applied the RO image successfully verifies and starts up the RW image. Change-Id: I26e1fbdaeb8b23d519c1a328526a3422231bb322 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311316 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: re-generate register descriptionsVadim Bendebury2015-11-102-21/+25
| | | | | | | | | | | | | | New aliases are created automatically, there is no need to include them in registers.h manually any more. BRANCH=none BUG=none TEST=built and ran cr50 successfully Change-Id: I9c12c9a66d231723f8c986dd0c598f1e03aaca3a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311372 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* GLaDOS: Kunimitsu: Enable link-time optimization.Aseda Aboagye2015-11-091-0/+9
| | | | | | | | | | | | | | | | | | | | Turn on LTO for GLaDOS and Kunimitsu. This saves about 5k from the image on GLaDOS. Also, LTO is disabled for the loader since it actually causes it to bloat in size for some reason. BUG=chrome-os-partner:46063 BRANCH=None TEST=Build and flash on GLaDOS with charger inserted. Verify that EC boot is successful. sysjump to RW and verify that the jump is successful. TEST=make -j buildall tests Change-Id: I9892edfc724f290acaf6cceba181c177702d63bf Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/311208 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Rename usb.h to usb_descriptor.hShawn Nematbakhsh2015-11-0812-12/+12
| | | | | | | | | | | | | | | | Rename usb.h to usb_descriptor.h to prevent conflict with a commonly-used libusb header. BUG=chromium:552006 BRANCH=None TEST=`make buildall -j` Change-Id: I6145ce120e1fda41bc5c4d4da0313272e76839c7 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311429 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Fix soft reboot to handle dropped permissions.nagendra modadugu2015-11-061-7/+31
| | | | | | | | | | | | | | | | | | Permission registers only reset on power cycle, so a soft reboot will fail unless a minimum power cycle is performed. BRANCH=none BUG=chrome-os-partner:47289,chrome-os-partner:43025 TEST=hard / soft reboot from ec shell Signed-off-by: nagendra modadugu <ngm@google.com> Change-Id: I8f0f1bc80a2748b031a9b7a3715485577f2b5b3b Reviewed-on: https://chromium-review.googlesource.com/310975 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Tested-by: Nagendra Modadugu <ngm@google.com> Commit-Queue: Nagendra Modadugu <ngm@google.com> Trybot-Ready: Nagendra Modadugu <ngm@google.com>
* Cr50: Update to the "final" FPGA image 20151104_041733@78962Bill Richardson2015-11-062-541/+562
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In fact this provides support for three FPGA images: 20151104_011218 - full crypto, no USB 20151104_041733 - tiny crypto, full USB 20151104_065845 - full crypto, full USB (only for hard-to-get boards) We can tell these FPGA images apart at run-time by looking at some SWDP registers: register crypto usb full GREG32(SWDP, BUILD_TIME) 0x2bd2 0xa305 0x10135 GREG32(SWDP, FPGA_CONFIG) 0x1 0x2 0x3 This CL includes a run-time check for the USB features so that it's safe to build the firmware with CONFIG_USB and run it on a non-USB FPGA image. Here are the differences I could find in the top-level image header files: All three FPGA images define different (apparently arbitrary) default values for the PMU_PWRDN_SCRATCHn registers, but other than that, the usb and full images differ only in the BUILD_TIME and FPGA_CONFIG register values. I'm not sure why, but function uart_init() in file chip/g/polling_uart.c writes to one of the PMU_PWRDN_SCRATCHn registers, but nothing seems to read it again. The crypto image defines these values which don't appear in the other images: #define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x4f #define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x50 #define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x51 #define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x52 #define PINMUX_USB0_EXT_RX_DMI_SEL 0x53 #define PINMUX_USB0_EXT_RX_DPI_SEL 0x54 #define PINMUX_USB0_EXT_RX_RCV_SEL 0x55 #define PINMUX_USB0_EXT_SUSPENDB_SEL 0x56 #define PINMUX_USB0_EXT_TX_DMO_SEL 0x57 #define PINMUX_USB0_EXT_TX_DPO_SEL 0x58 #define PINMUX_USB0_EXT_TX_OEB_SEL 0x59 #define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x230 #define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x234 #define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x238 #define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x23c #define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x240 #define PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x244 #define PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x248 #define PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x24c #define PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x250 #define PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x254 #define PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x258 #define PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0 The crypto image also differs in this: #define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x25c instead of this: #define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x230 The rest of the differences between the crypto and usb versions are in these values, which I don't think we care about. At least, I can't find any place where they're used. PINMUX_EXITEDGE0_DIOAn_OFFSET PINMUX_EXITEDGE0_DIOBn_OFFSET PINMUX_EXITEDGE0_DIOMn_OFFSET PINMUX_EXITEDGE0_VIOn_OFFSET PINMUX_EXITEDGE0_OFFSET PINMUX_EXITEN0_DIOAn_OFFSET PINMUX_EXITEN0_DIOBn_OFFSET PINMUX_EXITEN0_DIOMn_OFFSET PINMUX_EXITEN0_VIOn_OFFSET PINMUX_EXITEN0_OFFSET PINMUX_EXITINV0_DIOAn_OFFSET PINMUX_EXITINV0_DIOBn_OFFSET PINMUX_EXITINV0_DIOMn_OFFSET PINMUX_EXITINV0_VIOn_OFFSET PINMUX_EXITINV0_OFFSET PINMUX_HOLD_OFFSET PINMUX_SEL_COUNT PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET PINMUX_XO0_TESTBUSn_SEL PINMUX_XO0_TESTBUSn_SEL_OFFSET I used the header from the usb image to update chip/g/cr50_fpga_regdefs.h BRANCH=none BUG=chrome-os-partner:43791 CQ-DEPEND=CL:310978 TEST=make buildall I also built a single Cr50 firmware and tried it on both the crypto and usb FPGA images. Both worked as expected. Change-Id: Ia8a064758f71f86771729437ae3e81226fd55789 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311211
* Cr50: Disable customized RO image by defaultBill Richardson2015-11-062-4/+8
| | | | | | | | | | | | | | | | | | | | | A previous commit caused ToT to use a not-yet-working bootloader. This disables that bootloader by default so that the rest of us can continue to work. ;-) A configuration option is added to be able to address this issue in the future with other boards as well. BRANCH=None BUG=chrome-os-partner:43025, chromium:551151 TEST=make buildall -j Also verified that both normal and customized cr50 RO images build and work as expected. Change-Id: Ie433b07860cb1b04c12b2609c6fa39025fc0e515 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310978
* cr50: introduce RO image skeletonVadim Bendebury2015-11-054-1/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CR50 board will have to have a very different RO image, let's make it possible to override the default list of objects compiled by the top level makefile with a board/chip specific list compiled in the appropriate build.mk file. The CR50 RO will never run on its own for long time, it will always load an RW and go straight to it, so there is no need in running under the OS control, using sophisticated console channel controls, etc. The gist of the functionality is verifying the RW image to run and setting up the hardware to allow the picked image to execute, it will be added in the following patches. This change just provides the plumbing and shows the 'hello world' implementation for the customized RO image. A better solution could be the ability to create distinct sets of make variables for RO and RW, a tracker item was created to look into this. BRANCH=None BUG=chrome-os-partner:43025, chromium:551151 TEST=built and started ec.RO.hex on cr50, observed the 'hello world' message on the console. Change-Id: Ie67ff28bec3a9788898e99483eedb0ef77de38cd Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310410 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* it8380dev: modify hwtimer and LPC wake upDino Li2015-11-055-176/+52
| | | | | | | | | | | | | | | | | | | | | | | | | 1. In combinational mode and clock source is 8MHz, if timer 3 counter register always equals to 7, then timer 4 will be a 32-bit MHz free-running counter. 2. Fix TIMER_32P768K_CNT_TO_US(), each count should be 30.5175 us, not 32.768us. 3. Fix TIMER_CNT_8M_32P768K(). 4. Make sure LPC wake up interrupt is enabled before entering doze / deep doze mode. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Console commands: 'gettime', 'timerinfo', 'waitms', and 'forcetime'. 2. Enabled Hook debug, no warning message received (48hrs). 3. Tested ectool command 'version' x 2000. Change-Id: I796d985361d3c18bc5813c58705b41923e28c5b1 Reviewed-on: https://chromium-review.googlesource.com/310039 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Fix bug in print_later, add overflow detectionBill Richardson2015-11-051-9/+18
| | | | | | | | | | | | | | | | | | | | | | | | | Oops. I was losing one of the args when the USB debugging output was enabled. And with a lot of messages I was also losing some of the output. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual test of Cr50 USB: 1. Plug into a USB jack on a Linux host. 2. In src/platform/ec/extra/usb_console, run make ./usb_console -p 5014 -e 1 3. Type something, hit return 4. See whatever you typed come back with swapped case 5. ^D to quit Change-Id: I284606aa91a76262644cfce60913a91ccc36ae60 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310846 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* mec1322: reduce system stack sizeli feng2015-11-041-9/+8
| | | | | | | | | | | | | | | | | | | | | | | Reduce system stack size from 4096 to 1024. Increase code RAM size to 104K and reduce data RAM size to 20K. BUG=chrome-os-partner:45690 BRANCH=None TEST=Tested on Kunimitsu 1. Flash EC, boot up, force to S5/G3, back to S0; and powerd_dbus_suspend to S3, all work fine. 2. Use console command to dump system stack memory values, the size used is around 350, >600 still available. Change-Id: Ib004678cc16f10c94c333063b728a2816ed5b3c5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/310581 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* mec1322: killing the white whale (removing temp files left behind)Vadim Bendebury2015-11-041-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This has been bothering me literally for years: once in a while there would be tons of files in /tmp directory named tmpXXXXXX where XXXXXXX is some random string. Finally, it became clear that the files are generated when 'make buildall -j' is called in the ec directory. Next step - it looks like one of the culprits is building for board named 'chell'. Indeed, this board uses its own version of cmd_obj_to_bin make function, which, among other things invokes the pack_ec script to pack the image. The script was creating temporary files and leaving them behind. This patch makes the name pattern of the temp files better recognizable, juts in case, and makes sure that the files are deleted once they are not needed. BRANCH=none BUG=none TEST=invoking 'make buildall -j' still succeeds but does not result in leaving temp files behind. Change-Id: I50c511773caa87d4e92980c4c9a36768b0c3101f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310586 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32: i2c: Use correct timingr values based on clock sourceShawn Nematbakhsh2015-11-031-5/+5
| | | | | | | | | | | | | | | | Previous change 813e56e10af4 broke this by interchanging the values. BUG=chrome-os-partner:46188 BRANCH=None TEST=`make buildall -j` Change-Id: I9a66949b66e0d6736c007773740b4f7431faa3cc Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310057 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Standardize use of CONFIG_I2C and add MASTER/SLAVE CONFIGsShawn Nematbakhsh2015-11-034-4/+0
| | | | | | | | | | | | | | | | | | | Some chips previously defined CONFIG_I2C and others didn't. Standardize the usage by removing CONFIG_I2C from all config_chip files and force it to be defined at the board level. Also, make boards define CONFIG_I2C_MASTER and/or CONFIG_I2C_SLAVE based on the I2C interfaces they will use - this will assist with some later cleanup. BUG=chromium:550206 TEST=`make buildall -j` BRANCH=None Change-Id: I2f0970e494ea49611abc315587c7c9aa0bc2d14a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310070 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: fix gpio_disable_interruptKyoung Kim2015-11-031-1/+1
| | | | | | | | | | | | | | | | | MEC1322_INT_DISABLE(interrupt enable clear register) is 'Write 1 to Clear' for each bit. To disable interrupt for specific GPIO pin, only specific bit should be written with 1. BUG=NONE BRANCH=NONE TEST=NONE Change-Id: Ibf40a20656c4c99f9625b516cff3e7da9bf2f69d Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/309979 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* it8380dev: fix irq, jtag and systemDino Li2015-11-014-21/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | [irq] 1. The chip_init_irqs() function clears all IERx and EXT_IERx registers. [jtag] 2. Enable debug mode through SMBus. [system] 3. remove console_force_enabled functions. 4. implement __no_hibernate, scratchpad and nvcontext functions. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chrome-os-partner:23575 TEST=1. IERx and EXT_IERx registers are all cleared after chip_init_irqs(). 2. console command "scratchpad" and "hibernate". 3. bram bank0 index 0x10 ~ 0x1F (16 bytes) for system_get_vbnvcontext() and system_set_vbnvcontext functions. Change-Id: If044d50c69ae80b013ab646a3a6931cec7560ec4 Reviewed-on: https://chromium-review.googlesource.com/309390 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: Add state machines to handle i2c master stall bus and call i2c_xfer again.Mulin Chao2015-11-011-21/+94
| | | | | | | | | | | | | | | | | | Create two state machines SMB_WRITE_SUSPEND and SMB_READ_SUSPEND to handle i2c master stall bus and call i2c_xfer again. Notice we should disable i2c interrupt since cannot read/write SDA reg to clear interrupt pending bit. Modified drivers: 1. i2c.c: Modified to handle calling i2c_xfer twice or more. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I781f6f8227867ea9c0e265b3064f48602c0f5f07 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/309381 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f0: i2c: Set timing register values by port clock sourceShawn Nematbakhsh2015-10-301-30/+46
| | | | | | | | | | | | | | | | | I2C1 may be clocked by HSI or SCLK. I2C2 is always clocked by PCLK. Therefore, apply different timing register values according to the selected clock source for a port. BUG=chrome-os-partner:46188 BRANCH=None TEST=Manual on glados_pd. Verify slave i2c communication is functional. Change-Id: Icd2306d25d5863b0fc3379e46885a227efb23cca Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/309781 Commit-Ready: Gwendal Grignou <gwendal@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* cr50: upgrade to the latest FPGA image 20151029_41713@78167Vadim Bendebury2015-10-301-577/+700
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the EC codebase to match the latest USB build which now provides ability to programatically tell between different FPGA flavors. It also changes the polarity of the 'cold bootsrap' pin, so using the latest spiflash utility is mandatory. Note that there has been no signer changes. BRANCH=none BUG=none TEST=as follows: - programmed the FPGA, it now reports the following when reset: FPGA |20151029_041713@78167 - booted the new image using the latest spiflash version. Note that the bootrom now reports the FPGA image it comes from - disconnected the FPGA upgrade port, rebooted the device, entered on the device console: > spstp off > spste run on the workstation: $ examples/spiraw.py -l 10 -f 800000 FT232H Future Technology Devices International, Ltd initialized at 857142 hertz and observe on the DUT console: Processed 10 frames rx count 11574, tx count 5497, tx_empty 10, max rx batch 11 > Change-Id: I66596061731d9abcf41c5f5984ac479bbc1648e8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/309963 Commit-Ready: Vadim Bendebury <vbendeb@google.com> Tested-by: Vadim Bendebury <vbendeb@google.com> Reviewed-by: Ewout van Bekkum <ewout@google.com> Reviewed-by: Nagendra Modadugu <ngm@google.com>
* it8380dev: gpio - remove comment about E4Dino Li2015-10-251-2/+0
| | | | | | | | | | | | | | | | | E4 pin has two output options, INTC WKO25 and WKO114. We can use any of them. So we enable E4's output to INTC WKO114. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make buildall -j Change-Id: I1c24d3f5aa7c5ca0fc90fcafc3f0a5edc237ce53 Reviewed-on: https://chromium-review.googlesource.com/307215 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: Increase DLM sizeDino Li2015-10-252-10/+10
| | | | | | | | | | | | | | | | 1. Total DLM size is 48KB. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=DLM 0x84000 ~ 0x8BFFF read/write OK. Change-Id: I2340aeefca60ad59062254ddd363c703c30cfd24 Reviewed-on: https://chromium-review.googlesource.com/307006 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix clock moduleDino Li2015-10-258-29/+346
| | | | | | | | | | | | | | | | | | | | 1. Implement deep doze mode for CONFIG_LOW_POWER_IDLE. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=test the following items in deep doze mode. 1. WUI interrupts wake-up OK. (For example, power button, lid, uart rx, keyboard ksi, and so on) 2. LPC access interrupt wake-up OK. 3. Enabled Hook debug, no warning message received (48hrs). Change-Id: I8702a112632cb6c1c0fa75d682badf272130a7d4 Reviewed-on: https://chromium-review.googlesource.com/307060 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: remove unnecessary delay in phy initAlec Berg2015-10-231-1/+1
| | | | | | | | | | | | | | Remove unnecessary 250ms delay in USB PD phy init BUG=none BRANCH=none TEST=test on glados and samus. verify we negotiate with zinger after EC or PD reboots. Change-Id: I561e41fb0b8bbfeacdd7d6a9ceaf67a1606f65e5 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308535 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* oak: stm32f0: implement i2c_set_timeoutRong Chang2015-10-231-1/+16
| | | | | | | | | | | | | | | EC communicates with PD through I2C host command. This CL adds i2c_set_timeout implementation. BRANCH=none BUG=chrome-os-partner:41608 TEST=manual build and load on oak, check PD host command. Change-Id: I05259b40223b435eaf2a0c38954573e97ea4b32b Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306909 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Cr50: Support USB on 15MHz FPGA imageBill Richardson2015-10-222-13/+152
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latest Cr50 FPGA release runs at 15MHz, but supports USB operations. This CL includes changes to make that work. Specifically: * Enable the security features and select the correct PHY * Adjust the turnaround time for the slower clock speed * Handle the SET ADDRESS command specially for this SoC * Remove all printfs from interrupt handlers (but add #ifdef code to print debug messages later if desired). BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual test of Cr50 USB: 1. Plug into a USB jack on a Linux host. 2. In src/platform/ec/extra/usb_console, run make ./usb_console -p 5014 -e 1 3. Type something, hit return 4. See whatever you typed come back with swapped case 5. ^D to quit Change-Id: I848e96d19df056a453d30d4b5537481046fe852d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308062 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Support FPGA image m3.dist_20151021_054409Bill Richardson2015-10-221-2399/+2559
| | | | | | | | | | | | | | | | This enables support for a new FPGA image with tighter timing constraints. Some USB functions perform better using this model. There are also changes to the signing code. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall Change-Id: I608c2424d76b4ea566bf56fa0fed3810436216bb Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308063 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* nuc: Remove unnecessary NPCX_EC_FLASH_SIZE definition in npcx.Mulin Chao2015-10-192-18/+11
| | | | | | | | | | | | | | | | | | | Remove NPCX_EC_FLASH_SIZE definition and replace it with CONFIG_FLASH_SIZE. Due to inconsistence between NPCX_EC_FLASH_SIZE and CONFIG_FLASH_SIZE, some flash commands such as flasherase will cause unexpected results. Modified drivers: 1. config_flash_layout.h: Remove NPCX_EC_FLASH_SIZE definition. 2. flash.c: Replace NPCX_EC_FLASH_SIZE with CONFIG_FLASH_SIZE. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Idca286eef5bb014d5c4cd689c39635e09f40ee03 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/307004 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Abort curr DMA xfer in dma_disable_all().Aseda Aboagye2015-10-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | | When we call dma_disable_all(), we should abort any current transaction on a channel in addition to disabling the channel. Simply disabling the channel will ignore any future requests, but a DMA operation may be ongoing. Lastly, soft-reset the block so that it's a clean state next time we want to use it. BUG=None BRANCH=None TEST=Enable CONFIG_REPLACE_LOADER_WITH_BSS_SLOW on GLaDOS and add a few items to the section. 'sysjump' between RO and RW a few times without encountering a forced hard fault. TEST=make -j buildall tests Change-Id: Ia05702b928fbb12265b16d785b6e6dac09807582 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/306915 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Change the Port 80 task to a timer IRQ.Aseda Aboagye2015-10-193-3/+87
| | | | | | | | | | | | | | | | | | | | | | The port 80 task just polls every 1ms until disabled when the system goes into suspend. Therefore, this commit configures a 1ms timer interrupt that will be used for the port 80 writes instead of using an entire task. This saves task stack space as well as context switches. BUG=chrome-os-partner:46062 BUG=chrome-os-partner:46063 BRANCH=None TEST=Flash GLaDOS and verify using the `port80' console comamnd that there are bytes in the port80 history. TEST=make -j buildall tests Change-Id: I65b48217a638c1f6ae1ac86471f9a98e0ec4533a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305591 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32f05x: Use correct erase block size of 1kBAlec Berg2015-10-191-1/+1
| | | | | | | | | | | | | | Change erase block size to the correct 1kB. BUG=chrome-os-partner:41959 BRANCH=none TEST=with following CL, test software sync to PD MCU on glados. Change-Id: I6252e6344e50f00249ab105a90febd15599c936f Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/307042 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add synchronous debug printfAlec Berg2015-10-193-0/+132
| | | | | | | | | | | | | | | | | | Allow use of a synchronous debug printf instead of using the full console task to save space. This can be turned on with CONFIG_DEBUG_PRINTF, and will provide essentially a one-way console for debugging. This is essentially expanding upon the debug_printf work done for zinger. BUG=chrome-os-partner:41959 BRANCH=none TEST=tested with following CLs on glados_pd by verifying we get a one-way console. Change-Id: If028b5d873261890de5b270bbc00e06bdcaa7431 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306782 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Cr50: enable modificaton of flash bank 1Bill Richardson2015-10-171-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Security settings prevent flash updates by default. This allows erase and writes to flash bank 1 (0x80000 - 0xbffff). Note that this doesn't allow for execution of any code you might put there. That requires additional steps which are not part of this CL. BUG=chrome-os-partner:44745 BRANCH=none TEST=manual Pick an unused section of flash and use the flasherase and flashwrite commands to test it. The flashwrite command fills a buffer with bytes, counting up (0x00, 0x01, 0x02, 0x03, ...), then writes that buffer to the address given. Note that the "md" command uses the absolute address, while the flash commands use the offset address within the flash memory. For example: > md 0xbb000 16 000BB000: ffffffff ffffffff ffffffff ffffffff 000BB010: ffffffff ffffffff ffffffff ffffffff 000BB020: ffffffff ffffffff ffffffff ffffffff 000BB030: ffffffff ffffffff ffffffff ffffffff > flasherase 0x7b000 0x800 Erasing 2048 bytes at 0x7b000... > md 0xbb000 16 000BB000: ffffffff ffffffff ffffffff ffffffff 000BB010: ffffffff ffffffff ffffffff ffffffff 000BB020: ffffffff ffffffff ffffffff ffffffff 000BB030: ffffffff ffffffff ffffffff ffffffff > flashwrite 0x7b000 0x800 Writing 2048 bytes to 0x7b000... > md 0xbb000 16 000BB000: 03020100 07060504 0b0a0908 0f0e0d0c 000BB010: 13121110 17161514 1b1a1918 1f1e1d1c 000BB020: 23222120 27262524 2b2a2928 2f2e2d2c 000BB030: 33323130 37363534 3b3a3938 3f3e3d3c > md .b 0xbb000 16 000BB000: 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f > Change-Id: Ia9fb6415bcc65ab92cab8132d8cf615215804a6d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306687 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* nuc: Enable JTAG directly by NPCX_ENABLE_JTAG definitionMulin Chao2015-10-172-13/+13
| | | | | | | | | | | | | | | | | | Enable JTAG functionality by SW without pulling down strap-pin nJEN0 or nJEN1 during ec POWERON or VCCRST reset occurs. Please notice it will change pinmux to JTAG directly. Modified drivers: 1. gpio.c: Remove JTAG0/1 alternative groups and bits from gpio_alt_table 2. jtag.c: Enable JTAG functionality BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Change-Id: I5a664adedeea1c75df37662dc1f3206e90163eeb Reviewed-on: https://chromium-review.googlesource.com/306470 Reviewed-by: Shawn N <shawnn@chromium.org>
* g: implement support for hardware based TRNGVadim Bendebury2015-10-172-0/+23
| | | | | | | | | | | | | | | | The TRNG operation is simple: once started it begins to fill up an internal FIFO with random values. The consumer of these values might have to wait if the next number is not ready yet. BRANCH=none BUG=chrome-os-partner:43025 TEST=with the rest of the patches in place TPM2 gets a stream of random numbers when required Change-Id: I877452733377ec5b179fb6df8581af570b4f3668 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/306689 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mec1322: i2c: Simplify clk duty cycle calculationsShawn Nematbakhsh2015-10-151-11/+6
| | | | | | | | | | | | | | | | | Minimum high / low times are within 50% duty cyle bounds, except for 400KHz low time. With this in mind, simplify the duty cycle calculations and fix off-by-one errors. BUG=chrome-os-partner:46188 BRANCH=None TEST=Verify i2c is still functional on Glados. Change-Id: Ib08ebc06f334f65d2412222bb6c7a45f407b28c4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305577 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32: i2c: Add timings for 8MHz i2cclkShawn Nematbakhsh2015-10-141-4/+18
| | | | | | | | | | | | | | | | | Use the datasheet-specified 8MHz i2c timings, which are different from the 48MHz timings. BUG=chrome-os-partner:46188 BRANCH=None TEST=Probe glados_pd i2c signals, verify that clock isn't stretched ~2us on every bit received by slave. Change-Id: Id6a07bc364163c2efc61c3115043f48a79027010 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/305714 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* glados: kunimitsu: Change image size to 100K.stabilize-smaug-7547.BAseda Aboagye2015-10-132-7/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MEC1322 is optimized for 96k code RAM and 32k data RAM, therefore the default MEC1322 boards should follow this. On GLaDOS and Kunimitsu, we cannot fit all of the data in data RAM, therefore we adjust this boundary slightly. This should not be moved further as this represents when we are truly out of space. 128k image: -3k loader -1k for shmem/panic info -24k RAM for RO/RW -100k for RO/RW .text and .rodata BUG=chrome-os-partner:46058 BUG=chrome-os-partner:46063 BUG=chrome-os-partner:45690 BRANCH=None TEST=make -j buildall tests TEST=Flash GLaDOS, verify AP and EC boot. Change-Id: Ie53ef6dc607333968bee8f296e7c21ed629e357b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305362 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: upgrade to the latest FPGA image (20151012_041715@75660)Vadim Bendebury2015-10-121-350/+525
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the EC codebase to match the suggested USB build. The spiflash utility must come from the same tarball. BRANCH=none BUG=none TEST=as follows: - programmed the FPGA, it now reports the following when reset: boot_rom 20151012_041715@75660 - booted the new image using the latest spiflash version. Note that the bootrom now reports the FPGA image it comes from - disconnected the FPGA upgrade port, rebooted the device, entered on the device console: > spstp off > spste run on the workstation: $ examples/spiraw.py -l 10 -f 800000 FT232H Future Technology Devices International, Ltd initialized at 857142 hertz and observe on the DUT console: Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11 > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I4e21151d03d1050999ea2045b2be4b99886ff15c Reviewed-on: https://chromium-review.googlesource.com/305260 Commit-Ready: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org>
* mec1322: i2c: Disable i2c interrupts after failed waitShawn Nematbakhsh2015-10-081-0/+2
| | | | | | | | | | | | | | | | | If we timeout waiting for an i2c interrupt, we will exit wait_for_interrupt() with the i2c interrupt still enabled. Fix this by explicitly disabling the i2c interrupt before returning. BUG=None TEST=Manual on Glados, verify no i2c errors during normal functionality. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Icd85acb6de1d499a29f33ebda594f739cdf9fd3e Reviewed-on: https://chromium-review.googlesource.com/304841 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cr50: upgrade to the latest FPGA image (20151007_064811)Vadim Bendebury2015-10-071-1147/+1268
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the EC codebase to match the suggested USB build. The spiflash utility must come from the same tarball. BRANCH=none BUG=none TEST=as follows: - programmed the FPGA, it now reports the following when reset: BootRom 0.8.91hw - booted the new image using the latest spiflash version. Note that the bootrom now reports the FPGA image it comes from: BootRom 20151007_064811@75052 - disconnected the FPGA upgrade port, rebooted the device, entered on the device console: > spstp off > spste run on the workstation: $ examples/spiraw.py -l 10 -f 800000 FT232H Future Technology Devices International, Ltd initialized at 857142 hertz and observe on the DUT console: Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11 > Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Iccd8f202493951f803393395273caa83467655df Reviewed-on: https://chromium-review.googlesource.com/304622 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mec1322: Do not set mux mode to GPIO in gpio_set_flags_by_mask()Shamile Khan2015-10-072-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | gpio_set_flags_by_mask() should only set the GPIO flags for a pin. gpio_set_alternate_function() should set all mux modes including GPIO mode for a pin. This bug was uncovered when a glitch was observed on EC's LRESET# pin which reset the LPC bus. The glitch was caused when the LPC interface was re-initialized during execution of EC RW image. While programming the EC pins for LPC interface, LRESET# pin was temporarily converted from LRESET# mode to GPIO mode by gpio_set_flags_by_mask() before it got set back to LRESET# mode by gpio_set_alternate_function() BUG=chrome-os-partner:44993 BRANCH=none TEST=Manually tested on Kunimitsu FAB3. Flashed a coreboot image in which LPC SERIRQ is set to quiet mode and Clock Run is enabled and than confirmed that keyboard is functional. Change-Id: I25865d38bd6b6b5785e4247831722c5a02032138 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/304146 Reviewed-by: Shawn N <shawnn@chromium.org>
* nds32: fix panicDino Li2015-10-071-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support saving panic data for nds32 core. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console commands 'crash' and 'panicinfo'. 2. ectool command 'panicinfo' crash assert ASSERTION FAILURE '0' in command_crash() at common/panic_output.c:162 === EXCEP: ITYPE=1 === R0 00000000 R1 000000a2 R2 00000060 R3 00000000 R4 00080c40 R5 00000000 R6 dead6663 R7 000000a2 R8 00000002 R9 00000000 R10 00081960 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080c60 IPC 000007a2 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_ASSERT Software panic info 0xa2 Rebooting... panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=1 === R0 00000000 R1 000000a2 R2 00000060 R3 00000000 R4 00080c40 R5 00000000 R6 dead6663 R7 000000a2 R8 00000002 R9 00000000 R10 00081960 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080c60 IPC 000007a2 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_ASSERT Software panic info 0xa2 > crash divzero === EXCEP: ITYPE=10003 === R0 00000000 R1 00f02705 R2 00000060 R3 00081a09 R4 00000000 R5 00000000 R6 00000001 R7 00080cc0 R8 00000002 R9 00000000 R10 00081961 R15 00000000 FP 00000000 GP 000818d8 LP 00009bce SP 00080c90 IPC 00009bee IPSW 70009 SWID of ITYPE: 1 Exception type: General exception [Arithmetic] Exception is caused by a data memory access Rebooting... panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=10003 === R0 00000000 R1 00f02705 R2 00000060 R3 00081a09 R4 00000000 R5 00000000 R6 00000001 R7 00080cc0 R8 00000002 R9 00000000 R10 00081961 R15 00000000 FP 00000000 GP 000818d8 LP 00009bce SP 00080c90 IPC 00009bee IPSW 70009 SWID of ITYPE: 1 Exception type: General exception [Arithmetic] Exception is caused by a data memory access > crash stack +1+2+3+4+5+6+7+8+9+10+11+12+13+14+15+16+17 Stack overflow in CONSOLE task! === EXCEP: ITYPE=8 === R0 00000002 R1 00000002 R2 00000060 R3 00080458 R4 0000ebdd R5 00000000 R6 dead6661 R7 00000002 R8 00000bc8 R9 00000002 R10 00000000 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080448 IPC 00000a92 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_STACK_OVERFLOW Software panic info 0x2 Rebooting... panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=8 === R0 00000002 R1 00000002 R2 00000060 R3 00080458 R4 0000ebdd R5 00000000 R6 dead6661 R7 00000002 R8 00000bc8 R9 00000002 R10 00000000 R15 00000000 FP 00000000 GP 000818d8 LP 0000079a SP 00080448 IPC 00000a92 IPSW 70009 SWID of ITYPE: 0 Software panic reason PANIC_SW_STACK_OVERFLOW Software panic info 0x2 > crash watchdog Pre-watchdog warning! IPC: 00009c6c panicinfo Saved panic data: (NEW) === EXCEP: ITYPE=0 === R0 00000000 R1 00000000 R2 00000000 R3 00000000 R4 00000000 R5 00000000 R6 dead6664 R7 00000000 R8 00000000 R9 00000000 R10 00000000 R15 00000000 FP 00000000 GP 00000000 LP 00000000 SP 00000000 IPC 00009c6c IPSW 00000 SWID of ITYPE: 0 Software panic reason PANIC_SW_WATCHDOG Software panic info 0x0 > Change-Id: I3d491ecd0789335db4633f9bf2ca09cf85503ed9 Reviewed-on: https://chromium-review.googlesource.com/303286 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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