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* cr50: disable error printout on USB_DT_DEBUGNick Sanders2017-09-131-0/+2
| | | | | | | | | | | | | | | | lsusb scans for USB_DT_DEBUG, which produces logspam on the cr50 console. This isn't an error, just unimplemented. Remove the printout. BRANCH=cr50 BUG=b:65407184 TEST=no logspam on lsusb Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: Ib4fc7105015506927f45ee02f587f97e46e1ad9b Reviewed-on: https://chromium-review.googlesource.com/663786 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: Defragment codeRandall Spangler2017-09-091-1/+1
| | | | | | | | | | | | | | | | | For historical reasons, CCD, reset, and power button control were scattered around several files. Consolidate the code in more sensible (in retrospect) places. No functional changes, just moving code. BUG=none BRANCH=cr50 TEST=make buildall; boot cr50 Change-Id: Ic381a5a5d0627753cc771189aa377e88b81b155e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/653766 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* it83xx: i2c: fix i2c stop bitDino Li2017-09-081-13/+14
| | | | | | | | | | | | | | | | | | | | | We disable i2c interface immediately after stop bit is set. This might caused bus busy bit of status register unable to clear (bus busy bit will be set at start condition and cleared at stop condition). So the next transaction, we won't get a good state to start. This change also fix incorrect stop bit for write transaction: IT83XX_I2C_CTR(p_ch) = xx BRANCH=none BUG=none TEST=Ensure i2c interface is disabled after i2c stop condition. Change-Id: I5416bfcef3f95357c6771dead6b0611b908f787e Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/645407 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: clock: support e-flash clock up to 48MHzDino Li2017-09-071-0/+7
| | | | | | | | | | | | | | | | Default setting of embedded flash's clock is 24 or 32 MHz and PLL is 48 or 96 MHz correspondingly. And it8320 supports e-flash clock up to 48 MHz,so we add a new config option to support it. BRANCH=none BUG=none TEST=Run FAFT with e-flash 48MHz and test results are passed. Change-Id: I096ae3abc8fec9bd7e0556c57605e87a31ac3b07 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/645466 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Remove jtag_pre_init()Shawn Nematbakhsh2017-09-0728-266/+125
| | | | | | | | | | | | | | | Use our newly-created chip_pre_init() for doing JTAG initialization. BUG=chromium:747629 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic5771895a214a9f1aa9bd289eef576f52adf973f Reviewed-on: https://chromium-review.googlesource.com/629676 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: restore DATA PID after USB suspend/resumeVincent Palatin2017-09-074-11/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In USB FS on a bulk/interrupt endpoint, the transactions normally toggles between DATA0 and DATA1 PIDs. After a USB suspend/resume cycle, we need to restart from the PID we were at before suspend. In our current code, when going to deep-sleep during USB suspend, we are re-initializing everything when the MCU restarts at each resume. So we set implicitly the PID to DATA0. The USB Hardware IP just silently discards the packet when the PID of an incoming OUT packet is not matching the expectation in the endpoint register. In order to preserve DATA PIDS, record the state of the PID toggling on each endpoint when going to deep-sleep and restore it during the USB initialization. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:38160821 TEST=manual, plug a HG proto2 on a Linux host machine and enable 'auto-suspend' for this USB device. Let it go to sleep and wake-it up by sending a U2FHID request. Repeat the process several times and see that the key answers every time (while it was failing after the second cycle before). Change-Id: I75e2cfc39f22483d9e9b32c5f8b887dbafc37108 Reviewed-on: https://chromium-review.googlesource.com/655238 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Consolidate CCD device enableRandall Spangler2017-09-062-18/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the Cr50 state machines (EC, AP, RDD, bitbang, etc.) manage their own enabling and disabling of the ports (UART, SPI, etc.) This is tricky because the rules for when ports should be enabled are non-trivial and must be applied in the correct order. In additionl the changes all need to be serialized, so that the hardware ends up in the correct state even if multiple state machines are changing simultaneously. Consolidate all of that into chip/g/rdd.c. The debug command for it is now 'ccdstate', which just prints the state machines. This will allow subsequent renaming of the 'ccdopen', etc. commands to 'ccd open', etc. Also include UART bit-banging into that state which must be consistent. Previously, it was possible for bit-banging to leave UART TX connected, instead of returning it to the previous state. Use better names for CCD config fields for UART. I'd had them backwards. BUG=b:62537474 BRANCH=cr50 TEST=manual, with a CR50_DEV=1 image 1) No servo or CCD Pull SERVO_DETECT low (disconnected) Pull CCD_MODE_L high (disabled) Pull EC_DETECT and AP_DETECT high (on) Reboot. RX is enabled even if cables are disconnected so we buffer. ccdstate -> UARTAP UARTEC Pull EC_DETECT low. ccdstate -> UARTAP Pull EC_DETECT high and AP_DETECT low. ccdstate -> UARTEC Pull AP_DETECT high. ccdstate -> UARTAP UARTEC 2) Servo only still allows UART RX Pull SERVO_DETECT high (connected). ccdstate -> UARTAP UARTEC 3) Both servo and CCD prioritizes servo. Pull CCD_MODE_L low (enabled). ccdstate -> UARTAP UARTEC Reboot, to make sure servo wins at boot time. ccdstate -> UARTAP UARTEC Bit-banging doesn't work when servo is connected. bitbang 2 9600 even -> superseded by servo bitbang -> disabled ccdstate -> UARTAP UARTEC 4) CCD only allows more ports and remembers we wanted to bit-bang Pull SERVO_DETECT low. ccdstate --> UARTAP+TX UARTEC+BB I2C SPI bitbang 2 disable ccdstate --> UARTAP+TX UARTEC+TX I2C SPI Reboot and see we don't take over servo ports until we're sure servo isn't present. ccdstate --> UARTAP UARTEC (for first second) ccdstate --> UARTAP+TX UARTEC+TX I2C SPI (after that) 5) Bit-banging takes over ECTX bitbang 2 9600 even bitbang -> baud rate 9600, parity even ccdstate -> UARTAP+TX UARTEC+BB I2C SPI bitbang 2 disable ccdstate -> UARTAP+TX UARTEC+TX I2C SPI 6) Permissions work. Allow easy access to full console and ccdopen: ccdset OpenNoTPMWipe always ccdset OpenNoLongPP always ccdset GscFullConsole always Default when locked is full AP UART EC RO, no I2C or SPI ccdlock ccdstate -> UARTAP+TX UARTEC No EC transmit permission means no bit-banging bitbang 2 9600 even bitbang -> disabled ccdstate -> UARTAP+TX UARTEC But it remembers that we wanted to ccdopen ccdstate -> UARTAP+TX UARTEC+BB I2C SPI bitbang 2 disable ccdstate -> UARTAP+TX UARTEC+TX I2C SPI Try turning on/off permissions ccdset UartGscTxECRx always ccdlock ccdstate -> UARTAP+TX UARTEC+TX No read means no write either ccdset UartGscRxECTx ifopened ccdlock ccdstate -> UARTAP+TX ccdopen ccdset UartGscRXAPTx ifopened ccdlock ccdstate -> (nothing) Check AP transmit permissions too ccdopen ccdset UartGscRxAPTx always ccdset UartGscTxAPRx ifopened ccdlock ccdstate -> UARTAP Check I2C ccdopen ccdset I2C always ccdlock ccdstate -> UARTAP I2C SPI port is enabled if either EC or AP flash is allowed ccdopen ccdset flashap always ccdlock ccdstate -> UARTAP I2C SPI ccdopen ccdset flashec always ccdset flashap ifopened ccdlock ccdstate -> UARTAP I2C SPI Back to defaults ccdoops Change-Id: I641f7ab2354570812e3fb37b470de32e5bd10db7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615928 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* ISH: inclued header for sleep maskKyoung Kim2017-09-061-0/+1
| | | | | | | | | | | | | | | Fix errors due to missing definition of enable_sleep/disable_sleep. BUG=None BRANCH=master Test='make -j buildall' Change-Id: Ia9cb21d8a85241be2d6a675eb4b2c1186aef9d8a Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/651139 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50 updater: reject images with mismatching board IDVadim Bendebury2017-09-054-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in updating the Cr50 to an image which will not be allowed to run due to board ID settings mismatch. This patch modifies the prototype of check_board_id_mismatch() to allow to pass to this function an arbitrary pointer to an image header, so that the function can check not only the image in the flash memory, but also the image which just arrived over the line. The contents_allowed() function now checks if the new image is compatible with the Board ID value in Info1 and rejects the new image if there is a mismatch. BRANCH=cr50 BUG=none TEST=tried updating a Cr50 to an image which is incompatible with the Info1 fields contents. The update attempt is rejected. Verified that updating to a compatible image still works as designed. Change-Id: I3d6c16df11fcabd05888f3cbf5e9a81dc51fe66f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/650812 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: improve update error reportingVadim Bendebury2017-09-052-8/+15
| | | | | | | | | | | | | | | | | | When checking if the new contents are allowed the updater can reject the image for different reasons, let's make it possible to pass the actual rejection reason to the caller of the contents_allowed() function. BRANCH=cr50 BUG=none TEST=verified that attempts to update to an older image are still being rejected with the proper error code (as generated by contents_allowed() now). Change-Id: I24ac7671c4f461ec089f272581723ec2c3a232ff Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/650811 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: bypass for CSAE issue if CONFIG_LOW_POWER_IDLE is disabledMulin Chao2017-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In order to prevent keeping the CSAE bit at 1 forever impacts the eSPI performance, the npcx driver enables host access wakeup functionality before ec enters deep sleep or wfi. But this bypass also should be added in __idle() of core/cortex-m/task.c if CONFIG_LOW_POWER_IDLE is disabled. This CL also narrows the bypass only when host interface is eSPI. BRANCH=eve BUG=b:64730183 TEST=No build errors for make buildall. Disable CONFIG_LOW_POWER_IDLE functionality on poppy and use following script "count=0; while :; do echo "--- iteration --- $count"; time flashrom -p ec -r ec.bin; sleep 1; count=$((${count}+1)); done" to test eSPI performances over 300 times. No errors occur and all tests' efficiency are the same as removing CSAE bypass. Change-Id: I8b6b69e37318208c185747151c06b3e6bdfd2f4e Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/644967 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip/g: use ccd_ext_is_enabled() instead of ccd_get_mode()Randall Spangler2017-09-012-3/+3
| | | | | | | | | | | | | | | | | | | Currently, only usb_pd_protocol.c cares about the actual ccd mode (disabled/partial/enabled). Everything else just cares whether it's enabled or not. So promote the boolean ccd_is_connected() from board/cr50 up to chip/g, and rename it to ccd_ext_is_enabled() to match the new nomenclature (since 'CCD' itself is now too overloaded). This will make it easier to handle CCD state directly in board/cr50 after we split it from common/case_closed_debug.c BUG=none BRANCH=cr50 TEST=make buildall; boot cr50; make sure USB endpoints still work Change-Id: Ic3df7467bfe29f1c5d7060cac1309a1f0e090d9e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648212 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Clean up CONFIG_CASE_CLOSED_DEBUG usageRandall Spangler2017-09-011-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | CCD_CHANGE_HOOK should use CONFIG_CASE_CLOSED_DEBUG_V1. All boards which use chip/g either use both CONFIG_USB_SERIALNO and CONFIG_CASE_CLOSED_DEBUG or neither of them, so just depend on CONFIG_USB_SERIALNO. This is in preparation for making common/case_closed_debug refer only to the usb_pd_protocol version (with mode=disabled/partial/enabled), and cr50 will have its own version (with only enabled/disabled, and tied more closely to CCD config). No functionality changes. BUG=none BRANCH=cr50 TEST=make buildall -j; boot cr50 and see change hook called Change-Id: I1985c8c48c1a85fed4549402a7b47b8a9cf135d7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/648067 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/g: Move Rdd keepalive to chip driverRandall Spangler2017-09-012-23/+24
| | | | | | | | | | | | | | | | | | | | | | | | Previously, chip/g/rdd provided a method for an external console command to override the Rdd cable detect state. But since we'll be refactoring the 'ccd' command, it's tidier to move this to a console command inside the rdd driver itself. BUG=none BRANCH=cr50 TEST=manual, with no debug cable present rdd enable -> Rdd connect rdd -> keepalive rdd disable rdd -> connected (hasn't had a chance to run state machine) (wait <1 sec) rdd -> debouncing (wait 1 sec) -> Rdd disconnect Change-Id: I141eedf8070b4ad2c96cc5a364f4e37dc29bed70 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/647991 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/g: Fix usb_console read-onlyRandall Spangler2017-09-011-4/+14
| | | | | | | | | | | | | | | | | | | | | Currently, the console inhibited output when is_readonly=1, and only inhibited input when is_enabled=0. That's harmless in the current implementation, because common/case_closed_debug() only ever calls it with enabled=0/readonly=1 or enabled=1/readonly=0. But if we ever do decide to use enabled=1/readonly=1, that would have acted like write-only, not read-only. Fix that. BUG=none BRANCH=cr50 TEST=Attach to cr50 USB console, console is read/write. Hack USB console to set is_readonly=1, console is read-only. Change-Id: I04258fe2b040a00f98067d8be48a0632eb16e9c1 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/647336 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/stm32/usb_hid_keyboard: implement keyboard backlight controlWei-Ning Huang2017-09-014-18/+107
| | | | | | | | | | | | | | | | | | | | | | | Implement keyboard backlight control through HID output report. One could enable CONFIG_USB_HID_KEYBOARD_BACKLIGHT to enable keyboard backlight support for a given board. Target board must implement the `void board_set_backlight(int brightness)` function in order correctly set backlight. BRANCH=none BUG=b:37971411,b:63364143 TEST=with follow up CLs 1. `make BOARD=hammer -j` 2. `echo 10 > /sys/class/leds/hammer\:\:kbd_backlight/brightness` console shows 'Keyboard backlight set to 10%' Change-Id: Ibeff510a0d996ddebf61b54ed6b500b02c35564a Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/586348 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ISH: added UART port selectionKyoung Kim2017-09-012-11/+23
| | | | | | | | | | | | | | | | added uart port debug selection. in board.h, add "#define CONFIG_ISH_UART_0" for UART Port 0. For port1, use "#define CONFIG_ISH_UART_1" BUG=None BRANCH=None Test='make -j buildall' Change-Id: I5426b1d228ac715574e2ff4f28526232d375221f Reviewed-on: https://chromium-review.googlesource.com/566593 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ISH: added sleep mask for UART portKyoung Kim2017-08-311-0/+6
| | | | | | | | | | | | | | | added UART sleep mask not to allow to enter into deep sleep. BUG=None BRANCH=master Test='make -j buildall' Change-Id: I15e55c2c94276da99339465f2ea577b1f94e1ce4 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/644848 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* ISH: correction for HPET1 interrupt routingKyoung Kim2017-08-303-7/+10
| | | | | | | | | | | | | | | | | | | -Routing HPET1 timer requires HPET's General Config register's Legacy routing bit should be set. -For HPET0 interrupt, no need to set IRQ# to T0C register. -change IRQ# back to default values. BUG=None BRANCH=master TEST=`Build ISH and verify the timer interrupt via various console cmds` Change-Id: I9f83d62a1f7d999ebf6cedafd38691531ec91081 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/627628 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: Let state machines print their own statesRandall Spangler2017-08-292-9/+8
| | | | | | | | | | | | | | | | | | | Add a function to translate device_state enum into a string, then use it for printing the ec and RDD state. Refactor ec_state so that all state transitions go through a set_state() function, which makes it easier to turn on debugging all state transitions. That's normally not compiled in because it would be spammy during debouncing. BUG=none BRANCH=cr50 TEST=ccd command prints EC and RDD states Change-Id: Ie7bc56c7b66beee23d1d1989711c640e5e39ce43 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/642121 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* EFS: Rename CONFIG_VBOOT_EC to _EFSDaisuke Nojiri2017-08-291-1/+1
| | | | | | | | | | | | | | This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: Change rdd 0.4V ref to 0.3V.Aseda Aboagye2017-08-241-0/+7
| | | | | | | | | | | | | | | | | | | On some boards, it was seen that SuzyQable wasn't detected by the rdd block. The voltage around 0.4V is marginal with a Vbus around 4.75V. This commit simply adjust the 0.4V comparator reference voltage to 0.3V in order to make the detection work. BUG=b:64847312 BRANCH=cr50 TEST=Find a soraka where SuzyQable didn't work. Verify with this patch, it does work. Additionally, verify that servo_v4 continues works. Change-Id: If54630ec469408031cd84ffb93ef5fea42bdee3b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/633403 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: Move chip pre-init to chip_pre_init()Randall Spangler2017-08-244-23/+32
| | | | | | | | | | | | | | | | | | | | Currently, chip/g uses jtag_pre_init() to do some chip pre-initialization that isn't actually related to JTAG. This has been harmless, but it's currently the only chip which actually does "JTAG" pre-init, and we'd like to get rid of that. So, move that functionality to a new optional chip_pre_init() function. BUG=chromium:747629 BRANCH=cr50 TEST=make buildall boot cr50 make all dis; confirm chip_pre_init() is called early in <main> Change-Id: I3cae0747ab0c3cc974fce9f108947207b38e035f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/629876 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Don't enable CONFIG_CMD_FLASH_TRISTATE when internal flash is usedCHLin2017-08-231-0/+3
| | | | | | | | | | | | | | | | | | | The bit controlling the tri-state of FIU pins is reserved when the internal flash is used and should not be modified. This CL adds a compiler error to prevent this kind of misuse. BRANCH=none BUG=none TEST=No build errors for "make buildall". "BORAD=npcx7_evb make" with CONFIG_CMD_FLASH_TRISTATE defined, make sure the error message is printed. Change-Id: I020c8ab9e02b9a377879bbd2a337943e77a369d6 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/624828 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: Refactor Rdd state machineRandall Spangler2017-08-232-33/+195
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code to mirror Rdd detect into CCD_MODE_L and handle keepalive is now inside chip/g/rdd.c It uses a HOOK_SECOND state machine similar to what's coming for EC/AP/Servo. This also removes the explicit 'ccd enable' / 'ccd disable' commands, since they'd be overridden by the HOOK_SECOND handler. If you need to force CCD enabled, use 'ccd keepalive enable'. BUG=b:64799106 BRANCH=cr50 TEST=With a CR50_DEV=1 images: Disconnect CCD cable (pull RDCC1 and RDCC2 outside 0.2-2.0V) gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled Connect CCD cable --> see 'Debug accessory connected' gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled Briefly disconnect and reconnect CCD cable --> No debug output gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled Disconnect CCD cable and wait a second --> 'disconnected' gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled Force CCD_MODE_L = 0 externally, wait a second gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled Stop forcing CCD_MODE_L externally, wait a second gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled ccd keepalive enable gpioget --> CCD_MODE_L = 0 ccd --> CCD enabled ccd keepalive disable gpioget --> CCD_MODE_L = 1 ccd --> CCD disabled Change-Id: I65110b45e76f60390828e0fbbac8f36fc2cc9b37 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/619393 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/stm32/clock: Support RTC console/host commandsPhilip Chen2017-08-233-0/+137
| | | | | | | | | | | | | | | | Add the driver for RTC console/host commands on stm32f0. BUG=b:63908519 BRANCH=none TEST=on scarlet, manually test 'rtc'/'rtc set' on ec console and 'ectool rtcget/rtcset/rtcgetalarm/rtcsetalarm' on ap console. Change-Id: I71035c91ed69fa5f65448618ff8bd1a37427eaad Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/627637 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: log I2C slave 'wedged bus recovery' eventVadim Bendebury2017-08-231-0/+6
| | | | | | | | | | | | | | | | We want to be able to collect statistics of the i2c bus problems. This patch logs an event each time the wedged bus recovery happens. BRANCH=cr50 BUG=b:63760920 TEST=with the upcoming patches verified that i2c recovery events are logged as expected. Change-Id: I1241b2dece33f89cd724d53a48f94e17f4415c62 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/620114 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip/stm32/i2c-stm32f0: Further adjust 400kHz setting (48Mhz clock source)Nicolas Boichat2017-08-231-1/+1
| | | | | | | | | | | | | | | | | | It turns out SCLH = 0x5 is still a little fast (411 kHz on hammer), let's update it to 0x6. See 5e6f9a2b38 "chip/stm32/i2c-stm32f0: Adjust 400kHz setting (48Mhz clock source)" for details. BRANCH=none BUG=b:36172041 TEST=Measure I2C speed to be <400 kHz on hammer Change-Id: I2b5acc532963c407144b8e2a7786d3e2302192d3 Reviewed-on: https://chromium-review.googlesource.com/625507 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Toshak Singhal <toshak@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_hid_keyboard: Add support for boot protocol reportNicolas Boichat2017-08-231-7/+19
| | | | | | | | | | | | | | | | | | | | | | | | In boot protocol mode, we must only send the first 8 bytes of the report. Also, go back to report mode on USB reset. When mode is changed, we immediately toggle keyboard endpoint, to make sure the appropriately sized packet is sent (otherwise, a longer packet packet will be sent once, which confuses AP firmware). BRANCH=none BUG=b:62004286 BUG=b:64953295 TEST=Flash hammer, check that keyboard works at firmware screen and in the OS, and that new key works in OS. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: If7d6aa6c2dd127b9de34fc93d06bc0dd6e6128a2 Reviewed-on: https://chromium-review.googlesource.com/627344 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: bypasses for SHM reading fail via eSPI and CSAE impact efficiencyMulin Chao2017-08-212-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In eSPI systems, when the host performs a data read from the Shared Memory space, the returned data may be corrupted. This is a result of the Core-to-Host access enable bit being toggled (by toggling CSAE bit in SIBCTRL register) during an eSPI transaction. The bypass for this symptom is to set CSAE bit to 1 during initialization and remove the toggling of CSAE bit from other EC firmware code. But keeping the CSAE bit at 1 forever also impacts the eSPI performance a lots. When the core clock is stalled by sleep, deep sleep or wfi instruction, the eSPI Peripheral Channel transaction is stalled if this bit is set. The bypass for this symptom is to wake up the core by eSPI peripheral channel transaction and let eSPI module handle the remaining packet. BRANCH=eve BUG=b:64730183 TEST=No build errors for make buildall. Flash poppy ec image, make sure it can boot to OS. Run "ectool version" over 100000 times, no error occurs. Use following script "count=0; while :; do echo "--- iteration --- $count"; time flashrom -p ec -r ec.bin; sleep 5; count=$((${count}+1)); done" to test eSPI performances over 1000 times. No errors occur and all tests' efficiency are the same as removing CSAE bypass. Change-Id: I1b9051c5a3d368a5917882d9d1c3bb00481a53ad Signed-off-by: CHLin <CHLIN56@nuvoton.com> Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/620301 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32: add embryonic support for STM32F76xVincent Palatin2017-08-186-12/+134
| | | | | | | | | | | | | | | | | | | | | | | The STM32F76x is really close to the STM32F4 family, so the most concise implementation is just using CHIP_FAMILY_STM32F4 and adding CHIP_VARIANT_F76X. Tune the clock settings to 180 Mhz CPU clock as the goal is performance. (over-drive is not implemented yet to get to 216 Mhz) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=ran on nucleo-f767zi board. 'make BOARD=nucleo-f767 flash', the red LED is on and the green LED turns on/off when pressing the user button, UART console works properly. Change-Id: I1f67df3aec874c965c81188df46c72de210728d9 Reviewed-on: https://chromium-review.googlesource.com/612750 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: remove stm32f4 dead code in DMAVincent Palatin2017-08-181-33/+1
| | | | | | | | | | | | | | | | | | The STM32F4 family is building a special variant of the dma code (dma-stm32f4.c), all the conditionals for F4 in stm32/dma.c are just dead code. remove them. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall Change-Id: Icbf8d08c7e50fe5153a1b3830011bb12afcabaa5 Reviewed-on: https://chromium-review.googlesource.com/621391 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* g: add 'recover hosed slave' i2cs capabilityVadim Bendebury2017-08-172-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A common failure condition on the i2c bus is when the master unexpectedly stops clocking the bus while the slave is driving the SDA line low. In this case the master is not able to issue Stop or Start sequences, which makes the bus unusable. Good slave controllers are able to detect this condition and recover from it by removing the pull down from the SDA line. This patch adds this capability to the g chip i2c slave controller. A new timer function is created which samples the SDA line twice a second. If it detects that SDA is low in two consecutive invocations and the number of i2cs read interrupts has not advanced, it decides that the "hosed slave" condition is happening and reinitializes the i2c driver, which removes the hold from the SDA line. Even though the state of the SDA line is supposed to be accessible through the I2CS_READVAL register, it in fact is not, reads always return zero in the SDA bit. To work around this a GPIO (port 0, bit 14) is being allocated to allow to monitor the state of the line, it is multiplexed to the same pin the SDA line uses. When the AP is in low power modes the SDA line is held low, this state should not trigger i2c reinitializations. CQ-DEPEND=CL:616300 BRANCH=none BUG=b:35648537 TEST=connected H1 on the test board to an I2c master capable of stopping clocking mid byte. Observed that the existing code would just sit in the "hosed" state indefinitely. The code with the fix recovers from the condition (drives the SDA line high) 500ms to 1s after the failure condition is created. Change-Id: Iafc7433bbae9e49975a72ef032a923274f8aab3b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/614391 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: add delay after soft resetMary Ruthven2017-08-171-0/+9
| | | | | | | | | | | | | | | | Add a delay to allow the clocks and usb signals to settle. BUG=b:63767046,b:63867566 BRANCH=cr50 TEST=put the eve ec into hibernate, wait until cr50 enters deep sleep, use the uart to wake it up, and verify that it eventually reenters deep sleep Change-Id: I26463ce3e00996368a791a245b0f9de01737478c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/598448 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: shi: add the support for SHI module version 2CHLin2017-08-174-44/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx7, we introduce an enhanced version of Serial Host Interface (SHI) module. This CL adds the support for it. It includes: 1. Increase the size of IBF/OBF from 64 bytes to 128 bytes. 2. Add IBULVL/IBFLVL2 in SHICFG4/SHICFG5 which can configure at which level the IBF pointer reaches to trigger an interrupt to core. The current setting of these two register fields are: IBFLVL - 64 (half full) IBFLVL2 - 8 (the size of host command protocol V3 header) 3. Dedicated CS high/low interrupts. In old SHI module, the way to generate CS high interrupt event is via EOR bit. However, it has a defect that EOR won't be set to 1 when CS is de-asserted if there is no SHI CLK generated. It makes the handling of glitch condition more complicated. In the new SHI module, we introduce the CS high/low interrupts (by enabling the CSnFEN/CSnREEN) to make it easier to handle the glitch. The new SHI module is enabled during SHI initialization when the chip family is npcx7. BRANCH=none BUG=none TEST=No build errors for "make buildall". Test host command communication is ok between npcx7 EVB and a host emulator. Make sure the glitch condition can be detected and handled. Also test the driver on gru, make sure it won't break the operation of old SHI module. Change-Id: If297fd32a0ec2c9e340c60c8f1942868fa978fbc Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/607812 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: Remove BOARD_AP_USB propertyRandall Spangler2017-08-172-9/+9
| | | | | | | | | | | | | | | | | | | We previously disabled the USB PHY to the AP. But the BOARD_AP_USB property lingered on. Remove the property. Also clean up the idle task deciding when to do utmi wakes. With the AP USB connection disabled, that's only necessary when the debug cable is attached, so we can check that explicitly. BUG=none BRANCH=cr50 TEST=make buildall; boot CR50_DEV=1 image Change-Id: If81a7bcfe845d9d70dcc7e16239244a4f5f2427b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/616301 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Revert "npcx: workaround the bug that SHM data read via eSPI may be corrupted"Nicolas Boichat2017-08-161-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ddbfe690e294e595c6ed3511dcf417410d9b2804. Reason for revert: Causes move cursor movements to be choppy, and device to be very unresponsive during flashrom EC operations. Original change's description: > npcx: workaround the bug that SHM data read via eSPI may be corrupted > > In eSPI systems, when the Host performs a data read from the Shared > Memory space, the returned data may be corrupted. This is a result of > the Core-to-Host access enable bit being toggled (by toggling CSAE bit > in SIBCTRL register) during an eSPI transaction. > > The workaround in this CL is to set CSAE bit to 1 during initialization > and remove the toggling of CSAE bit from other EC firmware code. > (i.e., let the CSAE bit be always 1.) > > BRANCH=none > BUG=none > TEST=No build errors for make buildall. Flash poppy ec image, make sure > it can boot to OS. Run "ectool version" over 100000 times, no error > occurs. > > Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe > Signed-off-by: CHLin <CHLIN56@nuvoton.com> > Reviewed-on: https://chromium-review.googlesource.com/590396 > Commit-Ready: Shawn N <shawnn@chromium.org> > Tested-by: CH Lin <chlin56@nuvoton.com> > Reviewed-by: Shawn N <shawnn@chromium.org> BUG=b:64730183 TEST=flashrom -p ec -r ecr.bin, device still responsive. Change-Id: Idaeef2707df990b2441a77a15807698d41018449 Reviewed-on: https://chromium-review.googlesource.com/618366 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* usb_hid_touchpad: Add touch event to FIFO during suspendNicolas Boichat2017-08-161-17/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | Similarly to what we have done with keyboard events, we put touch events in a FIFO. The AP will need to interpret the timestamp in the events to be able to process the events correctly tough. Resume should typically take about 50ms, so a 8-event long FIFO should be good enough. Also, we bypass the FIFO altogether in most cases, when the USB interface is not suspended. BRANCH=none BUG=b:35775048 TEST=Connect hammer, force autosuspend using: DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct)) echo 500 > $DEVICE/power/autosuspend_delay_ms echo auto > $DEVICE/power/control Look at evtest output. Wait a second, make a swipe, see that events are received in a very short amount of time after resume (every EP interval/2ms), but the event timestamps show that some of them are older. Change-Id: If6ab56396f7d564b19e6c3c528847196ffa4d849 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/612221 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* usb_hid_touchpad: Add timestamp field to touch eventsNicolas Boichat2017-08-161-0/+10
| | | | | | | | | | | | | | | | | | | | | | We use the unofficial, Windows 8, Relative Scan time HID usage (Digitizer page, 0x56) to add timestamps to our HID touchpad events. The timestamps is a rolling, unsigned, 16-bit integer, with a resolution of 100us (so it wraps around every 6.5s). The host will be able to synchronize to that timestamp, resetting an offset every time the touchpad is quiet a certain amount of time (e.g. 1 second). BRANCH=none BUG=b:63685117 TEST=Flash hammer, timestamps are reported in HID descriptor. Change-Id: Ie5d56a9df14e464d2cdcd559f550d6e3cc81961f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/603041 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid_keyboard: Add keystrokes to a FIFONicolas Boichat2017-08-161-41/+163
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Put key events in a FIFO. This is especially useful when USB is suspended, so that we can replay the events on resume. This makes sure that no key strokes are lost on resume from USB autosuspend. We coallesce events happening within some interval (18 ms), greater than EP interval (16 ms) to ensure we cannot have a backlog of keys. The interval must also be short enough to ensure that the intended order of key presses is passed to AP, and that we do not coallesce press and release events (which would result in lost keys). We also discard key events in the FIFO buffer that are older than 1 second. Note that we do not fully drop them, we still update the report, but we do not send the events individually anymore (so an old key press and release will be dropped altogether, but a single press/release will still be reported correctly). BRANCH=none BUG=b:35775048 TEST=Connect hammer, force autosuspend using: DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct)) echo 500 > $DEVICE/power/autosuspend_delay_ms echo auto > $DEVICE/power/control Wait a second, type something quickly, verify that no keys are lost. Change-Id: I64d33c15a39ae33af42039fba62cf4ed3abef462 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/471188 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb_hid_keyboard: Simpler buffer handlingNicolas Boichat2017-08-161-31/+17
| | | | | | | | | | | | | | | | | | As suggested in CL:411741, makes the follow-up CL that buffers key strokes much simpler. We can revisit later if we can still sneak it that change, but, all in all, we can guarantee the same key latency by halving the USB endpoint interval. BRANCH=none BUG=b:35775048 TEST=Connect hammer, keyboard works. Change-Id: I6624fde9bd5561ddceb7ce195470d7af7cca7140 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/471187 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: Replace reset handler by generic event handlerNicolas Boichat2017-08-1620-75/+151
| | | | | | | | | | | | | | | | | | | Some USB interface handlers need to know when USB has been successfully resumed after a wake event. For example, this is useful so that HID keyboard can send the events at the right time. BRANCH=none BUG=b:35775048 TEST=Using USB HID keyboard patches to queue keys in a FIFO: After USB autosuspends, press a single key and hold it. Without this patch the endpoint data only gets reloaded on the _next_ event. TEST=On hammer, I2C passthrough still works. Change-Id: I9b52b9de16767c8a66c702a5ae70369334a3d590 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/569547 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* scarlet: Remap DMA channels for USART1Philip Chen2017-08-151-1/+2
| | | | | | | | | | | | | | | | | | | To enable console with DMA, we need to specifically remap DMA channels for USART1. ch2/3 and ch6/7 are already used by SPI1/2 modules. So we have to remap USART1_TX to ch4 and USART1_RX to ch5. BUG=b:64575809 BRANCH=none TEST=confirm ec console works on scarlet rev1 Change-Id: Ie2bb141c72252aee98e4cd4a284a01b4d57605f4 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/611147 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: Split usb wake handler as a different functionNicolas Boichat2017-08-151-43/+49
| | | | | | | | | | | | | | Indentation is growing out of control, let's move to a separate function so that we can return early. BRANCH=none BUG=b:35775048 TEST=Flash hammer, usb_wake works. Change-Id: I9abf99ff55b3977dfc307fc99aac6f1ab7dd1f6a Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/612922 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: system: Remove useless comparisonMartin Roth2017-08-131-1/+1
| | | | | | | | | | | | | | Because x is unsigned it's always greater or equal to zero. BUG=b:64477774 TEST=Build Change-Id: Iaf62be4aecf2738c123cf062099852a192285751 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606455 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: espi: Remove useless comparisonMartin Roth2017-08-131-1/+1
| | | | | | | | | | | | | | Because m is unsigned, it can't be less than 0. BUG=b:64477774 TEST=Build Change-Id: Iec93f396be1f01bc1c38b3285b93daacff6a15db Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606454 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: espi: Fix errors with unsigned variableMartin Roth2017-08-131-2/+4
| | | | | | | | | | | | | | | | Because sig_idx was declared as uint8_t, if espi_vw_get_signal_index() returned an error value of -1, it wouldn't get caught. This would cause the arrays to access the wrong locations later. BUG=b:64477774 TEST=Build Change-Id: Ibe21d51c00ae3511a66a6976e18495c3f7683a78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606453 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb_api.h: Stub usb_wake if CONFIG_USB_REMOTE_WAKEUP is not definedNicolas Boichat2017-08-122-4/+0
| | | | | | | | | | | | | | Removes clutter in callers, so that they do not have to wrap usb_wake calls around ifdefs. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I8641cb7aff702920aaa119e644dc812d5c3e774b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/612220 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: Merge CCD device handling to rdd.cRandall Spangler2017-08-081-8/+0
| | | | | | | | | | | | | | | | | | | | | The device_state module is used for debouncing GPIO inputs to determine device sstate. It was overkill for managing the CCD cable (RDD) attach/detach state, and split that handling between 3 files (board.c, rdd.c, device_state.c). Move all of that logic into rdd.c so it's easier to maintain. BUG=none BRANCH=cr50 TEST=manual plug in CCD cable (or ground DIOM1) ccd command reports cable connected and AP UART TX+RX unplug CCD cable (or un-ground DIOM1) ccd command reports cable disconnected and AP UART disabled Change-Id: Id8fcd3a51605ae7a4843668ea18dd0ef84aceb2c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/604499 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/host/config_chip: Fix TASK_STACK_SIZE of the host board.Che-yu Wu2017-08-081-0/+3
| | | | | | | | | | | | | Define TASK_STACK_SIZE as standard value 512 for the host board. BUG=chromium:752923 BRANCH=none TEST=make runtests Change-Id: I3e5120847e9b14fbf96d00c428b2db9d59d38fe2 Signed-off-by: Che-yu Wu <cheyuw@google.com> Reviewed-on: https://chromium-review.googlesource.com/604850 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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