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* npcx: Touch watchdog during initDuncan Laurie2018-04-091-0/+4
| | | | | | | | | | | | | | | | | | Touch the watchdog during init to prevent it from firing prematurely during HOOK_INIT processing before the tasks are started and watchdog_reload() will be called with HOOK_TICK. BUG=b:77336348 BRANCH=eve,poppy,fizz,reef,kevin TEST=run stress test for several days: while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done Change-Id: I79e744a4678ab1808870d0e7647d2ce273ddeb8f Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/1001532 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: watchdog: disable ITIM16 before updating ITCNT registerMulin Chao2018-04-091-0/+2
| | | | | | | | | | | | | | | | | | | | | During watchdog initialization, the driver doesn't disable ITIM16 module which used for detecting watchdog timeout before updating new preload value. Although the ITEN bit on reset is zero, it caused preload value is not updated to module successfully since ITEN won't be reset (ITIM16 is still enabled) in sysjump case. Despite WDCNT will be reloaded by touching watchdog in HOOK_TICK hook function later, it's better to disable any ITIM16 module before updating ITCNT register. BRANCH=none BUG=b:77336821 TEST=No build errors for npcx5 series. Change-Id: I19baa47bca347b9dca2fc1dcaacca81519facf21 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/999458 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: add Make variable for controlling blob swappingVadim Bendebury2018-04-071-0/+5
| | | | | | | | | | | | | | | | | | | The upcoming cr50-codesigner change will allow to use it for swapping arbitrary blobs in the Cr50 image before signing. Let's use this feature to replace test RMA public key with the prod one. BRANCH=cr50, cr50-mp BUG=b:73296144 TEST=with the rest of the patches in place verified that invoking make with CR50_SWAP_RMA_KEYS=1 causes swapping the RMA public key in the generated image. Change-Id: I4c9994c1a542f456b24d2066ecada9f92f1bfaf3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/996514 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: use codesigner from chrootVadim Bendebury2018-04-051-6/+2
| | | | | | | | | | | | | | | | | Source code for Cr50 codesigner has been added to the chroot and the executable is installed as /usr/bin/cr50-codesigner when cros sdk is created/updated. Let's use the 'official' version instead of outdated local one. BRANCH=cr50,cr50-mp BUG=b:73296144 TEST=verified that properly signed Cr50 images can be built. Change-Id: Ibc68340a26011c7d5ac028bbee73cd0f2c39c291 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/996512 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip/npcx: Ensure software watchdog has highest priorityNicolas Boichat2018-04-0511-40/+40
| | | | | | | | | | | | | | | | | | | | | Before this change uart_ec_interrupt and software watchdog interrupt handler both had priority 0. Since UART IRQ number is 33, and software watchdog is 44, the UART interrupt handler would have higher prority. Fix this by increasing all interrupt handler priorities, leaving the software watchdog handler alone on priority 0. BRANCH=eve,poppy,fizz BUG=b:76391320 TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt handler), check that panicinfo contains a sensible PC in r5 after reset. Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/979738 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: it83xx: remove config option of CONFIG_EC2IDino Li2018-04-032-3/+1
| | | | | | | | | | | | | | | | This is a specific option for it83xx chip and is used to include EC2I module. And we won't need it without LPC module enabled, so just depend on CONFIG_LPC. BUG=none BRANCH=none TEST=make buildall -j, boot to kernel on reef_it8320. Change-Id: I1aa4a182e94d802dbf9ca19cc4a47ef9542d74a7 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/987674 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* g: add caching around modulus loading.Marius Schilder2018-04-033-4/+17
| | | | | | | | | | | | | | | | Approx. 10% speedup on keygen. BRANCH=none BUG=b:68167013 Signed-off-by: mschilder@google.com TEST=buildall -j8; tcg_test passes Change-Id: Icea1628f75f5561130c3e56fee48cc6cbde046d0 Reviewed-on: https://chromium-review.googlesource.com/990937 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* ite: disable interrupts if no keyboard taskJett Rink2018-04-022-1/+3
| | | | | | | | | | | | We also need to ensure that the interrupts are not firing. BRANCH=none BUG=none TEST=buildall Change-Id: I3311c8667fab2c575ff6bbe8b26b010a3340e600 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/988229
* npcx: lpc: fixed bug that ec gets stuck in lpc_sib_wait_hostxx routines.Mulin Chao2018-04-013-4/+36
| | | | | | | | | | | | | | | | | | | | | | | | | If an ITIM32 timeout event occurred during lpc_sib_wait_host_read_done() and lpc_sib_wait_host_write_done() routines, in rare case, ec might have a chance to gets stuck since ec's interrupts are disabled when CSWR/CSRD bits are high forever. (Normally, CSWR/CSRD bits won't be always high. These bits are high forever also means something wrong on LPC/eSPI bus.) In order to prevent this situation, the CL checks TO_STS bit of ITCTS in these routines. If this bit is set, restoring ITIM32 preload counter value to maximum value and processing overflow will be done by force_time(). BRANCH=eve,fizz,poppy BUG=b:76182199 TEST=No build errors for npcx series. Passed test command of CL 979389 on npcx_evb. No symptom occurred during warm reset stress test on soraka. Change-Id: Ic645f7c5a2a1e49a3c1f3d7e089dd66b4bb75ac6 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/979874 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* g: use reset_count to determine system_rollback_detectedMary Ruthven2018-03-302-17/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the reset count to determine if there was a rollback in system_rollback_detected. Before system.c was checking if the inactive header was newer than active one to determine if the system rolled back. This wasn't accurate. Cr50 rollback isn't the only reason why a newer image may be rejected. The image may have been rejected because it wasn't signed correctly or it's corrupted, so we shouldn't be using the newer header as a sign that there was a rollback. The reset count is cleared when the AP boots. This means the rollback state will be lost the first deep sleep resume after the AP has booted. BUG=none BRANCH=cr50 TEST=manual flash a dbg image with version 4.0 that has two infomap bits erased. Check sysinfo to see that it doesn't think cr50 rolledback flash a dbg image with version 4.4 that has one infomap bit erased. Make sure that 4.4 image is rejected and cr50 is still running 4.0 Check sysinfo to see that it doesn't think cr50 rolledback flash a dbg image with version 4.4 that has two infomap bits erased. Make sure cr50 jumps to that image rollback to the 4.0 image Make sure sysinfo shows there was a rollback. Boot the system Make sure sysinfo shows there was a rollback. Change-Id: I85f2e001ffed9e2185a276dfa916e9b0a05ff7bf Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/985029 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cleanup: it83xx: don't enable non-essential modules at defaultDino Li2018-03-291-3/+0
| | | | | | | | | | | | | We let board-level code to enable them if needed. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I9369e33ee1821125cf8719a0c3526afaf294da80 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/985346 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ite: exclude keyboard interrupts if no keyboard taskJett Rink2018-03-293-7/+8
| | | | | | | | | | | | | | | | | | | When building the `tests` target for a specific board that uses the ite EC chip, it will fail to find the lpc_kbc_obe_interrupt function. Adding #define around code similar to npcx set up. This is needed because the unibuild system uses the tests target when compiling chromeos-ec. BRANCH=none BUG=b:77274422 TEST=Can now successfully `make BOARD=bip tests` Change-Id: I971aebe1667eb90e8ccccbe6047c5aa959c76c4b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/986634 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* sweetberry: add current and voltage loggingNick Sanders2018-03-282-37/+118
| | | | | | | | | | | | | | | | | | | | | This adds a config to specify whether sweetberry should measure power, current, voltage per powerlog entry. The json format is slightly revised to allow data type per channel. powerlog and sweetberry fw are updated to handle the new functionality. BUG=b:72973433 BRANCH=None TEST=./powerlog.py -b marlin.board -c marlin_a.scenario -s .5 Signed-off-by: Nick Sanders <nsanders@chromium.org> Change-Id: I231fc6600495146fad30583872bf14c660d5a50b Reviewed-on: https://chromium-review.googlesource.com/905427 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Mengqi Guo <mqg@chromium.org>
* chip/ite: add ADC constantsJett Rink2018-03-281-0/+5
| | | | | | | | | | | | | | | Add ADC constants to ITE driver to match existing driver style BRANCH=none BUG=none TEST=none Change-Id: I7e101a26b81d0cd5ffd50f94c18f20335df06c67 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/982560 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Dino Li <Dino.Li@ite.com.tw>
* g: add stream sniffing for DUT spiflash content.Marius Schilder2018-03-271-0/+11
| | | | | | | | | | | | | | | | | Use the stream signing mechanism to hook outgoing spiflash content. This is (only?) used by Mn50 during chip production flows. BUG=None BRANCH=none TEST=make buildall -j8 Signed-off-by: mschilder@google.com Change-Id: Iccfee173865f587f088a31fcbc7b939823884c31 Reviewed-on: https://chromium-review.googlesource.com/981892 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: add missing define for UART register UART_VAL.Marius Schilder2018-03-271-0/+1
| | | | | | | | | | | | | | | Holds most recent 16 oversampled values of rx and cts inputs. Signed-off-by: mschilder@google.com TEST=buildall -j8 BUG=None BRANCH=None Change-Id: I798b8c2ba645712600d7634769f418d81dec5f79 Reviewed-on: https://chromium-review.googlesource.com/981775 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* lpc: remove lpc_host_resetJett Rink2018-03-263-59/+0
| | | | | | | | | | | | | | | | | No one is using this method and it implies that all chipset should support the RCIN# Virtual Wire if using eSPI. Only large core chips use RCIN#; small core chips don't. This method was introduced for skylake and has since been replaced since CL:575947 was merged. BRANCH=none BUG=none TEST=build all Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/975904
* Add config for boards that cannot distinguish reset typeDuncan Laurie2018-03-261-4/+2
| | | | | | | | | | | | | | | | | | | | We have a growing list of boards in chip/npcx/system.c that are unable to distinguish a reset from a power-on or a reset-pin type. Instead of being a temporary issue this is now solidified in the design on some kabylake boards. Instead of defining board-specific checks in the chip code this change adds a config option that the relevant boards can define. BUG=b:76232539 BRANCH=none TEST=make -j buildall passes Change-Id: I76e0f011d70ce6f778b1fb6a56c2779c39c3cbd6 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/979575 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_LVijay Hiremath2018-03-241-2/+2
| | | | | | | | | | | | | | | | | Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel chipset variants have same GPIO name for doing SOC internal reset. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974241 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* i2c(npcx): Replace cprints by cputs/cprintfNicolas Boichat2018-03-171-8/+9
| | | | | | | | | | | | | | | | | These print-outs are usually very deep in the call stack (rare error cases that do not happen often), and therefore are the longest branches on most tasks. Replacing cprints by cputs/cprintf helps with that. BRANCH=none BUG=b:75234824 TEST=make BOARD=soraka SECTION=RW analyzestack | grep Task shrinks significantly (more than 100 bytes on some tasks) Change-Id: I7c5bb750f4aa624cd06736e0bb6b24d307fc0196 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/966041 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* console: Fix help for parse_boolEdward Hill2018-03-161-2/+2
| | | | | | | | | | | | | | | A few commands had help text of "[0 | 1]" but parse_bool() doesn't recognize 0 and 1. Change help text to "[on | off]", matching other commands. BUG=b:75302458 BRANCH=none TEST=none Change-Id: I9b1e4a70e024d17ec8bccc015069e31d7fff08ca Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/967248 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* servo_micro: switch parity to 8 bit dataNick Sanders2018-03-122-2/+11
| | | | | | | | | | | | | | Parity defaulted to 7 bit data, but hammer wants 8 bit. Change servo_micro to match. BRANCH=servo-firmware BUG=b:37513705 TEST=flash_ec -b hammer Change-Id: I91cc126b03c99107084fb0d1d2e90031b2435fe2 Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/952677 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* i2c: npcx: Check that unwedging succeedsSimon Glass2018-03-091-3/+6
| | | | | | | | | | | | | | | | | | | | | | | If the I2C port is completely broken then there is no point in trying to continue with the transaction. This can happen if the pull-ups on the bus are not working because they are in a power domain which is not currently enabled. Check the return value from i2c_unwedge() and return if it doesn't work. Tidy up a few comments at the same time. BUG=b:72129419 BRANCH=none TEST=manually remove the check AP being off in sb_tsi_get_val() and see that it quickly fails now, rather than hanging the EC for a while trying the transaction. Change-Id: I66ab52943459726537dfc74355f8aeaa5817dba5 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/956017 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Aaron Durbin <adurbin@google.com>
* npcx: remove optional CONFIG_PECI since no one is using it with npcxJett Rink2018-03-071-1/+0
| | | | | | | | | | | | | | | | | | | Some boards have forgotten to undef CONFIG_PECI but it is benign. This should be an opt-in feature instead of an opt-out feature. No one is using it, so no one will opt-in. BRANCH=none BUG=none TEST=Verified that grunt, kahlee, meowth, and zoombini are not using the PECI bus for Soc temperature via schematics (GPIO81). Other boards are a no-op. See cl:951407 for steps taken to ensure all npcx boards were accounted for. Change-Id: I6ca4b9d22b7cb23c9842729658810ebe165ff6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/951408 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* fan: Allow board to configure fans at run timeDaisuke Nojiri2018-03-062-12/+12
| | | | | | | | | | | | | | | This patch splits struct fan_t into two parts: base configuration and RPM configuration. RPMs are expected to be different from model to model while a base configuration is most likely shared. BUG=b:73720175 BRANCH=none TEST=make buildall Change-Id: Iff17573f110e07e88d097dd848cf91ee98b83176 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949382 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: Conforming CONFIG_UART_HOST define to match intentionJett Rink2018-03-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_UART_HOST is supposed to be defined to the index of the UART we want to use. It is not supposed to be defined as a boolean. Updated npcx and all incorrect uses. BRANCH=none BUG=none TEST=Added the following diff to ensure that everything still built: diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 446baa842..826233744 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -897,6 +897,9 @@ static void lpc_init(void) /* Initialize Hardware for UART Host */ #ifdef CONFIG_UART_HOST +#if !CONFIG_UART_HOST +#error "Fix me" +#endif /* Init COMx LPC UART */ /* FMCLK have to using 50MHz */ NPCX_DEVALT(0xB) = 0xFF; Change-Id: Ia46c7cb86c6040a5c75dddf23d5ccd8e33210581 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949308 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: convert to CONFIG_CHIP_MEMORY_REGIONSVincent Palatin2018-03-054-4/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the former special case for USB RAM Add additional RAM regions for STM32H7. For USB RAM, add an explicit alignment directive to ensure we always meet the 8-byte boundary hardware constraint for the BTABLE. This was already true because we put the .usb_ram.btable section first. I keep this property by alpha-sorting the sections but makes it more explicit by adding a 2-digit numeric prefix: e.g. 00_firstsection, 99_lastsection. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, along with the following CLs, run the firmware with large arrays in special AHB memory regions. TEST=build all targets with and without the patch and verify that all smap files are identical. Change-Id: I9ee7f519a13cb14ba9997220f22180028f9c0175 Reviewed-on: https://chromium-review.googlesource.com/946369 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* config: Rename new key to assistant keyNicolas Boichat2018-03-051-13/+13
| | | | | | | | | | | | | | | Make it clearer what the new key is about. CONFIG_KEYBOARD_NEW_KEY to CONFIG_KEYBOARD_ASSISTANT_KEY. BRANCH=none BUG=none TEST=make buildall -j Change-Id: Ic2db425b40ff8bc612626b6f644463b1f8ec630e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/950263 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32h7: enable the fast PLL on-demandVincent Palatin2018-03-051-23/+3
| | | | | | | | | | | | | | | | | | | | | | | Add a new module ID 'MODULE_FAST_CPU'. When it is enabled with clock_enable_module(MODULE_FAST_CPU, 1), switch the system clocking to the fast 400-Mhz PLL. For now, I consider that a single task/user is calling clock_enable_module(MODULE_FAST_CPU, x), so we don't need to count users (in a complicated atomic fashion). It's good enough for the current use-case and we can add the complexity later if we have a real need. BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, with follow-up CL setting clock_enable_module(MODULE_FAST_CPU,x) around the computation block, see that computations are fast and the clock goes back to HSI after. Change-Id: I2aef3ad673ddbffd6fc64c591c54297e94896fa6 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/945688 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32: crank up CPU PLL frequency to 400Mhz on STM32H743Vincent Palatin2018-03-053-31/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the PLL frequency to 400 Mhz (max value) and the AHB frequency to 200 Mhz. Fix the PLL clocking code for STM32H7 : - fix the frequency computation. - adjust the timer divider depending on the system clock. - the 64Mhz HSI is already setup properly at startup, takes it into account. - set the SPI ports on the fixed 64-Mhz HSI, so clocking changes don't mess up their frequencies or stability. Note: this is just modifying the CPU frequency when the system is clocked by the PLL, by default the system is still clocked by the 64-Mhz HSI. Currently, one have to use the 'clock pll' console command to test this PLL mode, some code will be added soon to switch on-demand for heavy computations. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508, b:72879097 TEST=On ZerbleBarn, do 'clock pll', check 'gettime' against wall clock, run image capture and enrollment. TEST=on ZerbleBarn, verify on the scope that the SPI master frequency is 4 Mhz in both configuration. Change-Id: I92a2216999337cf9831fb5dfc2797ab1cce71a8f Reviewed-on: https://chromium-review.googlesource.com/941226 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Nami: Enable fan featureraymondchou2018-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Enable fan feature and update fan setting. 2. Enable SW and chipset throttle feature. 3. Fix the issue that cannot set fan duty by "fanduty" in EC console. BUG=b:72974136 BRANCH=none TEST=Check fan command(fanduty/fanset/fanauto) in EC console can work and check below condition. 1.AP throttling soft --> Increased temperature to over trigger point, then to check EC notify event in EC console. 2.AP throttling hard --> Increased temperature to over trigger point, then to check EC notify event and CPU_PROCHOT pin status in EC console. 3.Fan controlled in s3/s5 as expected (by EC) --> Check Fan turn off in s3/s5. 4.Fan controlled in S0 as expected (by DPTF) --> Check Fan keep 100% duty and no see DPTF to set fan duty. But fan duty can be control by "fanduty" in EC console. Change-Id: If9fd7f64c123ff54742052b6310023f0d4b0113a Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/906086 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx: Preserve default values of HW_WIREFurquan Shaikh2018-03-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | NPCX7 requires that the HW_WIRE bits 2-0 of VWEVSM2 register are set so that the hardwire signals for SCI, SMI and RCIN are connected to VW input of eSPI_SIF module. NPCX5 did this by default, however NPCX7 has made it configurable. NPCX7 however sets the HW_WIRE bits 2-0 to 1 at reset. So, this change ensures that they are preserved while initializing VWEVSM2 registers BUG=b:74111394 BRANCH=None TEST=Verified that SCI works on glkrvp and meowth with NPCX7. Change-Id: I9da6f45b4aa0b72b68db6192cb7567f09b072f0c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/943801 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* scarlet: Turn off ADC after board version is readPhilip Chen2018-03-023-0/+14
| | | | | | | | | | | | | | | | | | We can turn off ADC after the first successful read for board version. A few milliwatts saved is important when Scarlet is in S3. BUG=b:72160379 BRANCH=scarlet TEST=Try 'version' command a few times on EC console and see correct board version. Change-Id: Id2bef415f161431ed895f49db30d50347479176d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/942377 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Derek Basehore <dbasehore@chromium.org>
* cortex-m: enable I-cache on ARMv7-MVincent Palatin2018-03-022-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARMv7-M ISA defines standard (and optional) mechanism to manage the CPU caches through the SCB (System Control Block) registers. So far, only the Cortex-M7 core implements such as a mechanism (e.g. the Cortex-M4 with caches we have are using a proprietary mechanism for the management). Define the functions to use the I-Cache, and enable them on STM32H7 which is our only supported Cortex-M7 core. The D-Cache mechanism is still To Be Done, as it involves a bit more support in the firmware for the DMA memory areas. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, verify manually that the 'IC' bit is set in the CCR (e.g. 'rw 0xe000ed14' returns 0x60218), and runs some CPU workload without crash and with a speed-up. Change-Id: I6af1021d65048b787630387f7d95797db15d069c Reviewed-on: https://chromium-review.googlesource.com/943445 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: fix RTC configuration on STM32H7Vincent Palatin2018-03-021-2/+0
| | | | | | | | | | | | | | | | | | The DBP bit needs to be set in the PWR_CR1 register before doing the RTC configuration (in order to be able to right RTC registers). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn, dump the RTC_TR register and it is incrementing every second, e.g. 'rw 0x58004000'. Change-Id: I02dc6c6f1852ced934bccf3e401f4fdc1aad57d9 Reviewed-on: https://chromium-review.googlesource.com/941224 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx/fan: Make all fans in RPM mode workDaisuke Nojiri2018-02-281-2/+1
| | | | | | | | | | | | | | | Currently, if there is a fan which isn't in RPM mode, the rest of the fans are not controlled even if they're in RPM mode. This patch gives a chance to all the fans. BUG=b:35543471 BRANCH=none TEST=none Change-Id: I6f930bad313bc2a31497f46647ab2b08e328dfff Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/940813 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx7: WoV: Add support for Wake-on-Voice (WoV) moduleCHLin2018-02-288-4/+3755
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the driver support for the WoV module which inludes the following files: - wov.c - wov_chip.h - apm.c - apm_chip.h It also supports the console commad "wov" which can test different configuration and audio quality by entering different parameters. The detail description of WoV console command is listed below: ------------------------------------------------------------------------ [Note]: Before changing any of settings, please make sure the operation mode is on the "OFF" state. (ie. run the command wov cfgmod off first) . > wov init Initialize WoV interface, including pin mux and interrupt registration etc. > wov mute <enable / disable > mute enable / disable. > wov cfgsrc <mono | stereo | left | right> set audio source, ex: wov cfgsrc left, means audio source from left MIC. > wov cfgbis <16|18|20|24> set audio resolution, ex: wov cfgbit 16 means audio resolution are 16bits. > wov cfgsfs <8000|12000|16000|24000|32000|48000> set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio sampling rate are 48Khz. > wov cfgbck <32fs|48fs|64fs|128fs|256fs> set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs means audio sampling rate are 1536Khz (32*48000). > wov cfgfmt <i2s|right|left|pcma|pcmb|tdm> set I2S but format, ex: wov cfgfmt right means audio I2S format are Right-Justify. > wov cfgmod <off|vad|ram|i2s|rami2s> set audio operation mode ,ex: wov cfgmod i2s means audio output via I2S bus. > wov cfgtdm <0~496 0~496 0~3> set TDM time slot, the first values is left channel delay counter, the second is right channel, and the 3rd is startup counting condition. (chosen LRCK raising or falling edge) . [Note: this command is just working on cfgmod equal to tdm] > wov cfgget retrieve above settings. > wov vadsens (currently not support, reserve for next version) > wov gain (0~31) set audio data gain value, ex: wov gain 10 means setting audio digital gain are 10dB. > wov cfgdck <1.0 | 2.4 | 3.0 > set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock are 2.4Mhz. ----------------------------------------------------------------------- This CL also adds the chip ID (0x24) for npcx7m7w. So the console command "version" can show the chip is npcx7m7w. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function with console commands described above. Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com> Signed-off-by: Simon Liang <CMLiang@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/897314 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* npcx/fan: Avoid turning on disabled fansDaisuke Nojiri2018-02-261-0/+3
| | | | | | | | | | | | | | | Fan enable state is controlled in common/fan.c. This patch prevents npcx fan driver from enabling it. BUG=b:73127788 BRANCH=none TEST=Verify no 'Fan 0 stalled' is printed in S3 and S5. Verify the fan spins in S0. Change-Id: I549253a64c91d8a23bb793c3506b5daf1f7642be Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/937941 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* g: make fw upgrade less chattyMarius Schilder2018-02-261-2/+1
| | | | | | | | | | | | | | | | | | When running w/ blocking usb console output (CONFIG_USB_CONSOLE_CRC) and the host is not polling the console, upgrade will fail. Signed-off-by: mschilder@google.com TEST=buildall -j8; gsctool update succeeds on mn50 BRANCH=none BUG=none Change-Id: I5c09694c146ba0fbf7562b86ab0fad0d578bc5ff Reviewed-on: https://chromium-review.googlesource.com/938392 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Add rw_product_family field to signed_header.h.Jeff Andersen2018-02-261-1/+3
| | | | | | | | | | | | | | | | | This field allows multiple product families to be independently versioned and released, without risk of having one product family's image flashed to another product family's chip. BUG=b:73728151 BRANCH=none TEST=make buildall -J Change-Id: I53f5e5b1e9ac7ea19997f8d1228a568e66c43d39 Reviewed-on: https://chromium-review.googlesource.com/935759 Commit-Ready: Jeff Andersen <jeffandersen@google.com> Tested-by: Jeff Andersen <jeffandersen@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Nadim Taha <ntaha@google.com>
* stm32: trigger watchdog hard reset immediatelyVincent Palatin2018-02-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | When using the watchdog (IWDG) to perform the cold reset, set the Key register to 'RELOAD' (0xAAAA) rather than 'START' (0xCCCC) to ensure that the reset is performed immediately rather than at the end of the current watchdog period (which might be 1 to 5s away). Replace the Key register special values by their symbolic constants. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=On ZerbleBarn using a STM32H7, run 'ectool reboot_ec cold' and see the MCU rebooting immediately rather than after 5s. Change-Id: Ib49c703e3ec973389e4d774eda53f3be7ec4dd2e Reviewed-on: https://chromium-review.googlesource.com/936764 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* g: add CONFIG_USB_CONSOLE_CRCMarius Schilder2018-02-241-0/+23
| | | | | | | | | | | | | | | | | This option will cause usb console output to block and also compute a crc32. Signed-off-by: mschilder@google.com TEST=make buildall -j BRANCH=none BUG=none Change-Id: Icf66d5ddbea52008a9c97094e7c83194caa7db79 Reviewed-on: https://chromium-review.googlesource.com/936281 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: optionally check board_id match at upgrade timeMarius Schilder2018-02-231-0/+17
| | | | | | | | | | | | | | | | | | CONFIG_IGNORE_G_UPDATE_CHECKS currently drops all upgrade checks. Now with CONFIG_BOARD_ID_SUPPORT only check for board_id match. CR50_DEV still retains full no check behavior. TEST=buildall -j8 BRANCH=none BUG=none Change-Id: I0d085a26c814cd0f35450f0a0db06fe8525ab896 Reviewed-on: https://chromium-review.googlesource.com/933589 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: use single __packed definitionVadim Bendebury2018-02-221-0/+1
| | | | | | | | | | | | | | | | | | | Various parts of Cr50 code and Cr50 related utilities duplicate definition of __packed available in include/common.h. Let's use the same definition everywhere. BRANCH=cr50, cr50-mp BUG=none TEST=make buildall succeeds verified that linker generated map files for Cr50 RW are the same before and after this change. built and used gsctoo and rma_reset Change-Id: Ib91f9bbad1f6822b347f32b393630f592df80d60 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/931929 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32: fix AXI memory corruption on STM32H743Vincent Palatin2018-02-212-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The STM32H743xI Errata document (rev Y) mentions in the paragraph 2.2.15 'Reading from AXI SRAM might lead to data read corruption': """ Read data might be corrupted when the following conditions are met: - Several read transactions are performed to the AXI SRAM, - and a master delays its data acceptance while a new transfer is requested. """ We can actually hit this under a fair interrupt load and two tasks running (e.g polling with the AP with host commands while doing fingerprint image acquisitions). So apply the proposed workaround and limit concurrent read access on AXI master to 1 by setting the READ_ISS_OVERRIDE bit in the AXI_TARG7_FN_MOD register. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:67081508 TEST=on ZerbleBarn or Meowth, run 'ectool fpmode capture vendor', poll in a tight loop with 'ectool fpmode'. No longer see random panics. Change-Id: I6270866b74645d53e4d65f07f65431d5dee11576 Reviewed-on: https://chromium-review.googlesource.com/926009 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: Set ESPI_MAXFREQ based on FMCLK valueFurquan Shaikh2018-02-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | According to NPCX data sheets (NPCX5 and NPCX7), ESPI_MAXFREQ should be decided based on the value of FMCLK. Since we are setting FMCLK to 30MHz on NPCX5, eSPI_MAXFREQ needs to be set to 33MHz. This change sets ESPI_MAXFREQ_MAX depending upon the value of FMCLK. BUG=b:73504527 BRANCH=fizz? TEST=Verified that on soraka ESPI_MAXFREQ is set to 33MHz. Also, ran some reboot tests to ensure that there is no regression in boot time. Change-Id: Iaee89078741cf44c7ac232e2ee14d75384f68a35 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/925843 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: remove set capabilities from powerbtnMary Ruthven2018-02-202-40/+0
| | | | | | | | | | | | | | | | | | | | Cr50 cannot override the state of the power button. It was possible with dev cr50 chips, but the capability was removed in prod chips. Change the console command, so it is only used to get the state of the power button. Remove all of the commands used to override the power button. BUG=b:73557298 BRANCH=none TEST=none Change-Id: I99cb5e8a18dd972fba460c434364702f06a26305 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/926964 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* cr50: fix DEBUG_DRIVE commentBrian Norris2018-02-161-1/+1
| | | | | | | | | | | | | | This is the DEBUG_DRIVE register, not the DEBUG_BLOCK_OUTPUT. Copy/paste error? BRANCH=none BUG=none TEST=none Change-Id: Ic915b8675559d6f43d153f3a309becc621416dbe Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/924698 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* lpc: Removing unnecessary register writesJett Rink2018-02-161-6/+1
| | | | | | | | | | | | | | | | | | | | According to Nuvoton datasheet, when SHM windows are in IO mode, only the bottom 16-bits of registers @ offset xF4 and xF8 are used. "This register is ignored when WRAM1_IO bit in WIN_CFG register is set to 1 (LPC / eSPI Peripheral Channel I/O access with 16-bit address). This register is set to its default value by Host Domain reset." BRANCH=none BUG=none TEST=boot grunt and verify host communication still works. Change-Id: I3e48ea1b09355eaf6967b9f7522bc3d35459b76b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/919006 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: set eSPI speed to max supported by hardwareCaveh Jalali2018-02-152-3/+12
| | | | | | | | | | | | | | | | | | the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up to 66MHz. so, set the max speed to whatever the hardware can actually do. the bit pattern for 66MHz is "reserved" on the npcx7, so let's not even define it in the npcx7 case. BUG=b:72838699, b:71859563 BRANCH=none TEST="make buildall" passes; boots on meowth Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910321 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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