summaryrefslogtreecommitdiff
path: root/chip
Commit message (Collapse)AuthorAgeFilesLines
* hatch_fp: Add RDP (read protection) support to STM32F4Tom Hughes2019-07-244-2/+159
| | | | | | | | | | | | | | | | | | | BRANCH=none BUG=b:125419658 TEST=Remove "-U" flag in STM32MON_READ_FLAGS in flash_fp_mcu_common.sh flash_fp_mcu -r foo.bin => success hexdump foo.bin => valid data ectool --name=cros_fp flashprotect enable ectool --name=cros_fp reboot_ec flash_fp_mcu -r foo.bin => fails Add "-U" flag back to STM32MON_READ_FLAGS in flash_fp_mcu_common.sh flash_fp_mcu -r foo.bin => success hexdump foo.bin => all 0xFF Change-Id: Ic3ec18262e653b72baf239caa8db12186a63613c Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1692220 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: make i2c slave address uint16_t to be standardDenis Brockus2019-07-231-1/+1
| | | | | | | | | | | | | | | | | | | | EC code changed over to a 7-bit slave address and stored in a uint16_t to generically be able to handle 10-bit addresses, if they are ever needed, as well as common bit flags in the most significant bits. This code does not use more than the 8 least significant bits but to be EC consistent, I am making this 16 bits. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ic5f4b3500ae7b3c18380b188efbc37c01d58d7e9 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1714136 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* npcx7: UART: wait for Tx empty before enabling deep-sleepCHLin2019-07-234-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the original firmware (in the uart_buffering.c), it clears the SLEEP_MASK_UART immediately after it pushes all characters from its Tx buffer to UART's FIFO without checking the status of transmission. It may break the transmission because EC goes to deep sleep before UART TX (FIFO or shift register) becomes empty. This CL fixes it by: (1) Don't clear SLEEP_MASK_UART immediately when uart_tx_stop is called. (2) Enable the NXMIP (No Transmit in Progress) interrupt. (3) Clear SLEEP_MASK_UART in the UART interrupt handler when NXMIP is set. This fix only needs to apply to NPCX7 chips which have UART FIFO support. BRANCH=none BUG=b:137143640 TEST=No error for "make buildall" TEST=run 10 iterations of uart_stress_tester on yorp with command: ./util/uart_stress_tester.py /dev/ttyUSB2 -t 360; make sure no character lost in each iteration as below: ... INFO | UartSerial| /dev/ttyUSB2 | Detected as EC UART INFO | UartSerial| EC | Ready to test INFO | ChargenTest | Ports are ready to test INFO | ChargenTest | Test starts INFO | UartSerial| EC | Test thread starts INFO | UartSerial| EC | Test thread is done INFO | UartSerial| EC | 0 char lost / 4147200 (0.0 %) INFO | ChargenTest | PASS: lost 0 character(s) from the test INFO | ChargenTest | Test is done Change-Id: I97b1f572e8b9ebdb5102aa3e98ae2963d768b5b3 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703944 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* ish: fix snowball structure linker placementDenis Brockus2019-07-223-30/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following bug https://buganizer.corp.google.com/issues/136002955 indicates after my initial move of snowball to use the linker map instead of hard defined addresses that 0xFF801E80 was reading back as all zeroes. The change that was made for this is https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593 I double checked the map files and everything looked good. For some reason using the linker to map the location of this structure, the system does not run properly. If I remove the link map placement of this structure then the issue goes away. I looked at how aon_share was placed at the specific address in AON memory and this CL is doing the same thing and it is working. I think this is the way we should keep this fix and not try to get the linker map to place this structure where we want it. BUG=b:136002955 BRANCH=none TEST=make buildall -j TEST=verify soft reboot does not indicate power reset Change-Id: Ibb6dbd3a4414b5c546e99f5ad7e0409250de6256 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1707998 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-2015-153/+153
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-1915-171/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* chip/host: Add spi+trng support, and add gpio funcCraig Hesling2019-07-184-1/+85
| | | | | | | | | | | | | | | | | | | | This adds fake SPI Master and TRNG support to the host target. This change also adds the missing emulated gpio interface function. Although general purpose, these changes are setup for allowing fuzzing of the FPMCU specific host commands. Thus, they do not impact any outstanding code. BRANCH=none BUG=b:116065496 TEST=make buildall -j Change-Id: Icfc40e7bf8ee421a4c3ad15377fd56ae68c763d7 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684223 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Basic implentation of the Maxim Integrated MAX32660 within the EC OSJerry Bradshaw2019-07-1718-0/+6195
| | | | | | | | | | | Includes System Clock, Timer, Uart, Watchdog Change-Id: I195059c87d97e70c6a134304143613b86b623e22 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1647741 Reviewed-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Jerry Bradshaw <jerry.bradshaw@maximintegrated.com> Commit-Queue: Jes Klinke <jbk@chromium.org>
* cr50: provide separate environment variable to enable crypto testsVadim Bendebury2019-07-171-4/+0
| | | | | | | | | | | | | | | | | | | | Presently the CR50_DEV environment variable is overloaded, if its value is a number exceeding 1, it enables inclusion in the image of the dcrypto tests. To make things cleaner let's use a separate environment variable to add dcrypto tests to the image. Note that the tests still can not be enabled, as they do not fit into the flash code space. BRANCH=cr50, cr50-mp BUG=b:137659935 TEST=verified that image building with CRYPTO_TEST=1 fails due to exceeded code size. Change-Id: I550c219c1eefe01fbe035b85a1d5aae88ea439de Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704607 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* mt_scp: Trigger IRQ if has pending IPC when re-enable SCP_IRQ_IPC0.Yilun Lin2019-07-171-3/+18
| | | | | | | | | | | | | | | | | | | | Prevent a starved waiting IPC. IPC may be requested while SCP_IRQ_IPC0 is disabled, and this may result in AP dead waiting for a reply from SCP. This CL forces triggering the SCP_IRQ_IPC0 if seeing a pending IPC when re-enable the SCP_IRQ_IPC0. TEST=run factory front_camera_test for over 1 hr and see AP doesn't complains HC not respsonsed. BUG=b:136809224, b:136616282 BRANCH=None Change-Id: Ic36da774994f6c571c3b79fd6717562f8866b7df Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697884 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org>
* mt_scp: Drop TCM and L1 cache setting.Yilun Lin2019-07-172-8/+11
| | | | | | | | | | | | | | | | | | | | This config has been moved to kernel https://crrev.com/c/1687454 to correctly initialize L1 cache. We should drop the config in SCP side. Also, update the comment for CM4_MOD registers. TEST=Boot SCP with kernel https://crrev.com/c/1627394/10 BUG=b:132658087 BRANCH=none Change-Id: I37613533563acc00017f96a3d3009383057f072b Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703946 Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Erin Lo <erin.lo@mediatek.com> Commit-Queue: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org>
* stm32: Add known variants to registers filesCraig Hesling2019-07-175-0/+21
| | | | | | | | | | | | | | | | | | Although these registers files may support other variants, these listed variants are the only ones that are referenced throughout EC codebase. They were collected using the following grep line: grep -rIi 'variant.*stm32.' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I3691d8db5c2a6c1a94bb5df40edf12504c3fee7e Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700168 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Factor out stm32f7 family registersCraig Hesling2019-07-174-55/+1093
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This extracts the STM32F76X variant from the STM32F4 family registers file. This also removed a redundant #ifdef CHIP_FAMILY_STM32F4 inside the F4 family register file. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash # Make dummy board for STM32F76X using STM32f7 fammily mkdir -p board/usestm32f7 printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f7\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk touch board/usestm32f7/board.h ./registers-extract.bash board-regs-new git checkout cros/master # Change family back to STM32F4 printf "CHIP:=stm32\nCHIP_FAMILY:=stm32f4\nCHIP_VARIANT:=stm32f76x\n" > board/usestm32f7/build.mk ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new # Expect only a difference in CHIP_FAMILY Change-Id: I5ff87e1c82c5d27d78c3ea62fed29d647a0f98db Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1700167 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Add header guard and fix fmt/doc of registers header fileCraig Hesling2019-07-177-260/+347
| | | | | | | | | | | | | | | | | | | | | | | | | | | We enforce that all family specific registers file can only be included from registers.h. We add a brief history and rationale behind splitting registers.h into multiple family specific header files. We fix formatting of preprocessor conditionals and documentation. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash ./registers-extract.bash board-regs-new git checkout cros/master ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new [ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I5d5983eb1e0cf7fb46339cba2987d551ff6b16cc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693879 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Manually fix separate register filesCraig Hesling2019-07-165-92/+4
| | | | | | | | | | | | | | | | | | | | | | This fixes the CPP conditionals that could not be separated using the split script. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash ./registers-extract.bash board-regs-new git checkout cros/master ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new [ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I40eac114cd5ed7abe708cc51242a3b267aaaf118 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693876 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Split registers.h into independent filesCraig Hesling2019-07-157-2706/+6243
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the sort_file.bash script from this bit: http://go/bit/hesling/5840756455505920/7 $ git fetch "https://chromium.googlesource.com/chromiumos/platform/ec" refs/changes/78/1674678/6 && git cherry-pick FETCH_HEAD $ cp registers.h registers-split.h $ ./sort_file.bash chip/stm32/registers-split.h f0=chip/stm32/registers-stm32f0.h f3=chip/stm32/registers-stm32f3.h f4=chip/stm32/registers-stm32f4.h h7=chip/stm32/registers-stm32h7.h l=chip/stm32/registers-stm32l.h l4=chip/stm32/registers-stm32l4.h com=chip/stm32/registers.h Modified registers.h to include chip family specific header file. Modify copyright year of output files. BRANCH=none BUG=none TEST=make buildall -j TEST=Grab registers-extract.bash from http://go/bit/hesling/6385147721023488/4 . chmod +x ./registers-extract.bash ./registers-extract.bash board-regs-new git checkout cros/master ./registers-extract.bash board-regs-original diff board-regs-original board-regs-new [ $? -eq 0 ] && echo "# Good2Go" || echo "# Bad" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: Ia7804e9a346ed94f881bd5583f5a4bf78422cb47 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1674679 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* arcada: ensure i2c transmit fifo is emptyLeifu Zhao2019-07-141-2/+3
| | | | | | | | | | | | | | | | | | | | Make sure transmit fifo is empty before disable i2c controller during transfer, otherwise the i2c write may fail for speed 100k, it also helps 400K and 1M. BUG=b:137218876 BRANCH=none TEST=tested on arcada Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I6f9fb9a71c28f2d3f9696340cc87fe3b72c25a02 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697061 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* ish: fix aon task not auto rebuild issue in increment buildHu, Hebo2019-07-122-13/+37
| | | | | | | | | | | | | | | | | | | | | aon task image build rules are lack of dependent rules of source code, so can't track the source code changes and trigger auto build. Refactor build rules for aon task to make sure always auto rebuild when aon task's source code and dependent header files update BUG=b:136691893 BRANCH=none TEST= ish aon task should always rebuild when it's code and dependent header files update Change-Id: I0d8c7c6a4a2b7e99d724b88b233e09a29b8facea Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688701 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* stm32h7: Fail build if CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE not usedTom Hughes2019-07-111-0/+3
| | | | | | | | | | | | | | | | As comment indicates, we're not sure that using RSS1 for the write protect PSTATE is safe. BRANCH=none BUG=chromium:888104 TEST=In nocturne_fp board.h file: #undef CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE => Build fails with error as expected Change-Id: I0236381738e7ecf9b18a8d10dc7ba4b9dc370001 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693339 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32: Make sure watchdog is enabled when using it to resetTom Hughes2019-07-101-0/+30
| | | | | | | | | | | | | | | | | | | | | On hatch (using hatch_fp), the watchdog appears to never fire when issuing the following commands: ectool --name=cros_fp flashprotect enable ectool --name=cros_fp reboot_ec Adding the explicit enable of the watchdog here fixes that. BRANCH=none BUG=b:137045370 TEST=On hatch: ectool --name=cros_fp flashprotect enable ectool --name=cros_fp reboot_ec Change-Id: Ib42b67a2c88a5c11e3064523d74c9ded51f71379 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1692078 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ish: cleanup i2c constantsJett Rink2019-07-092-21/+26
| | | | | | | | | | | | | | Rename i2c constants to expose the speed they represent. BRANCH=none BUG=none TEST=builds. arcada i2c bus speed is correct Change-Id: If26f4868053f5df0a83bf1f06b62b6969dd5a44f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1691310 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Revert "ish: enter ISH ROM during reset prep"Jack Rosenthal2019-07-091-1/+1
| | | | | | | | | | | | | | | | | | This reverts commit 58f535e8c175311d866d4c1dd2d283d69230e9c5. Now that b:136265450 has an actual fix landed, we need to revert this workaround to reduce power usage when the system is off. BUG=b:136265450 BRANCH=R76,master TEST=press 'shut down' on normally failed DUT, observe ISH come alive at next boot multiple times Change-Id: I623249dfcb697a055378ca721721f346b01b7a8e Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1691116 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* ish: fix osscaisonally not load issue when doing shutdown & rebootHu, Hebo2019-07-081-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Before switch to aon task, cache and ROM will be power gated (PMU_RF_ROM_PWR_CTRL control register) in ecos, and resume after switched back to ecos. But for reset_prep/D3 process, aon task will reset minute ia to ROM finally but forget to resume the power of ROM. This keeps ROM still power gated and make ROM code can't run correctly. The fix is simple, just disable power gating of ROM before reset to ROM in aon task. BUG=b:136265450 BRANCH=none TEST=ISH fw should always load Change-Id: Ib26678bbfdd5dbb17389154478f2565c44d392ab Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684825 Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Yangzhong Ge <yangzhong.ge@intel.corp-partner.google.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* ish: enter ISH ROM during reset prepJack Rosenthal2019-07-041-1/+1
| | | | | | | | | | | | | | | | | | | This is a temporary workaround based on PS1 of Hebo's CL:1684825. The actual fix for b:136265450 should revert this. The cost of this change is higher power usage when the system is powered off. BUG=b:136265450 BRANCH=R75,R76,master TEST=Normally failed DUT comes back alive consistently with this change. Change-Id: I623249dfcb697a055378ca721721f346b01b7a8f Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688142 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* it83xx/register: rename the register of MCCR3 to RVILMCR0Dino Li2019-07-032-5/+5
| | | | | | | | | | | | | | This register is specific to the risc-v core. We only apply the register to risc-v core. BUG=none BRANCH=none TEST=console commands: flasherase and flashwrite Change-Id: I241179170ca1394dca4f7631b266a57f959fe036 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684955 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/i2c_slave: the DMA registers have updated on IT8xxx2tim2019-07-022-5/+33
| | | | | | | | | | | | | | The DMA read and write target address registers have changed. BUG=none BRANCH=none TEST=Testing on IT8320dx and IT83202 EVB. Change-Id: I9e63c3f7f402ed22c461eb86daa5eba0e6dcb58e Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660071 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* mt_scp/ipi: Add ref-counted API ipi_{en,dis}able_irq()Yilun Lin2019-07-022-4/+48
| | | | | | | | | | | | | | | | | | | | | | | Unify IPC IRQ accessing to prevent a wrong IRQ enabling status. An IPC IRQ could be shared across many IPI handlers. Those handlers would usually operate on disabling or enabling the IPC IRQ. This may disorder the actual timing to on/off the IRQ when there are many tasks try to operate on it. As a result, any access to the SCP_IRQ_* should go through ipi_{en,dis}able_irq(), which support a counter to enable/disable the IRQ at correct timeing. TEST=Boot scp. BUG=b:117917141 BRANCH=master Change-Id: I792849279dfeb5231f27fa7a9cf260e2059bbf4b Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1670650 Tested-by: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* chip/stm32/clock: Remove warning message about clock modulesNicolas Boichat2019-07-022-6/+0
| | | | | | | | | | | | | | | | It is not super-useful to print a warning message on every single boot about the fact that some module is not supported, and that takes up a bit of flash space. Let's remove it. BRANCH=none BUG=none TEST=none Change-Id: I04728aa5971675d8e93dcd397ebb259bfdd15bac Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660520 Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ish: arm T1 in __hw_clock_event_clearJack Rosenthal2019-06-271-3/+6
| | | | | | | | | | | | | | | | We need to make sure that process_timers gets called when the event timer rolls over, which is a bug caused by the refactor in CL:1668056. BUG=b:133190570 BRANCH=none TEST=CtsSensorTestCases all passing Change-Id: Ib86ca0a5879476f334588c213cb7a4c732ac3be4 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1678240 Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* ish5: fast 32-bit division in scale_us2ticksJack Rosenthal2019-06-271-1/+18
| | | | | | | | | | | | | | | | | | | The critical section using scale_us2ticks is in __hw_clock_source_set, which we can optimize as this has 32-bit inupts and outputs. Make a separate function for this usage, scale_us2ticks_32, to be used in this critical section. BUG=b:133190570 BRANCH=none TEST=tested outputs of scale_us2ticks_32 to make sure they matched the correct value for 32-bit inputs Change-Id: I4f0f928327cb686006c5ebf4ef17becc5e921d9e Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1677239 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: commit persistent data during d3 entryJack Rosenthal2019-06-275-32/+14
| | | | | | | | | | | | | | | | Refactor D3 entry to use ish_pm_reset, as it performs the same operations modulo the pm_state, save persistent data when entering D3. BUG=b:134089952 BRANCH=none TEST=rmmod ish modules, insmod again on arcada Change-Id: Ifed49d49d42b55cd220ff5d8e8d98843d28dfa22 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1674470 Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* g: avoid CERT_28Marius Schilder2019-06-271-19/+1
| | | | | | | | | | | | | | | | | | | | | | | chip/g has a hardware KI with executing CERT_28 more than 512 times after reset. Current use of CERT_28 makes little sense so we address the issue with deletion. While at it, delete a bunch of other useless code in this function. Ultimately we're left with just pulling bits from TRNG and mixing them with entropy from the keyladder as mild hedge. Signed-off-by: mschilder@google.com BUG=b:127343845 BRANCH=none TEST=b:127343845 Change-Id: I84218f644aa2508c45101464512019754647f229 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646533 Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Commit-Queue: Marius Schilder <mschilder@chromium.org> Auto-Submit: Marius Schilder <mschilder@chromium.org>
* g: try batching USB stream data under heavy loadVadim Bendebury2019-06-272-55/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB TX data rate is much higher than UART RX, this results in USB driver streaming data received from UART in smaller than max size chunks, which in turn means that per byte overhead of shipping USB packets to the host is not as low as it could have been. This patch detects attempt to ship less than full chunk over USB stream and instead of processing data immediately posts a deferred function, which is supposed to triggers another send attempt in a few milliseconds. If there is a high traffic on the stream, the queue would have much more data after deferred interval ends. The problem with the posted deferred function is the fact that it is not guaranteed to run soon enough in case there are other deferred functions waiting. To address this issue an additional check is being introduced to make sure that the USB buffer does not overflow: if the deferred function is posted, and the buffer is half full or more, let's cancel the deferred function and process the stream right away. If the deferred function gets to execute - there is a chance that a UART and or USB interrupt comes while the deferred function is running, which is likely to mess up USB controller settings by tx_stream_handler(). To avoid these issues, interrupts are disabled before the kicker function calls the handler. Note that this optimization applies only to AP and EC console streams. BRANCH=cr50, cr50-mp BUG=b:38448364 TEST=two full chargen streams on an octopus device run indefinitely and don't seem to be interrupting even when some CLI command is ran on the Cr50 console or when an update is uploaded over USB or TPM Change-Id: Id151c494967d1eb15d2af42acf8f2282966b5147 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672209 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: set up USB TX in USB endpoint interrupt handlerNamyoon Woo2019-06-272-25/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB TX used to be set up in a deferred function. This patch makes USB endpoint interrupt handler to setup USB TX to speed up sending data to host USB. It reduces Flash usage by 100 bytes, and RAM usage by 40 bytes. BUG=b:38448364 BRANCH=cr50, cr50-mp TEST=(1) Flashed EC FW on fleex (uut), atlas (npcx_int_spi), ampton (it83xx), bob (npcx_spi), coral (npcx_spi), and scarlet(stm32). (2) Flashed AP FW on fleex. (3) Ran firmware_Cr50DeviceState on Coral. (4) Uart Stress Tester on fleex. [ before applying this CL ] $ uart_stress_tester.sh --pty="/dev/ttyUSB2 /dev/ttyUSB1" --min_char 200000 ........................... ERROR : /dev/ttyUSB2: 1953 lost / 330330 : .5 % ERROR : /dev/ttyUSB1: 451 lost / 200655 : .2 % [ after applying this CL ] $ uart_stress_tester.sh --pty="/dev/ttyUSB2 /dev/ttyUSB1" --min_char 200000 ........................... INFO : /dev/ttyUSB2: 0 lost / 334425 : 0 % INFO : /dev/ttyUSB1: 0 lost / 200655 : 0 % Change-Id: Ic966486f034a199b601ca002f6ed76a73b2b9dd8 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1574661 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chip/stm32/gpio: Disable external interrupts in gpio_pre_initNicolas Boichat2019-06-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | After a sysjump, external interrupts are left enabled. However, exti_events is reset to 0, so upon receiving an interrupt, gpio_interrupt will call the handler for signal 0 (the first GPIO_INT defined in gpio.inc) for these sources. This is obviously very wrong, and the easiest (and most robust) way to fix this is to disable all interrupts on sysjump, and let the new code re-enable if desired. BRANCH=none BUG=chromium:977950 TEST=On kukui, with following CL, trigger a watchdog (stop daisydog; echo > /dev/watchdog), see that no interrupt is generated. Change-Id: Ic55262f8b8dd9d154619cb0620e1889b3da3feec Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1673950 Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mt_scp/ipi: Host command should not wake up AP.Yilun Lin2019-06-251-1/+1
| | | | | | | | | | | | | | | | | Host command doesn't have needs to be a wake-up source (yet). We should not register it as a wake-up IPI. TEST=powerd_dbus_suspend, AP does not wake back up immediately. BUG=b:133380592 BRANCH=none Change-Id: Ie4b63a9e45bda4cdcdd0c369d9dd7e3163750bdd Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672657 Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/mt_scp/uart: Switch to use ULPOSC1_DIV10 for UARTNicolas Boichat2019-06-253-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | The 26Mhz clock is not available in S3, so use ULPOSC-sourced clock for the SCP in suspend. Also, change ULPOSC1 frequency to 240 Mhz, as this allows for a better division of the clock to get 115200 bps: - 240*1000*1000/10/(115200*16.0) => 13.02 <<< lowest error - 248*1000*1000/10/(115200*16.0) => 13.45 - 256*1000*1000/10/(115200*16.0) => 13.89 - 264*1000*1000/10/(115200*16.0) => 14.32 BRANCH=none BUG=b:134035444 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP powerd_dbus_suspend TEST=Can interract with console SCP in suspend. TEST=Measure UART frequency with an oscilloscope: 115.7 kHz Change-Id: I3bce4e94abaa97e20bef70f4f3ef3ca4e01d57b5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672646 Reviewed-by: Yilun Lin <yllin@chromium.org>
* ISH: fix UART output errorHyungwoo Yang2019-06-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently when there're a lot of prints to UART we don't see all of the prints. For example, -------- code -------- for (i = 0, v = 0x000FFFF; i < 1000; i++, v++) CPRINTF(">> UART TEST [%d] = 0x%08x\n", i, v); ---------------------- -------- output -------- >> UART TEST [0] = 0x0000ffff >> UART TEST [1] = 0x00010000 : : >> UART TEST [56] = 0x00010037 >> UART TEST [57] = 0x00010038 >> UART TEST>>>>>>>>>>>>>>[0.407104 HC 0x400b err 1] <<= print error ------------------------ It only happens with lots of prints and, based on the output, it looks like we are overwriting data before it's sent out. So This patch changes the bit used to see if transmitter is ready for new data from DTRQ to TEMT. BUG=none BRANCH=none TEST=Ran the code above and verified the output on Arcara platform. Change-Id: I21e9209510cade39f95e161f23ee373007b90e50 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672755 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* ish: Use 64-bit hardware timerJack Rosenthal2019-06-242-118/+27
| | | | | | | | | | | | | | | | ISH has native support for storing the hardware ticks in a 64-bit integer. With CONFIG_HWTIMER_64BIT, we can use this instead of relying on the periodic rollover interrupt. BUG=b:133190570,chromium:976804 BRANCH=none TEST=ran arcada_ish for more than 2³² μs, observed timer worked as normal Change-Id: I3b608c49081842f28d2ef8c16279992af1cb4fad Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1668056 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* g: make uart run fasterVadim Bendebury2019-06-241-14/+17
| | | | | | | | | | | | | | | | | | The EC queue library wrappers are very heavy, let's bypass them and use direct queue access where performance matters the most, in the UART RX driver used by USB streams. BUG=b:38448364 BRANCH=cr50, cr50-mp TEST=with the rest of the patches in place observed a much more reliable streaming of two consoles (ec and ap), both pumping chargen streams into their respective UARTs on an Octopus device. Change-Id: I45dc8f1c0841b43e17ef67e96820669053fba831 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672208 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* chip/mt_scp/hrtimer: Switch hrtimer to use ULPOSC1/8Nicolas Boichat2019-06-243-8/+18
| | | | | | | | | | | | | | | | | | | To be able to use the SCP in S3, we cannot rely on the 26Mhz clock, as it's off in S3. Switch to using ULPOSC1 divided by 8 instead. Also, make sure the frequency is a multiple of 8Mhz for the timer to be accurate. BRANCH=none BUG=b:134035444 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP powerd_dbus_suspend Change-Id: I048431cc062040caea70a5de3709ddd33550439c Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672645 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/hrtimer: Change 26Mhz to a defineNicolas Boichat2019-06-241-7/+10
| | | | | | | | | | | | | | | | Instead of hardcoding 25/26 all over the place, define the value at the top of the file. That'll make it easier to change the clock later. BRANCH=none BUG=b:134035444 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP Change-Id: I32df164c172a624560c1299049269899211815ce Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672644 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/clock: Prefer closest frequency when calibratingNicolas Boichat2019-06-241-4/+7
| | | | | | | | | | | | | | | | It's better to chose the closest possible frequency, rather than the one above the target, as the system clock is now sourced from ULPOSC1 and we want to minimize errors. BRANCH=none BUG=b:120176040 TEST=Load kukui_scp, see that ULPOSC is calibrated to 247558 kHz, instead of 250148 kHz (0.18% error, instead of 0.87%) Change-Id: I068fa09b5fedaf795ee6171f0b88ab658d5792a9 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672655 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/clock: Fix frequency meter divider (1024, not 1000)Nicolas Boichat2019-06-241-10/+10
| | | | | | | | | | | | | | | | | The frequency meter measures at 26 Mhz / 1024, not 26 Mhz / 1000, and use DIV_ROUND_CLOSEST to get a closer frequency meter target. Also, print the frequencies in kHz, not Mhz. BRANCH=none BUG=b:120176040 TEST=Add new timer sourced from (precise) 32.768 kHz to tick every second, see that the interval is close to a second. Change-Id: I32a9265187ed2936a928f2c09da8f544d814b5ae Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672650 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/clock: Move ULPOSC1/2 frequency settings to clock_chip.hNicolas Boichat2019-06-242-15/+16
| | | | | | | | | | | | | | | | Refactor the code to make it easier for hrtimer to use ULPOSC1 frequency. BRANCH=none BUG=b:134035444 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP powerd_dbus_suspend Change-Id: Ic1a7eab0f9075bf77c1b17ace9e3e95bee2924df Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672656 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/clock: Wait longer for clock measurement to completeNicolas Boichat2019-06-241-5/+11
| | | | | | | | | | | | | | | | Instead of a fixed-time wait, for in a loop (and a little longer) for the measurement to complete. This is useful when running ulposc in command line after the SCP has started, as the clock is then faster and the busy_udelay completes faster. BRANCH=none BUG=b:120176040 TEST=Deploy kukui_scp, ulposc works after boot. Change-Id: I2148ef6f6b7e7e673b035b9eee65cb6a83c9e9ae Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672647 Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp/ipi: Do not support ipi_send in ISR contextYilun Lin2019-06-232-7/+5
| | | | | | | | | | | | | | | | | No one uses ipi_send in ISR, and removing this can simplify the ipi_send logic. TEST=runs SCP, and see it doesn't print it sends IPI in ISR. BUG=b:117917141 BRANCH=none Change-Id: I96115ffc4124331d864daff2d375021c76a74b0c Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1670649 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org>
* kukui: scp: calibrate ULPOSC1&2Rong Chang2019-06-222-66/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ULPOSC generates clock for SCP core and peripherals. The calibration process adjust 2 values, div and cali. Both values are positive correlated to OSC frequency. The frequency function is: f(div, cali) = k1 * (div + k2) / R(cali) * C Where: R(cali) = k3 / (1 + k4 * (cali - k4)) The actual frequency is not linear to cali parameter. This change selects the div that generates closest frequency when cali == 32. And then adjust cali to get better output. [drinkcat: This relands e08a71fd0 "kukui: scp: calibrate ULPOSC1&2", with the following modifications: - Replace udelay by udelay_busy as the clock is not yet ready when calibrating - Simplify calibration logic. ] BRANCH=none BUG=b:120176040,b:120169529 TEST=manual check SCP console command: > ulposc ULPOSC1 frequency: 252 MHz ULPOSC2 frequency: 333 MHz Change-Id: I1a6b9d1ad140cd67b1fdecebf14b61cad88b2c4f Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1655221 Reviewed-by: Yilun Lin <yllin@chromium.org>
* ish: fixed wrongly entered D0ix states in some timesHu, Hebo2019-06-212-7/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In __idle() task, when calculate the 'next_delay' value (the sleep time), in most time, 'next_delay' should be always positive, but ISH HPET timer HW has some latency for interrupt, so it's possible in some times when its very close to the expire time of the event timer, the current time could advance the 'last_deadline' which should be updated in event timer ISR, in this case, 'next_delay' could be negative. We calibrated the 'last_deadline' in timer driver for this interrupt latency impact. So, the negative case for 'next_delay' should be not happen. If still happens, its doesn't matter, we can just ignore it , and if not want to see this case, can adjust the 'HPET_INT_LATENCY_TICKS' for new calibration till its not happen anymore. BUG=b:133459192 BRANCH=none TEST=tested on arcada platform, with 10ms timer loop task, D0i2/D0i3 should not entered. Change-Id: Ie84fb630900dd7d59a41c98c08da4a71a831c030 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1643247 Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* trng: make init_trng(), exit_trng() and rand_bytes() test_mockable.Yicheng Li2019-06-211-3/+3
| | | | | | | | | | | | | | | Make these functions test_mockable so that crypto-related functions that use them can be unit-tested. BRANCH=nocturne BUG=chromium:927095 TEST=make -j buildall Change-Id: Ie59c232077fa14420ca9686409159173815f0d26 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1652626 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
View Lorry Controller Status