| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Morphius connects the trackpoint device to EC via the PS/2 interface.
To support it, we implemented the chip level PS/2 driver in this CL.
The PS/2 driver can be used on all series of NPCX EC chips (NPCX5/7).
BUG=b:145575366
BRANCH=none
TEST=No error for "make buildall"
TEST=Apply this and related CLs, connect npcx5/npcx7 EVBs to standard
PS/2 keyboards and PS/2 device emulator with different channels. Verify
that the PS/2 write/read transaction can keep working for several hours
without issue.
Change-Id: I5bae313db2d697999c2da5cf33478be2da754b8c
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982302
Tested-by: CH Lin <chlin56@nuvoton.com>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Edward Hill <ecgh@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In Morphius, the trackpoint data is passed through EC to the host by the
legacy ports (60h/64h). In this CL, we enable the host interface mouse
channel (LDN = 05h). Mouse interrupt (IRQ 12) will be asserted when the
trackpoint data is written to the HIMDO register. It will be de-asserted
once the host reads the data via IO port 60h.
BUG=b:145575366
BRANCH=none
TEST=No error for "make buildall"
TEST=Apply this and related CL, connect npcx EVB to host emulator.
Execute console command "kbcmouse data". Make sure the host can see IRQ12
and read correct data from IO port 60h.
Change-Id: I4a4e9fb6c079c164b6a5e617587dd2f2cdf55164
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2003002
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When the HW SPI module is disabled (i.e. SPE bit is cleared), then the
stm stops actively driving the SPI CLK signal and lets it float. This
can cause spurious communication issues or guaranteed issues if there is a
pullup on the CLK signal.
Ensure that the CLK signal is being driven (low) for the duration of a
USB SPI transaction at minimum.
Driving the CLK signal low for the duration of the SPI transaction also
seems to help with sporadic reliability issues on servo_micro
Also add a flag that enables the SPI module to be enabled for the
entire time the firmware wants to enable the SPI module opposed to
needing both the firmware and the USB host to enabled the SPI module.
BRANCH=servo
BUG=b:145314772,b:144846350
TEST=with scope verify that SPI CLK line is help low as soon at the
`enable_spi 1800` command is enter on C2D2 console and continues to stay
low in between all USB SPI traffic from host.
Change-Id: I9dbd6b3ebca8db6470d9ec70bae02ac8366d6c9e
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1995604
Reviewed-by: Brian Nemec <bnemec@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add flags field to stm and g chip usb spi configuration. This is unused
for g chip, but added for consistency.
BRANCH=none
BUG=b:147353903
TEST=builds
Change-Id: Ie2aa88ae09e8f6f4049ba13fe4565901c604b92c
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1995603
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Brian Nemec <bnemec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
If the stm has its SPI bus disabled locally, then the
host request to enable or disable SPI would go unacknowledged
which would ultimately crash the stm32.
BRANCH=none
BUG=b:147353903
TEST=execute flash rom when C2D2 is not in SPI mode and watch
that C2D2 no longer crashes.
Change-Id: I05d6c1519b90932a9c883c013059446c2751c892
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1995602
Reviewed-by: Diana Z <dzigterman@chromium.org>
Reviewed-by: Brian Nemec <bnemec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add configuration for changing adc control pin order
on chip it83202Bx.
BUG=none
BRANCH=none
TEST=ADC16 of PD port2 can read correct Vbus value.
Change-Id: I9a7f81bf3cb1ac74a5f07ce817d03f5ab0569d17
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009539
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add chip support pd physical port count configuration.
BUG=none
BRANCH=none
TEST=build all -j
Change-Id: Ic473e53af44b5360aad6d2db74cf09ce5a3fa3e8
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009537
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Because contents of section 0 ~ 0x1000 of flash are only
mapped to ILM on it8xxx2 series (risc-v core).
So we changed to verify flash from ILM to fix erase/write
the section error.
BUG=none
BRANCH=none
TEST=erase/write section 0 ~ 0x1000 are successful on IT83202.
Change-Id: I34165ce9cb04babc8c55ddcc64549df1e65c4ff9
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982296
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Dedede has support for the new low power "Z-state". In this state. the
EC and H1 are unpowered, but power will be restored to the EC once one
of the wakeup events occurs. These events are ACOK, lid open, and a
power button press. This commit simply enables the Z-state when the EC
hibernates.
BUG=b:147819424
BRANCH=None
TEST=build and flash waddledoo, enter `hibernate`, verify that EC power
is turned off and can be restored by pressing the power button or
plugging in a charger.
Change-Id: I4f93efd0632f457354f4bf6bf0274b19a9cd799c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006215
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=Attach SWD to dragonclaw v0.2
Change-Id: I7bd5741c4862bb2f134ae3067715d2301a18ea78
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1962974
Reviewed-by: Jett Rink <jettrink@chromium.org>
Tested-by: Tom Hughes <tomhughes@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enables the programmable voltage detector (PVD) interrupt in
ServoMicro. This interrupt fires when the supply voltage drops
from the expected 3.3V to under 2.3V after power on. This gives
several hundred microseconds of time for the device to respond
to the power reduction.
In order to ensure that the ServoMicro does not enter a
non-responsive state, it triggers a reboot of the system to
restore it to a good configuration.
BRANCH=servo
BUG=chromium:1023715
TEST=Configured GPIO output to trigger on pvd_interrupt()
and verified the interrupt fires during the following
situations using Saleae analyzer:
* USB Power removed from working device
* Ramping supply voltage from 1.5V to 5V with a DC supply
* Repoducing failure condition from crbug/1016051
1 Connect ServoMicro to Cyan board
2 dut-control power_state:on
3 dut-control fw_wp_vref:pp3300
4 dut-control power_state:off
5 GPIO toggles and system reset occurs
Change-Id: I721f48ab84b01d52a5f98747cc9d879ff2876a07
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1911759
Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
Tested-by: Brian Nemec <bnemec@chromium.org>
Commit-Queue: Brian Nemec <bnemec@chromium.org>
Auto-Submit: Brian Nemec <bnemec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add a i2c_set_freq function and let chip drivers add their underlying
implementation.
Also implemented on stm32f0.
BUG=b:143677811,b:78189419
TEST=1) make
2) On kodama, call i2c_set_freq(1, 100) during init.
verify the bus is configured to 100kbps in kodama rev 1
BRANCH=kukui
Change-Id: Iebb5baacf098b3e5649a4bd8ca14acf097d39693
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1969245
Reviewed-by: Matthew Blecker <matthewb@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
かな (kana) key in the right side of the space bar (Row 12/
Column 1) must emit USB keycode 0x8a, which will get translated
to KEY_HENKAN(92) by the Linux kernel.
英数 (eisu) key on the left side (Row 12/Column 3) must emit USB
0x8b, translated to KEY_MUHENKAN(94).
BRANCH=kukui
BUG=b:144141826
TEST=Flash masterball, hand the device to Japanese PM for testing.
Change-Id: Ie16453a605a7153f248badbc4c8ebfc3872ce3ac
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002428
Tested-by: Joseph Kurachi Luk <kura@google.com>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This commit simply refactors the bkpdata functionality,
common to all stm32s, into its own source and header files.
Same code, different place.
This allows for the use of stm32 backup register functionality
outside of stm32/system.c.
The targeted usage is in https://crrev.com/c/1992740 , a bug fix that
is limited to a board's scope.
BRANCH=nocturne,hatch
BUG=b:146428434
TEST=make buildall -j
TEST=Ensured that reset flag preservation works across resets.
Change-Id: Id2ba570949e0e7bb3a1faf64e625e122aa3b4ed5
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1992488
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When the OFMCLK is reloaded, it will be stopped until the clock
generation becomes stable. During this narrow window, any eSPI response
from EC will be abnormal. However, we needn't change the OFMCLK during
system-jump because it should be set only once when EC powers on.
BUG=b:145369656
BRANCH=none
TEST=Pass "make buildall"
TEST=The symptom no longer occurs for 3 hours stress test.
Change-Id: Idcc745f11119ba3781787b8b5e77ea620264e908
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994685
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This patch allows chargen to print output to USB instead of UART,
which is chosen by command parameter.
If USB console is not supported, then the parameter will be ignored,
and output shall go to UART port.
The patch increases flash usage by 48 bytes if CONFIG_CMD_CHARGEN
is defined.
BUG=chromium:992607
BRANCH=None
TEST=manually ran on fleex.
for BOARD in {cr50, fleex}
1. Define CONFIG_CMD_CHARGEN in board/cr50/board.h,
and baseboard/octopus/baseboard.h.
2. Build binaries, and program them.
3. Connect CCD to Octopus Fleex.
4. Open terminal to Cr50 and EC consoles, and run chargen
(cr50) chargen 1 4
> // no output, because they went to UART.
(cr50) chargen 1 4 usb
0000
>
(ec) chargen 1 4
0000
>
(ec) chargen 1 4 usb // usb parameter gets ignored.
0000
>
Change-Id: I5810421fef56548e0bd667488e853e724f699a31
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1769386
Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add new register definitions needed for c2d2
BRANCH=none
BUG=b:145314772
TEST=none
Change-Id: I159f832a40037271aa352fe83c5289a3a674699b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1991848
Reviewed-by: Craig Hesling <hesling@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
1. Uses DEBUG_AUDIO_CODEC instead of DEBUG_WOV.
2. Moves console commands under DEBUG_AUDIO_CODEC (saves ~3KB).
BRANCH=none
BUG=b:144064048, b:144063867
TEST=make BOARD=trembyle -j
Change-Id: Ic5b3442809506d71a333b5c1c9cc0dd4776d98bb
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986688
Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org>
Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
CONFIG_WAKE_ON_VOICE consists 3 features in NPCX:
- DMIC
- I2S_RX
- WOV
These features has broken down into smaller CONFIG options. Deprecates
CONFIG_WAKE_ON_VOICE and prepares to separate smaller features in NPCX.
BRANCH=none
BUG=b:144064048, b:144063867
TEST=make BOARD=trembyle -j
Change-Id: Ieaa123299ea687644f19066cf95ef150a18bf252
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986687
Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org>
Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Migrates DMIC and I2S_RX to new audio codec framework.
BRANCH=none
BUG=b:144064048, b:144063867
TEST=make BOARD=trembyle -j
Change-Id: Ifbc6d939110311578c4aa0655ede92b1df714774
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986686
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org>
Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Some changes to bytes/string handling to convert to Python 3. Most of
these changes came from the mec1322 script (since it seems large
sections were copy/pasted).
BUG=chromium:1031705
BRANCH=none
TEST=make BOARD=reef_mchp, ensure binary equivalent
Change-Id: Idffa2dbef7359aa176c1aafa1c504e9e29ee9d49
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1997736
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=make BOARD=nucleo-h743zi
# Reboot H743 into bootloader using boot0 pin and reset
# Flash nucleo over FTDI and STM32 bootloader
stm32mon -u -U -w build/nucleo-h743zi/ec.bin -d /dev/ttyUSB0 -b 115200
# Reset without boot0
# Open console
minicom -D/dev/ttyACM0
reboot soft
# Verify soft reset was used
reboot hard
# Verify hard reboot was used
Change-Id: If211198b853ad97cb96b39c063d3e04bfce68179
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1988232
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Just some string/bytes encoding handling needed to upgrade to
Python 3.
BUG=chromium:1031705
BRANCH=none
TEST=make BOARD=strago, verified binary is unchanged
Change-Id: I2e95da9442e680e89761b9d34ce7aee9a72c0991
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1975098
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
pd_get_role in the TCPMv1 stack meant pd_get_power_role.
pd_get_role in the TCPMv2 stack meant pd_get_data_role.
This CL will clean that up and make them the correct naming.
pd_get_power_role will also return an enum pd_power_role
type instead of an int.
BUG=b:147290482
BRANCH=none
TEST=make buildall -j
Change-Id: I73ee465401ccd050c2bd151f2fc043a59d95e079
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1991844
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL does:
1. Move power_chipset_handle_host_sleep_event from board to chip folder
2. Uses ULPOSC1(240/2MHz) when AP suspend. When AP in suspend, Vcore
decreases from 0.8V to 0.6V and thus it shouldn't use ULPOSC2 (330Mhz)
which needs at least 0.7V to clock. ULPOSC1 only needs 0.6V to clock.
TEST=run suspend/resume test for 2500 runs and ensure the
SCP won't trigger watchdog.
BUG=b:144820026
BRANCH=kukui
Change-Id: I7b317a70b6ed93ff83e9543b2fc6cdfede112fd3
Signed-off-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1985728
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Erin Lo <erin.lo@mediatek.corp-partner.google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
NPCX was missing support for an inverted write protect polarity, this
commit simply adds that support.
BUG=b:146172102
BRANCH=None
TEST=`make -j buildall`
Change-Id: I3324d7f7cfa268a2d55f87d3b1943717e26c856c
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986311
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Auto-Submit: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We got an issue on IT83202BX that flash won't be able to wake up
correctly in EC low power mode when WRST# is asserted.
This issue might cause cold reset failure so we made this change
to fix it.
BUG=none
BRANCH=none
TEST=hibernate EC and then press servo board's COLD_RST_L to reset EC.
EC reboots.
Change-Id: Ide3a240e1fe62d712536c69d8f390241e67144f6
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1973974
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Misc changes to get working in Python 3, mostly to do with handling
bytes/strings differently.
BUG=chromium:1031705
BRANCH=none
TEST=make BOARD=arcada_ish
Change-Id: I3fe4adbf8d8dcb07401515ddf8a02aec9c3d0b05
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1975094
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is more for register documentation accuracy.
BRANCH=hatch
BUG=none
TEST=make buildall -j
Change-Id: I879ae1feb85115ebfa845fc98ff9bb1b9ef2b936
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1962973
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The STM32F412 and STM32F446 reference manuals seem
to indicate that the SBF clear bit is actually bit 3.
BRANCH=hatch
BUG=none
TEST=make buildall -j
Change-Id: Ib98c5831f19355dfe3643c7d0b8258bd449d373b
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958847
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This brings no function change.
BRANCH=hatch
BUG=none
TEST=make buildall -j
Change-Id: I9a9363d4771039244ed79408674a598f768075e9
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958846
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This brings no change in functionality.
BRANCH=nocturne,hatch
BUG=none
TEST=make buildall -j
Change-Id: I03ed72ba07affb9b6a8757c1a2154ca31283bb97
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958845
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add the spi slave function which is required to
communicate with the EC when the CPU is the ARM
processor.
BUG=none
BRANCH=none
TEST=Replaced board elm's EC with it83202 and
boot kernel and keyboard work.
Change-Id: I7ce3bb56450276997b58e84b1c6de3f8e45bb4b7
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918991
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Kodama needs to reconfigure i2c bus frequency at runtime.
Expose i2c_init_port so we can re-init i2c bus at board_rev_init().
BUG=b:143677811
TEST=verify sensor/battery works on kodama EVT and DVT
BRANCH=kukui
Change-Id: I4050179d24f05db1ef20270ebbb567eba429546c
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1959669
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
CONFIG_DCRYPTO compiles and links thirdparty/libcryptoc for cr50.
CONFIG_LIBCRYPTOC does similar things for other boards that configures
it, including host. This resulted in cr50_fuzz having concurrent
recipes for libcryptoc, as it has both configs. This change separates
CONFIG_DCRYPTO from the responsibility of building and linking libcryptoc.
Libcryptoc is now solely handles by CONFIG_LIBCRYPTOC.
BRANCH=none
BUG=b:144811298
TEST=make -j buildall > /dev/null
Observed no more "warning: overriding recipe for target
'build/host/cr50_fuzz/cryptoc/libcryptoc.a' "
Change-Id: I2186cbead773629456da254df5f82b96e9646fc2
Signed-off-by: Yicheng Li <yichengli@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949554
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Both RO and RW sections have their respective rollback spaces in
INFO1, but until now Cr50 code did not honor the RO binaries' headers
rollback maps and did not update the appropriate iNFO1 space.
With this patch both RO and RW info maps are updated to the lowest
level of the two images found in the flash when invoked during
board_init() or to match the currently active RO/RW when invoked
through vendor command indicating successful OS startup.
BRANCH=cr50, cr50-mp
BUG=b:136284186
TEST=tried the new image on a chip with freshly erased INFO1 space:
first running a DBG image, which does not touch INFO1 maps:
> vers
...
RO_A: * 0.0.11/bc74f7dc
RO_B: 0.0.11/4d655eab
RW_A: * 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
RW_B: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
..
> sysinfo
...
Rollback: 0/1/1 0/128/128
...
Then running an image with debug extensions disabled:
> vers
...
RO_A: * 0.0.11/bc74f7dc
RO_B: 0.0.11/4d655eab
RW_A: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
RW_B: * 0.4.24/cr50_v2.0.2744-d79516a9d
...
> sysinfo
...
Rollback: 1/1/1 2/128/2
...
Change-Id: I259a3f46c03199633ca85389872449d667f172fb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949548
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Cr50 firmware is required to update the rollback prevention map in
INFO1 for both RO and RW images.
This patch adds code to display the state of the RO map and both RO_A
and RO_B headers in addition to previously reported RW information.
BRANCH=cr50, cr50-mp
BUG=b:136284186
TEST=loaded the new image and observed reported rollback state:
> sysinfo
...
Rollback: 0/1/1 0/128/128
...
Change-Id: I32206545b6a59a5693e4274e62fcf0627780f61f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949546
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
DCRYPTO_gcm_init hardcoded key length to 128 bit causing preventing
testing of 192 and 256 bit functionality for AES-GCM.
BUG=b:135623371
BRANCH=cr50
TEST=compile, specific test for issue as described in bug
Change-Id: I4fc41f6155661709115c57aa944c8976e17bffac
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1766098
Reviewed-by: Andrey Pronin <apronin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
watchdog_stop_and_unlock() depends upon the ITIM32 module to ensure
that it has been at least 3 watchdog ticks since the last time the
watchdog has been touched. If it has been > 100ms since then, there
will be no problem, but if it has been less than 100ms, then because
the ITIM32 module was disabled, then the system will get stuck in the
while (time_since32() ...) loop. This will eventually cause the
watchdog to kick in and reboot the EC, which will also cause the
AP to reboot.
BUG=b:145371494, b:140207603
BRANCH=firmware-hatch-12672.B
TEST=sanity testing (alt+volup+h still works) and
buildall (this bug was nearly impossible to reproduce)
Change-Id: I5e32f4940f03fee90b3aa809b185c13ed66ce7f1
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1946773
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In npcx7, all I2C modules have separate 32-byte transmit FIFO and
32-byte receive FIFO buffers. In this CL, we add the FIFO mode support
to the I2C driver. This will help to reduce the firmware overhead (i.e.
the occurrence of I2C interrupt) during long I2C transactions by allowing
the EC to write/read more than one byte of data at one time to I2C
module and hence improve the I2C performance.
The FIFO mode is enabled by default on all npcx7 series chips.
BUG=none
BRANCH=none
TEST=No error for "make buildall"
TEST=Connect npcx7 EVB to the I2C slave emulator, do stress test:
1. iterate ~2000 times of single i2c_xfer_unlocked API call.
i.e.
i2c_xfer_unlocked(.., I2C_XFER_SINGLE)
2. iterate ~2000 times of multiple i2c_xfer_unlocked API calls:
i.e.
i2c_xfer_unlocked(.., I2C_XFER_START)
i2c_xfer_unlocked(.., 0)
.
.
i2c_xfer_unlocked(.., I2C_XFER_STOP)
3. Issue 6 I2C transactions by 6 tasks at the same time.
iterates ~2000 times.
TEST=with this CL; build and upload an image (with/without FIFO mode
enabled.) to yorp; no symptom occurs.
Change-Id: I387e8ef6e619acef670273f08ab4150e3d2b75f2
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827137
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The CONFIG_HOSTCMD_X86 will get automatically defined
if either CONFIG_HOSTCMD_LPC or CONFIG_HOSTCMD_ESPI
are defined. So this definition is redundant in
config_chip.h
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I3cb9b61d4b006becba5eb75e0dabe61bd9e3c999
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868134
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The module ID in alternate function setting for spi
master should be corrected as MODULE_SPI_MASTER.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Ib52b09a5f1e0c496374d4ed2f3a222dab9af2eb0
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868133
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
GPIO, WUC and IRQ changes for chip it83201/it83202.
BRANCH=None
BUG=b:133460224
TEST=test GPIO group O, P, Q, R
1.Input: external input 3.3v, GPDR of corresponding pin is 1.
(GCR31, GCR32 select 1.8v, validate again for O and
P group)
2.Output: GPDR of corresponding pin set 1, measure 3.3v.
3.INT: GPIO_INT input trigger => WU INT (select high, low,
rising, falling, both edge trigger mode) => INT => CPU INT
4.Test power-up and down with this CL on ampton.
Change-Id: Ifae081c87b3dafcf3f7da84f637ceaf64a5ed536
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1675704
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We have seen cases where after a cold EC reboot the pin is low until the
first CEC message is sent by AP (after which the bus is left in a well
defined state again)
This is a follow up to https://crrev.com/c/1346990 which initializes
the pull up in case not done by the RO FW.
BRANCH=none
BUG=b:144548408
TEST=CEC pin only goes low for ~40ms instead of 30s.
Signed-off-by: Felix Ekblom <felixe@chromium.org>
Change-Id: I3c98f8858f407279ad1bd086210969d69df2230b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928993
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When we go through the suspend code path, we disabled RX
monitoring, and we have done that for a 4+ years. We have
not had a unit test for that ever. One is come that needs this
BRANCH=none
BUG=b:144369187
TEST=See that disabling RX in set_state no longer causes
assertion failures in tests that it shouldn't.
Change-Id: Iab4b44d3f5fdd1fe8657b23ac59df247a384ee32
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925667
Tested-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The new RO has a new dev key, modify the dev manifest to match the new
RO expectations.
BUG=b:74100307
BRANCH=cr50, cr50-mp
TEST=built a node locked image for ro 0.0.11 and observed it boot and
run
Change-Id: I3ce9ca8d23be6b2d959d4457ea6d08afa05376ac
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1866173
Reviewed-by: Andrey Pronin <apronin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Counter implementation has been moved to the AP, no need to keep space
for it in the flash.
BUG=b:65253310
BRANCH=cr50, cr50-mp
TEST=generated image uses 2048 bytes less than before this patch.
Change-Id: I8225e9923932ce06ca0a4333c06508cf7d7c70d8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1753677
Reviewed-by: Andrey Pronin <apronin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
HMAC DRBG is used for U2F key generation, and as such is subject
for ACVP tests. Expose DRBG Init, Generate and Seed commands for
automated testing with externally provided test vectors.
BUG=b:138578319
BRANCH=cr50
TEST=make CRYPTO_TEST=1 BOARD=cr50 -j && test/tpm_test/tpmtest.py
Change-Id: I50a6750864d3cd9a304a9b8a8524ef29cec04410
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1912662
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
NIST 800-90B Entropy assesment tests requires 1M of 8-bit samples for
statistical tests. While it's possible to use TPM2_GetRandom command
to get entropy on cr50 (there is no software postprocessing), this
command is not available when compiled with CRYPTO_TEST=1 due to lack
of space in firmware. Adding vendor command which is available with
CRYPTO_TEST=1 to get raw entropy from TRNG. Added support script
to save entropy in file for further analysis. Since downloading
entropy takes a long time, new option'-t' added to tpmtest.py
which only invokes download of TRNG samples
BUG=b:138577834
BRANCH=cr50
TEST=make BOARD=cr50 CRYPTO_TEST=1 && test/tpm_test/tpmtest.py -t
To run NIST tests: nist_entropy.sh
Change-Id: I237a4581332a6e2c0332fe6ecf40731ab0be3355
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919640
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
With the addition of external i2c keyboard controllers, chips that don't
necessarly have gpios going to a keyboard can now still have a TASK_KEYSCAN.
Therefore it's wrong to assume we want the chip/*/keyboard_raw code included.
There was no easy way to make an ways on option (eg: CONFIG_KEYBOARD_RAW)
that could get #undefd in strategic places. The place that would always
define it would be in include/config.h but I don't believe that executes
before the build.mk rules.
BUG=b:135895590
TEST=Other boards with keyboards still happy.
TEST=No compile errors (regarding missing keyboard GPIOS) when declaring
TASK_KEYSCAN on a fresh stm32 board.
BRANCH=master
Change-Id: I061812a6941a11784950280648912edd5844bd79
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693862
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|