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* chip/stm32: Save STAY_IN_RO flag if set during resetTom Hughes2020-05-141-0/+4
| | | | | | | | | | | | | | | This matches the behavior of system_encode_save_flags() and allows us to reboot into RO for testing. BRANCH=none BUG=b:156401765 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: Ibbb95ca81fb87eaa48639dea99be1bd0e35ea230 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2197621 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* cleanup: rename kpbs to kbps for i2cJett Rink2020-05-091-2/+2
| | | | | | | | | | | | | | | This changes follows the hdctool change for c2d2 that ensures either kpbs or kbps on the console output will work (CL:2161642) BRANCH=servo BUG=none TEST=builds Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I57e1638a4e8c9a61d58705c70d4d24c7b65e48bd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2191132 Commit-Queue: Diana Z <dzigterman@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* stm32: Add chip_read_reset_flags and chip_save_reset_flagsDaisuke Nojiri2020-05-061-3/+13
| | | | | | | | | | | | | | | | | | | | | Battery backed up RAM is used to store the reset flags. This patch wraps the code reading and writing the reset flags with APIs for the consistency and make it available to external callers. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1078470 BRANCH=none TEST=buildall Change-Id: Ica31008b8f0f89f6804002c2c796e3b3c117e06a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182563 Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* mchp: Add chip_read_reset_flagsDaisuke Nojiri2020-05-061-2/+7
| | | | | | | | | | | | | | | | | | | | Battery backed up RAM is used to store the reset flags. This patch wraps the code reading the reset flags with an API for the consistency and make it available to external callers. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1078470 BRANCH=none TEST=buildall Change-Id: I11dd5a75eb51fa02664e0c30fa7e23a9ea2dc3bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182562 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* lm4: Add chip_read_reset_flags and chip_save_reset_flagsDaisuke Nojiri2020-05-061-3/+13
| | | | | | | | | | | | | | | | | | | | | Battery backed up RAM is used to store the reset flags. This patch wraps the code reading and writing the reset flags with APIs for the consistency and make it available to external callers like other chips. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1078470 BRANCH=none TEST=buildall Change-Id: I39c8646e57755d661b239979946df2871275878b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182561 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx: Add chip_read_reset_flags and chip_save_reset_flagsDaisuke Nojiri2020-05-061-13/+22
| | | | | | | | | | | | | | | | | | | | | Battery backed up RAM is used to store the reset flags. This patch wraps the code reading and writing the reset flags with APIs for the consistency and make it available to external callers like other chips. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1078470 BRANCH=none TEST=buildall Change-Id: Ibba8078ea9fa3d7e018280254b8ca40c34e4eafe Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182560 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* test: Add on-device unit test for STM32 RTCTom Hughes2020-04-301-0/+1
| | | | | | | | | | | | BRANCH=none BUG=b:151105339 TEST=make BOARD=bloonchipper test-stm32f_rtc -j Flash stm32f_rtc.bin and "runtest" in the console Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I3debfd93b62cb269ad61af0e4ca7e195554b5548 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171569 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/adc: enabled GPIO alternate mode by default for pin into gpio.inc ↵tim2020-04-293-53/+15
| | | | | | | | | | | | | | | | | | | | marked as MODULE_ADC In the ADC initialization function, we should use the function of gpio_config_module to set alternate function and declare corresponding alternate function pins in gpio.inc. So we are able to enable extra flag if needed. BUG=none BRANCH=none TEST=testing the alternate function pins are normal on the board of it83xx_evb, it8xxx2_evb, it8xxx2_pdevb and reef_it8320. Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I734b6ecc8f9343be65d9f29837e793b9574f8bdc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2160241 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it8xxx2: lpc/espi: mapping host I/O cycle to h2ram sectionDino Li2020-04-283-0/+16
| | | | | | | | | | | | | | | | | | On it8xxx2 series, host I/O cycles are mapped to the first block (0x80080000~0x80080fff) at default, and it is adjustable. We should set the correct offset depends on the base address of H2RAM section, so EC will be able to receive/handle commands from host. BUG=b:133460224 BRANCH=none TEST=not yet. just check the register setting is correct (I/O cycles are mapped to 0x80081000~0x80081fff) after EC initialization. Change-Id: Ib9085181917712bf735b83487720f12c8cd7ca31 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2038223 Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: add chip family codeCHLin2020-04-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | If a hardware feature is supported across two or more chip families but not supported in the older chip family, using the chip family code can simplify the guard of the new feature. For example, we can use: #if (NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7) Implementation of the new feature #endif instead of: #if defined(CHIP_FAMILY_NPCX7) | defined(CHIP_FAMILY_NPCX8) .... Implementation of the new feature #endif BUG=none BRANCH=none TEST=No error for "make buildall" Signed-off-by: CHLin <CHLIN56@nuvoton.com> Change-Id: I09614428034f64f16ed446b73bf0797ee81538c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142834 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
* it81202/it81302: set GPIOH7 as output low at defaultDino Li2020-04-202-0/+14
| | | | | | | | | | | | | | | | | | | On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left floating internally. We need to enable internal pull-down for the pin to prevent leakage current, but IT81202/IT81302 doesn't have the capability to pull it down. We can only set it as output low, so we enable output low for it at initialization to prevent leakage. BUG=none BRANCH=none TEST=On it81202 EVB, power consumption is reduced by ~70uA. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Iba1f5af684e31cad192b4e9ee5b099e7c51a71a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2147761 Reviewed-by: Jett Rink <jettrink@chromium.org>
* c2d2/servo_micro: invert SDA during ITE programming seqJett Rink2020-04-162-2/+8
| | | | | | | | | | | | | | | | | | | According to programming guide, the SDA signal (200kHz) should have its rising edge in the middle of the SCL (100kHz) transition. Since the timers are starting at the same time, inverting the SDA timer will achieve this. This will affect both servo_micro and c2d2 BRANCH=servo BUG=b:153393490 TEST=verify with scope on C2D2 is SDA/SCL signals match programming guide Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: Ibda89a30f77d39c633f491840b82f7b1dee552c5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142561 Reviewed-by: Matthew Blecker <matthewb@chromium.org>
* it83xx/pwm: clear cycle timer1 high byte for using as 8-bitRuibin Chang2020-04-162-0/+9
| | | | | | | | | | | | | | | | | | | | | | The cycle timer1 of chip 8320 later series was enhanced from 8bits to 10bits resolution, and others are still 8bit resolution. Because the cycle timer1 high byte default value is not zero, we clear cycle timer1 high byte at init and use it as 8-bit resolution like others. BUG=none BRANCH=none TEST=on board it8xxx2_evb 1) console check: the register CTR1M value 2) oscilloscope check: the pwm output frequency same as our setting on board level via prescaler c4. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I5b2f249bbf56d3fbded88401779715973434e5d9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142850 Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* it81202/gpio: set group L and K as pull-down at defaultDino Li2020-04-092-0/+18
| | | | | | | | | | | | | | | | On IT81202 (128-pins package), the pins of GPIO group K and L aren't bonding with pad. So we configure these pins as internal pull-down at default to prevent leakage current due to floating. BUG=none BRANCH=none TEST=Checking control registers of group K and L are all internal pull-down. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I67abff25ba4617898203693b21eb8eb1059be910 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2141375 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ITE: Return an error if i2c unwedge attempt failedDiana Z2020-04-081-1/+7
| | | | | | | | | | | | | | | Checks the return of the i2c unwedge attempt and returns the error if the bus was unable to be unwedged. BRANCH=None BUG=b:153195490 TEST=on waddledee, "apshutdown" can be run from the EC with no i2c wedge issues Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Id0785f099bdf20d622226501f415ac411eea6f81 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2136873 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* it83xx/gpio: disable unused cc port moduleRuibin Chang2020-04-072-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | To prevent cc pins leakage and cc pins can be used as gpio. We will check if the chip supported tcpc physical port count is more than board active ITE port count. If yes, we will disable unused cc port module. BUG=none BRANCH=none TEST=1) on board it8xxx2_pdevb with chip it81202, check the pd port connection with adapter and dongle when hibernate and resume. adapter: connect dongle: disconnect then re-connect 2) on board it83xx_evb with chip it8320, set cc pins as gpio, check output level when hibernate and resume. Change-Id: I13511741b2e066dd87277db9f71f2b4a9323ad6d Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994693 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ec: Enlarged Task Stack size on platformsBrian J. Nemec2020-04-023-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The task stack size of is small enough that the process was triggering stack overflows when responding to commands. These actions had a small chance of causing EC hardfaults. This was apparent with the gpioget command which had the attributes of performing many calls to a printf function which also has many parameters. Since the structure of a printf with 10 or more parameters is common when constructing console responses, this enlarges the stack for that task. This is more important since the probability of it creating a hardfault is low. To reduce the chance of this issue on other platforms, the platforms with 488 byte tasks were also enlarged to 512 bytes. BUG=chromium:1056780 BRANCH=none TEST=Connected servod to servo_v4 looped the command 'dut-control servo_v4_uart_cmd:gpioget' 1000 times TEST=make buildall -j Verified free ram space remains over 60 bytes on impacted platforms Change-Id: I6b50b204c83a10068153f3e01bc134446047f235 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2133130 Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* it83xx/spi: enable auto reset rx fifo functiontim2020-04-023-83/+69
| | | | | | | | | | | | | | | | | | | | | | | | In this change, we enable IT83XX_SPI_AUTO_RESET_RX_FIFO. When CS# deasserted, the rx fifo and fifo count can auto reset in time by the hardware way to avoid the time delay caused. And we removed the spi_chipset_startup and shutdown. we don't need to disable the interrupt of GPIO_SPI0_CS via hook during chipset suspend and enable it during chipset resume. Instead, when the interrupt of GPIO_SPI0_CS occurs, we judge whether the chipset state is enabled and then to disable deep sleep. BUG=none BRANCH=none TEST=boot to kernel with it81202 on elm board. Press the button to shutdown and resume testing 10 times are normal. Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I263d63fa5c22ef430d8f807c694317b7496f238f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2100372 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Dino Li <Dino.Li@ite.com.tw>
* tcpm/it83xx_pd: cc1 and cc2 resistance setting separateRuibin Chang2020-03-301-0/+2
| | | | | | | | | | | | | | | | | | In it81202/it81302 setting cc1 and cc2 resistance is individual for each cc. BUG=none BRANCH=none TEST=on it8xxx2_pdevb board, check cc toggle and connection with adater and dongle by Oscilloscope. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I3d0697b39b2302830c67061fc3279d33d40b9957 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2120112 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* cleanup: drop the _TYPEC part of USB device configJett Rink2020-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The three USB device configurations describe more than just the Type-C layer, so remove the _TYPEC part within the define. This is also in preparation to change how the usbc build.mk includes files. This was performed with the following commands: $ git grep --name-only CONFIG_USB_TYPEC_DRP_ACC_TRYSRC | xargs perl -i -ple 's/CONFIG_USB_TYPEC_DRP_ACC_TRYSRC/CONFIG_USB_DRP_ACC_TRYSRC/g' $ git grep --name-only CONFIG_USB_TYPEC_CTVPD | xargs perl -i -ple 's/CONFIG_USB_TYPEC_CTVPD/CONFIG_USB_CTVPD/g' $ git grep --name-only CONFIG_USB_TYPEC_VPD | xargs perl -i -ple 's/CONFIG_USB_TYPEC_VPD/CONFIG_USB_VPD/g' BRANCH=none BUG=none TEST=builds Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I4deab784b7c3479cffd3dee7fb3ea3c8a9d6081c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2121193 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* stm32f412: Fix chip config Flash and RAM sizesCraig Hesling2020-03-242-4/+13
| | | | | | | | | | | | | | | | | | We are already using the stm32f446 config for many F4 based chips. Let's actually make this more clear and un-hack our hatch_fp board.h. This present no functional change. BRANCH=none BUG=none TEST=./util/compare_builds.sh -b "hatch_fp sweetberry" Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I6b46e696686ad740833dc889c1db5d7bac84a768 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2109244 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* it83xx/flash: exclude immu tag workaround if chip's core is riscvDino Li2020-03-241-1/+1
| | | | | | | | | | | | | | | | | This issue is present on chip with N8 core only. So we don't need to apply the workaround for chip with RISCV core to save time of writing and erasing. BUG=none BRANCH=none TEST=use console "flasherase" and "flashwrite" commands to erase/write these two 4KB blocks(0x7e000 ~ 0x7ffff) on both IT8320 and IT81202, no error message occurred. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I9aeb7e32048dafb2fa54bf1a137ecafb5a854b91 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2109438 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it8xxx2: wake up CPU if an interrupt is pending in idle taskDino Li2020-03-244-5/+17
| | | | | | | | | | | BUG=b:142029177 BRANCH=none TEST=In idle task, EC does not get stuck. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I9f3c0e3b58e68d60b1218338603a5f2a4bc5eb5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2100055 Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/it8xxx2: add support IT81302 and IT81202Dino Li2020-03-213-6/+59
| | | | | | | | | | | | | | | | | | | | | | | IT81302 (144-pins package) and IT81202 (128-pins package) chips belong to it8xxx2 family. So we apply the same chip options of it83202bx (except ADC pin order config option) and setup the correct flash size, ram size, and ram base. With this change, we are able to build FW image with IT81202 or IT81302 chip variant. BUG=none BRANCH=none TEST=EC boots and test console commands (version, sysinfo, sysjump, flasherase, flashwrite, and flashread) on IT81202 EVB. Hibernate EC and then press servo board's COLD_RST_L to reset EC. EC reboots. Change-Id: If351d561c61f635ebdb1e4e444e73e061a494c9a Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2072562 Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32: Refactor clock-stm32h7.cCraig Hesling2020-03-201-70/+244
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This cleans up and modularizes the clock configuration code for the STM32H743. This makes it easier and cleaner to add the STM32H7A3 variant. This brings no functional change, as coarsely verified with crrev.com/c/2096017 . BRANCH=icetower BUG=b:130296790 TEST=Verified all impacted registers values with and without this change using crrev.com/c/2096017 on the Nucleo-H743ZI. The sequence of commands used to test was the following: # After fresh startup (from reset) * > clock * > clock hsi * > clock pll * > clock hsi * > clock hsi * > clock * > waitms 5000 * # Run timer to check accuracy of 5 seconds * > clock pll * > waitms 5000 * # Still broken -> Watchdog should still kick-in early and render MCU unusable. Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4fbf6982190c0d660e31c2027b5ad07cae48755e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2095853 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* chip: stm32: fix TIM9 interrupt for STM32F412Virendra Kakade2020-03-201-0/+4
| | | | | | | | | | | | | | | | | | | | | Currently the TIM9 global interrupt is mapped to 25 instead of 24 which causes the interrupt to not work. Fix this by changing the mapping. RM0402 STM32F412 reference manual: Vector table for STM32F412xx (table 40); TIM1_BRK_TIM9 entry. BUG=none BRANCH=none TEST=make -j4 buildall TEST=TIM9 interrupt works after this change on STM32F412 board. Signed-off-by: Virendra Kakade <virendra.kakade@ni.com> Change-Id: I18ee7cda79e78c01bc561b1d70d2a25fa3aed5a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2098872 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org> Tested-by: Craig Hesling <hesling@chromium.org>
* Rename Cortex-M MMFS to CFSRPeter Marheine2020-03-191-6/+6
| | | | | | | | | | | | | | | | | Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR; the Configurable Fault Status Register. MMFS is the low byte of this value, so it's misleading to refer to the whole 32-bit value as MMFS; instead call it CFSR to make it clear that the value we store encompasses the MMFSR, BFSR and UFSR. BUG=None BRANCH=None TEST=make buildall Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807 Reviewed-by: Keith Short <keithshort@chromium.org>
* it83xx/clock: Disable voltage comparator modules in hibernateRuibin Chang2020-03-132-1/+10
| | | | | | | | | | | | | | | | | | | | | Disable all voltage comparator modules in hibernate for better power consumption. vcmp_enable() is moved out of #ifdef to avoid implicit declaration error, because whether we define the CONFIG_ or not, compiler always checks if (IS_ENABLED(CONFIG_)) { } block codes. BUG=none BRANCH=none TEST=check voltage comparator control registers by console Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I4ab10a0a67cf00e5d697a2298711e589ccbc8eab Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2097802 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* stm32: pwm: fix timer PSC register calculationVirendra Kakade2020-03-131-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | The timer PSC register value is calculated based on the cpu clock frequency but it should actually be based on the timer clock frequency. Timer clock frequency and cpu clock frequency may be the same or different based on the STM32 variant. Example: In the STM32F412 case, timer freq = cpu freq * 2. This leads to incorrect PSC calculation based on old formula, ultimately leading to a frequency twice that of requested. BUG=none BRANCH=none TEST=make -j4 buildall TEST=verified that I got expected frequency on a stm32f412 pwm output with this change. Change-Id: I9ff954cf6304507f7506f5cf974857f6c3140b4e Signed-off-by: Virendra Kakade <virendra.kakade@ni.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2096841 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org>
* stm32: Fix manual interrupt clearing functionCraig Hesling2020-03-121-1/+3
| | | | | | | | | | | | | | | | | | | This fixes a bug in gpio_clear_pending_interrupt, where all pending interrupts are unintentionally cleared. This is not in the code path for normal gpio interrupt handlers, since the normal interrupt clearing occurs in gpio_interrupt (right below this function). BRANCH=none BUG=chromium:1059520 TEST=none Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I4d6fe7947f4d76cf3b57dfbf3bb926e41851c80c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2101208 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* max32660: enabled gpio interrupts and fixed gpio level interruptsJerry Bradshaw2020-03-111-18/+37
| | | | | | | | | | | | | | | | Adds enabling gpio interrupts in the gpio_init routine. The initialization of the gpio level interrupts fixed. BRANCH=none BUG=none TEST=GPIO interrupts tested for each GPIO pin. Rising, Falling, and Level interrupts tested. Change-Id: I83c625be8056831abfb3af7a6ebeec33d1651a73 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092208 Reviewed-by: Tai-Hsu Lin <sheckylin@chromium.org> Tested-by: Tai-Hsu Lin <sheckylin@chromium.org> Commit-Queue: Harry Cutts <hcutts@chromium.org>
* npcx/lpc: Don't enable PM channel OBE interrupt at initWealian2020-03-111-3/+2
| | | | | | | | | | | | | | | | | | Like what is done in the CL:2073282 for KBC. OBE interrupt enable shouldn't be set in lpc_init(). The default value of OBF bit is 0. It's will send a spurious interrupt to NVIC. BUG=none BRANCH=none TEST=No error for "make buildall" TEST=Test host command on yorp overnight by the following command: "while true; do ectool version; done" Change-Id: If9172a18b737f2d6c3c7930fcdc9aaf5ef4c8533 Signed-off-by: Wealian <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2091133 Reviewed-by: Edward Hill <ecgh@chromium.org>
* it83xx/adc: add voltage comparator featureRuibin Chang2020-03-115-0/+241
| | | | | | | | | | | | | | | | | | | | Add voltage comparator feature. BUG=b:149094481 BRANCH=none TEST=on board it83xx_evb, 1.set VCMP1 threshold 2.8v: external input 3v, the INT would be triggered and ADC5 read the correctly voltage. 2.set VCMP0 threshold 0.2v: external input 0v, the INT would be triggered and ADC5 read the correctly voltage. Change-Id: I59510b1c6bd38004ff06e0fcbd2a671e895d59e3 Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2062110 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* keyboard: Add a new config for the keyboard customizationZhuohao Lee2020-03-101-3/+9
| | | | | | | | | | | | | | | In order to support a non-chromeos keyboard matrix, we can add a new config CONFIG_KEYBOARD_CUSTOMIZATION to customize the keyboard matrix in the board setting. BUG=b:148034320 BRANCH=firmware-hatch-12672.B TEST=build pass Change-Id: I6a32a1f79aeb09805c5f47f8540ea25f67a34f7f Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2035444 Reviewed-by: Jett Rink <jettrink@chromium.org>
* max32660: make methods static in UART codeHarry Cutts2020-03-101-23/+11
| | | | | | | | | | | | | | | Also removed a couple of unused methods and replaced `unsigned` with `unsigned int` in a couple of places pointed out by the presubmit check. BUG=none TEST=Board using MAX32660 builds successfully, has functioning console BRANCH=none Change-Id: I596410e5fb8b78e5325bbe726a710ae476968a71 Signed-off-by: Harry Cutts <hcutts@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2095847 Reviewed-by: Tai-Hsu Lin <sheckylin@chromium.org> Commit-Queue: Tai-Hsu Lin <sheckylin@chromium.org>
* remove cr50 related filesNamyoon Woo2020-03-096-159/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:149350081 BRANCH=none TEST=build all, and emerged ec related packages for host and octopus. $ make buildall -j $ cros_workon --host list chromeos-base/chromeos-cr50-dev chromeos-base/chromeos-ec chromeos-base/chromeos-ec-headers chromeos-base/ec-devutils chromeos-base/ec-utils chromeos-base/ec-utils-test dev-util/hdctools $ sudo emerge chromeos-cr50-dev -j $ sudo emerge chromeos-ec -j $ sudo emerge chromeos-ec-headers -j $ sudo emerge ec-devutils -j $ sudo emerge ec-utils -j $ sudo emerge ec-utils-test -j $ sudo emerge hdctools -j $ cros_workon-octopus list chromeos-base/chromeos-ec chromeos-base/chromeos-ec-headers chromeos-base/ec-devutils chromeos-base/ec-utils chromeos-base/ec-utils-test dev-util/hdctools $ sudo emerge-octopus chromeos-ec -j $ sudo emerge-octopus chromeos-ec-headers -j $ sudo emerge-octopus ec-devutils -j $ sudo emerge-octopus ec-utils -j $ sudo emerge-octopus ec-utils-test -j $ sudo emerge-octopus hdctools -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: If751b26b0635b0021c077338e96eaa8e8dcf17a5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2080631 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* remove board/cr50 and chip/gNamyoon Woo2020-03-03107-53032/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes cr50 related files from platform/ec. BUG=b:149350081 BRANCH=none TEST=$ make buildall -j $ cros_workon --host list chromeos-base/chromeos-cr50-dev chromeos-base/chromeos-ec chromeos-base/chromeos-ec-headers chromeos-base/ec-devutils chromeos-base/ec-utils chromeos-base/ec-utils-test dev-util/hdctools $ sudo emerge chromeos-cr50-dev -j $ sudo emerge chromeos-ec -j $ sudo emerge chromeos-ec-headers -j $ sudo emerge ec-devutils -j $ sudo emerge ec-utils -j $ sudo emerge ec-utils-test -j $ sudo emerge hdctools -j $ cros_workon-octopus list chromeos-base/chromeos-ec chromeos-base/chromeos-ec-headers chromeos-base/ec-devutils chromeos-base/ec-utils chromeos-base/ec-utils-test dev-util/hdctools $ sudo emerge-octopus chromeos-ec -j $ sudo emerge-octopus chromeos-ec-headers -j $ sudo emerge-octopus ec-devutils -j $ sudo emerge-octopus ec-utils -j $ sudo emerge-octopus ec-utils-test -j $ sudo emerge-octopus hdctools -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: Ifa3a037fff17177204ce1a9b88474490fb9be3ed Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2083659 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* include/lpc.h: Expose lpc_aux_put_charRaul E Rangel2020-03-021-3/+8
| | | | | | | | | | | | | | | * Expose lpc_aux_put_char so we can call it from common/keyboard_8042. * Renamed lpc_mouse_put_char to lpc_aux_put_char so it's more generic. * Added the send_irq parameter for parity with lpc_keyboard_put_char. BUG=b:145575366 BRANCH=none TEST=Verified it builds Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I61854ed7c9b9ad1c50e55735747cfb25ca15762b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2079694 Reviewed-by: Edward Hill <ecgh@chromium.org>
* common/system: Unify ec_current_image and system_image_copy_tTom Hughes2020-02-2811-86/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "enum ec_current_image" is exposed in ec_commands.h (and used by non-EC code, such as biod). We also have an "enum system_image_copy_t" that is the exact same thing (though has a few more definitions). A followup CL (I714b6bd8c0d7192386404c25a831e38438fa5238) adds the "sysinfo" host command, so we want to be able to expose all the potential image variants. Rather than maintain two enums that can potentially get out of sync, unify the code to use a single enum. We choose to keep the "enum ec_current_image", since external code depends on it. To verify that this change results in no changes to the generated binaries: ./util/compare_build.sh --board all BRANCH=none BUG=b:146447208 TEST=./util/compare_build.sh --board=all Change-Id: I13776bc3fd6e6ad635980476a35571c52b1767ac Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036599 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* chip/npcx/lpc: Don't enable Output Buffer Empty by defaultRaul E Rangel2020-02-271-2/+2
| | | | | | | | | | | | | | | OBE is enabled by lpc_keyboard_put_char and lpc_mouse_put_char and the disabled by lpc_kbc_obe_interrupt. No reason to enable the interrupt on initialization. BUG=b:145575366 BRANCH=none TEST=Verified OBE interrupt still fires. Change-Id: Iba3f97b2bf4a6c5f09833f808c52901bd8406b4f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2073282 Reviewed-by: Edward Hill <ecgh@chromium.org>
* chip/npcx/lpc: Set bit 5 when sending AUX responses.Raul E Rangel2020-02-271-0/+5
| | | | | | | | | | | | | | The linux kernel expects bit 5 to be set in the status register when the output buffer contains and AUX packet. BUG=b:145575366 BRANCH=none TEST=Verified bit 5 is set when sending aux packets Change-Id: I0d3944ea6fd04224d9f9bcf0e1b0b3c8633ad786 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2073281 Reviewed-by: Edward Hill <ecgh@chromium.org>
* chip/nxcp/lpc: Fix race condition when reading 8042 data.Raul E Rangel2020-02-271-4/+9
| | | | | | | | | | | | | | | | | When reading NPCX_HIKMDI it deasserts the IBF status flag. This means the AP is allowed to write to the input buffer. Because NPCX_HIKMDI is read twice, that means the AP could have written to the input buffer between reads. This results in losing one of the interrupts. This only happens if DEBUG_LPC is enabled. BUG=b:145575366 BRANCH=none TEST=Verified we don't lose any writes by examining logs. Change-Id: I2904c316fcad55001e8d297f4a0a73073b07702b Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2073280 Reviewed-by: Edward Hill <ecgh@chromium.org>
* c2d2: add support for I2C-based flashingJett Rink2020-02-272-4/+22
| | | | | | | | | | | | | | | | Add necessary console command to allow C2D2 to pass through i2c bus for ec and ap. Also hook into common ite programming mode code. BRANCH=servo BUG=b:148610186,b:147381671 TEST=flash ampton with C2D2 adapter Change-Id: I1d9b20684b45ff0d101b9cfff8b0b0a85e6c0c70 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064594 Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-by: Matthew Blecker <matthewb@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* ish: chip level enablement for ish5.4 PMLeifu Zhao2020-02-273-32/+175
| | | | | | | | | | | | | | | | | Chip level power management enablement for ish5.4. BUG=b:149238813 BRANCH=none TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp. Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: Icc554a68fe57970bcaa7be457f56db34067858d9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055895 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* ish: infrastructure changes to support ish5.4 PMLeifu Zhao2020-02-277-46/+105
| | | | | | | | | | | | | | | | | | Infrastructure related changes to support enabling power management for ish5.4 on tgl rvp platform. BUG=b:149238813 BRANCH=none TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp. Signed-off-by: Leifu Zhao <leifu.zhao@intel.com> Change-Id: I50b6f1a4fe9c14f9479af2a2a438ec7395ec27a1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056149 Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
* max32660: add I2C board support for stand-alone read transactionsJerry Bradshaw2020-02-262-70/+134
| | | | | | | | | | | | | | | | | | | Adds support for solitary I2C board read transactions that are not preceded with an I2C write. BRANCH=none BUG=none TEST=Slave tested with EC CMDs and board cmds sent from a custom written EC HOST using another MAX32660 device as an I2C Master. Tested with Raspberry PI that emulates EC HOST and board commands. Change-Id: I653fd2bd9d4799c7e9cec4561906f0afe92c458c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1939779 Reviewed-by: Jes Klinke <jbk@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org> Reviewed-by: Tai-Hsu Lin <sheckylin@chromium.org> Tested-by: Tai-Hsu Lin <sheckylin@chromium.org> Commit-Queue: Harry Cutts <hcutts@chromium.org>
* cleanup: tab over register valuesJett Rink2020-02-251-20/+20
| | | | | | | | | | | | | | Tab over register values underneath the register definition for consistent style. BRANCH=none BUG=none TEST=none Change-Id: I823a454fc57d4ee455c9efb693baff8838bc7d3c Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2067158 Reviewed-by: Diana Z <dzigterman@chromium.org>
* cleanup: move voltage rail detection to commonJett Rink2020-02-251-3/+17
| | | | | | | | | | | | | | Single source the VDD rail sagging reset interrupt Add VDD detection to C2D2 as well. BRANCH=servo BUG=none TEST=builds Change-Id: Iceac7d9fa7a9bde5a3c23c36e63b6d635d8812a3 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064593 Reviewed-by: Diana Z <dzigterman@chromium.org>
* servo_micro: move ite flashing codeJett Rink2020-02-252-0/+336
| | | | | | | | | | | | | | | | In preparation for servo_micro and c2d2 to sharing the ite, i2c flashing code, move it to a stm specify common file. It is STM specific because it explicitly uses STM registers to accomplish the non-compliant i2c waveforms needed to put the ITE EC into flash mode. BRANCH=servo BUG=b:148610186,b:79684405 TEST=flash ampton with servo_micro using this code Change-Id: Ia0f3f944df2f8a8ad47ea5a62c5f0edae2c71943 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2064592 Reviewed-by: Diana Z <dzigterman@chromium.org>
* it83xx/dac: add DAC moduletim2020-02-214-1/+156
| | | | | | | | | | | | | | | | | | The DAC module has four channels. We can set output voltage when DAC channel is enabled by this driver. BUG=b:149094279 BRANCH=none TEST=The console command #dac set as follows: read: dac [ch] write: dac [ch] [voltage] [ch]:2-5, [voltage]:0(disable)-3300 Change-Id: I8e815cb5bc749467581d5f771fd6f9e0995fca3b Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2046685 Reviewed-by: Diana Z <dzigterman@chromium.org>
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