| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add the following features to support z-state for Asurada.
1) Call chip_save_reset_flags() before entering
board_hibernate_late() to make sure the hibernate flag
saved before ec powered off.
2) Handle the second ec reset correctly if
CONFIG_BOARD_RESET_AFTER_POWER_ON enabled.
BUG=b:163963220
TEST=Check the reset cause under following cases:
1) boot from z-state -> reset-pin power-on hibernate initial-pwr
2) boot from cutoff -> reset-pin power-on initial-pwr
3) `ecrst pulse` in cr50 console
-> reset-pin power-on initial-pwr
BRANCH=none
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I176075ea2b3f6b2abbfe22e47f3019ee23af57a0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2371751
Tested-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We have used both methods of waking up the PD tasks to process the next
state: PD_EVENT_SM and TASK_EVENT_WAKE. They effectively do the same
thing and it is more straightforward to only have one way to wake the
task up with the sole purpose of re-evaluating the current state.
BRANCH=none
BUG=none
TEST=No regressions on GRL testing.
Signed-off-by: Jett Rink <jettrink@chromium.org>
Change-Id: I0fa79b82223e6b97eede4130480156949d79f365
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2363466
Reviewed-by: Edward Hill <ecgh@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
| |
BUG=none
BRANCH=none
TEST=No error on the command of get EC protocol info.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I08d87bd20e60520c891f1b99d78ff91c1e89b2cb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2359613
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add the following changes:
1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to
define what (RAM, flash, features...) are supported in npcx7m7fc.
2. add the chip id and chip revision id of npcx7m7fc
BRANCH=none
BUG=b:163910671
TEST=pass "make buildall"
TEST=with related CLs, change CHIP_VARIANT to npcx7m7fc in
board/npcx7_evb/build.mk; flash image and run on the internal testing board of
npcx7m7fc; make sure the EC can boot up; check the chip ID and chip
revision ID are correct by console command "version".
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Ibef17148eeba71bbbb63145064a5fa398c0118dc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355156
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
_Noreturn was added in C11 and the convenience macro "noreturn" is
specified by stdnoreturn.h:
https://en.cppreference.com/w/c/language/_Noreturn.
BRANCH=none
BUG=none
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I30361bb5290cea1c776a7356f7e3a68edf1f8e39
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324816
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
For chip it8xxx2 series and it8320dx, we set embedded flash clock
48MHz as default.
BUG=none
BRANCH=none
TEST=build all
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I100d70fbf80430ae98fa14c557886c4a37d8b93a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355164
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Instead of asserting that task_start() has not been called,
just return without doing any locking.
This avoids the need to fix every caller of mutex_lock() to check
task_start_called().
BUG=b:164461158
BRANCH=none
TEST=Esc+F3+Power enters recovery, does not assert.
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: Ic157d7e7041185a67f257f0f5710fd02e45cd77f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2357496
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Tested-by: Wai-Hong Tam <waihong@google.com>
Commit-Queue: Wai-Hong Tam <waihong@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable IT83XX_SPI_RX_VALID_INT which can obtain data length field of
host requested. When received data to reach, Rx valid interrupt will
be fired then start to parse.
Instead of waiting for Rx 256 bytes reach interrupt method, this is
effectively saving time to complete once transaction.
BUG=b:160662061; b:161509047
BRANCH=none
TEST=Boot to kernel with it81202 on asurada.
No error on the command of get EC protocol info with
1MHz clock frequency.
Change-Id: Ib56e3034d3ee39fa64818b95747eb7e9e5821294
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076826
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We missed it when ADC accuracy initialization, let's fix it.
BUG=b:164011390
BRANCH=none
TEST=ADC accuracy is in +/- 4LSB.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Id40adbdc6823fbf3db506681ce4bff6a2f32b843
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355166
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Tested-by: Parker Lin <parkerlin@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Google is working to change its source code to use more inclusive
language. To that end, replace the term "sanity" with inclusive
alternatives.
BUG=b:163885307
BRANCH=None
TEST=make -j buildall
TEST=grep -ir sanity
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I487a50999d506a0337f1d3fbe173f193e5e4098a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2353516
Reviewed-by: Sam Hurst <shurst@google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
EC images are copied in full from flash to RAM. When the code RAM size
is smaller than 1/2 the flash size, the EC image size is limited to the
code RAM size, leaving unused flash space.
Create a new linker section .init_rom used to store data objects that
are single use in the previously unused flash area. Data objects can be
used at runtime by copying into RAM using the flash_read() function.
This change is tied to the NPCX flash layout, with asserts to ensure
builds fail if the CONFIG_CHIP_INIT_ROM_REGION is not supported by
the chip.
CLs that enable CONFIG_CHIP_INIT_ROM_REGION should not be merged until
the predecessor CL:2325764 is available in CPFE images.
BUG=b:160330682
BRANCH=none
TEST=make buildall
TEST=With debug code, use the _init_rom macro and validate the data can
be read using flash_read().
TEST=Using hex editor, verify .init_rom section located at 192K boundary
and unused bytes are filled with 0xFF.
TEST=compare_build.sh passes when run against waddledoo (npcx, cortex-m)
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ia0785798fd1938ad6a1c254a070b219027ee82a3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311268
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL adds the i2c driver for stm32g4 chip family. The i2c block for
stm32g4 is very similar to that of stm32l4 chip family. The g4 driver
is mostly copied from the L4 version of the i2c driver. However, the
driver only currently supports master mode.
BUG=b:148493929
BRANCH=None
TEST=run i2scan on EC console
> i2cscan
Scanning 0 usbc.................
0x18.
0x19.
0x1a.
0x1b.
0x1c.
0x1d.
0x1e.
0x1f.
0x20.
0x21.
0x22.
0x23.
0x24.
0x25.
0x26.
0x27...........................
0x42..............................
0x60.......................
Scanning 1 usb_mst.
0x08.
0x09.
0x0a.
0x0b.
0x0c.
0x0d.
0x0e.
0x0f.
0x10.
0x11.
0x12.
0x13.
0x14.
0x15.
0x16.
0x17...
0x1a...........................
0x35............
0x41.........
0x4a.
0x4b......................
0x61......................
Scanning 2 eeprom.........................................
0x30................................
0x50.......................................
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Id8b7472e579bae17360a0122fe2b12a333139cfa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2161580
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The clock frequency macro added in previous CL was missing the
'0'. This CL fixes that error and makes a minor change to how the
flash wait state value is configured. Previously, setting of the wait
state field was disabling instruction/data cache until it was restored
in the next instruction. This results in swd debugger not remaining
attached.
BUG=b:148493929
BRANCH=None
TEST=verified console is working and debugger remains attached after
setting wait state to the correct value.
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I65e3a22e36de0bbf14926e5687a995b7e5717e7f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340695
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enlarges the stack size of idle task from 256 to 640.
BRANCH=none
BUG=b:163459890
TEST=$ r() {
echo stop >/sys/class/remoteproc/remoteproc0/state
echo start >/sys/class/remoteproc/remoteproc0/state
}
$ r
$ r
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I6d887262f39ff32bdb1b86aba59759917a0a95d1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2351640
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
BRANCH=none
BUG=b:160382789
BUG=b:163459890
TEST=1. remove hostcmd task from ec.tasklist
2. make BOARD=asurada_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: Ia92abeccd5fba8862563a200cbdcf4ce461f4106
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2351639
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
mutex_lock() must not be used in interrupt context. Add an assert
to catch this.
Also assert task_start_called() since task ID is not valid
before this.
Also remove an old assert since comparing id with TASK_ID_INVALID
doesn't make sense.
Add check for task_start_called() for NPCX flash_lock, I2C port_mutex,
pwr_5v_ctl_mtx, STM32 bkpdata_write_mutex.
This was submitted CL:2309057, reverted CL:2323704, submitted
CL:2335738, reverted CL:2341706.
BUG=b:160975910
BRANCH=none
TEST=boot AP, jump to RW
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: I0aadf29d073f0d3d798432099bd024a058332412
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2343450
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This reverts commit 8d46141f4d45c65712a9ca7509b7b60128fa4d89.
Reason for revert:
getting EC boot loop on volteer:
(note that you have to flash EC-RO to get this)
20-08-07 00:22:33.520 --- UART initialized after reboot ---
20-08-07 00:22:33.531 [Image: RO, volteer_1.1.9999-4284ce1 @caveh]
20-08-07 00:22:33.531 [Reset cause: reset-pin]
20-08-07 00:22:33.531 [0.005149 KB boot key mask 0]
20-08-07 00:22:33.543 [0.005438 init buttons]
20-08-07 00:22:33.543 [0.005669 VB Main]
20-08-07 00:22:33.543 [0.005872 VB Ping Cr50]
20-08-07 00:22:33.543 [0.007148 hash start 0x00040000 0x0002f61c]
20-08-07 00:22:33.833 [0.300169 hash done e4ddc3d0ffd015db085389d94faa38d3922e42290b6887baa8de3067ce846c13]
20-08-07 00:22:33.833 [0.300289 VB Verifying hash]
20-08-07 00:22:33.833 ��������������������������������EC\0\0 �������S��O�8Ӓ.B)h����0g΄l[0.317577 VB Received 0xec00]
20-08-07 00:22:33.850 [0.317899 Jumping to image RW]
20-08-07 00:22:33.850
20-08-07 00:22:33.850 ASSERTION FAILURE '!in_interrupt_context() && task_start_called()' in mutex_lock() at core/cortex-m/task.c:868
20-08-07 00:22:33.861
20-08-07 00:22:33.861 === HANDLER EXCEPTION: 00 ====== xPSR: 0000000a ===
20-08-07 00:22:33.861 r0 :00000364 r1 :100b6815 r2 :100b72ab r3 :100956bd
20-08-07 00:22:33.873 r4 :dead6663 r5 :00000364 r6 :200c1c20 r7 :00000001
20-08-07 00:22:33.873 r8 :00001388 r9 :100b4108 r10:100b4158 r11:00000013
20-08-07 00:22:33.884 r12:10095811 sp :200c0320 lr :200c1c20 pc :200c14f8
20-08-07 00:22:33.884
20-08-07 00:22:33.884 cfsr = 0, shcsr = 70000, hfsr = 0, dfsr = 0
20-08-07 00:22:33.884
20-08-07 00:22:33.884 =========== Process Stack Contents ===========
20-08-07 00:22:33.889 00000000: 100cfc00 00002a3d 00002751 00002731
20-08-07 00:22:33.901 00000010: 00002741 00002711 000027e1 00002791
20-08-07 00:22:33.901 00000020: 000027a1 000027b1 00002771 000027c1
20-08-07 00:22:33.901 00000030: 00002721 00002781 00002761 000027d1
20-08-07 00:22:33.906
20-08-07 00:22:33.906 Rebooting...
20-08-07 00:22:33.996
20-08-07 00:22:33.996
20-08-07 00:22:33.996 --- UART initialized after reboot ---
Original change's description:
> task: Fix mutex_lock() assert (reland)
>
> mutex_lock() must not be used in interrupt context. Add an assert
> to catch this.
>
> Also assert task_start_called() since task ID is not valid
> before this.
>
> Also remove an old assert since comparing id with TASK_ID_INVALID
> doesn't make sense.
>
> This was first submitted as CL:2309057, then reverted by CL:2323704
> because it broke jump to RW (b/162302011). Fix this by adding check
> for task_start_called() to chip/npcx/flash.c and common/i2c_master.c.
>
> BUG=b:160975910
> BRANCH=none
> TEST=boot AP, jump to RW
>
> Signed-off-by: Edward Hill <ecgh@chromium.org>
> Change-Id: I070a265a95d2128643b536814e608509d81adbe3
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738
> Reviewed-by: Raul E Rangel <rrangel@chromium.org>
> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Bug: b:160975910
Change-Id: I9e37b1eac7344cddbd756fb45b130d7e0aee661b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2341706
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
mutex_lock() must not be used in interrupt context. Add an assert
to catch this.
Also assert task_start_called() since task ID is not valid
before this.
Also remove an old assert since comparing id with TASK_ID_INVALID
doesn't make sense.
This was first submitted as CL:2309057, then reverted by CL:2323704
because it broke jump to RW (b/162302011). Fix this by adding check
for task_start_called() to chip/npcx/flash.c and common/i2c_master.c.
BUG=b:160975910
BRANCH=none
TEST=boot AP, jump to RW
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: I070a265a95d2128643b536814e608509d81adbe3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Reading HIKMDI causes the IBF flag to deassert and allows
the host to write a new byte into the input buffer. So if we
don't capture the status before reading HIKMDI we will race
with the host and get an invalid value for HIKMST.A20.
BUG=b:162539945, b:157617092, b:159282882
BRANCH=none
TEST=Boot ezkinil and make sure keyboard still functions.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia8dcd18e3de31b4fa8c1742c7604d5c39e80dc51
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2341090
Commit-Queue: Edward Hill <ecgh@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC to let board config
their wake pins at runtime.
BUG=b:162814191
TEST=make
BRANCH=master
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Iae2072ec7239a0daa84222c23733b90153e732f1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340730
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Google is working to change its source code to use more inclusive
language. To that end, replace the term "dummy" with inclusive
alternatives.
BUG=b:162781382
BRANCH=None
TEST=make -j buildall
`grep -ir dummy *`
The only results are in "private/nordic_keyboard/sdk8.0.0"
which is not our code.
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
BUG=b:162805450
BRANCH=none
TEST=not yet
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ie1525b8a0f67a4700649163b536d09bef9a9671a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335518
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Interrupt mechanism of MT8192 SCP has 3 tiers: INTC, global VIC,
local VIC (in RV33).
+------+ +-------------+ +----------------+
| | | | | |
UART TX -----| |--GROUP 0 --| | | |
UART RX -----| INTC |--GROUP 1 --| Global VIC | | Local VIC |
Timer 0 -----| |--GROUP 2 --| | | |
Timer n -----| | . | (MIEMS, |-----| (INTC_IRQ_OUT, |
. | | . | MICAUSE, | | INTC_IRQ_...) |
. | | . | MIXXXX...) | | |
GIPC 0 -----| |--GROUP 14--| | | |
. +------+ +-------------+ +----------------+
GVIC latches from INTC at a time and notifies LVIC if any group is
asserted.
For example, suppose UART TX corresponds to group 12 and GIPC 0
corresponds to group 7:
(1) GIPC 0 and UART TX are asserted.
(2) GVIC notifies LVIC about the interrupt.
(3) RV33 finds group 7 and group 12 (from INTC_IRQ_OUT) are asserted.
Note that it is a fatal error if RV33 cannot find the corresponding
groups in (3).
GVIC caches the group 7 and group 12 until RV33 writes to bit 7 and bit
12 of MIEMS. Even though the interrupt source is de-asserted, the GVIC
cache won't get updated.
The most suggested way to handle interrupt in RV33: batch handle them.
However, EC OS doesn't handle multiple interrupts at a time. EC OS
handles 1 interrupt, acknowledges by writing 1 bit in MIEMS, and sees
if further interrupts from GVIC.
UART TX interrupt can be easily cleared by calling cflush() in anywhere.
To avoid the interrupt source of UART TX being cleared in other ISR,
don't unset the THRI flag unless we are in the UART ISR.
BRANCH=none
BUG=b:157541273
TEST=call cflush() in any ISR
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I2fab7308edce386ea65d0d45e39805d8cc7f4857
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2331984
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement detect cc disconnection interrupt for source. When TCPC
detect SNK/audio/debug device plug out (cc lines open), TCPC can
interrupt pd task to update cc state.
BUG=b:160548079
BRANCH=none
TEST=test on board reef_it8320, it81202_pdevb with TCPMv1, TCPMv2.
Connect to dongle, adapter and DRP, check
1.Plug in/out interrupt fire correctly.
2.Power role swap can state to SRC_READY and SNK_READY.
3.When partner disconnect, we discharge Vconn within
tVconnOFF(35ms).
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: I58bc8a5a9289df4ea4e8b3efec000d3a9ab1cb5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2294626
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL adds changes to enable clocks and configure the uart speed for
stm32g4 chip family.
BUG=b:148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I5600ed64867192fe77fd85fc3dbc0a63f912d738
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195550
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The STM32G4 family chips have similar DMA engine as some other STM32
families and therefore most of DMA code can simply be used as
is. However, the STM32G4 does have a DMAMUX and so the correct
peripheral request must be set.
BUG=b:148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I2694881f97558ea7b904a9b83ee20d9ec813c273
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195549
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
If CONFIG_CHIPSET_RESUME_INIT_HOOK is defined, move the SPI
enable/disable to different hooks, i.e.
* RESUME_INIT instead of RESUME
* SUSPEND_COMPLETE instead SUSPEND
The SPI interface has to be enable earlier than other hooks
to receive a host sleep event.
BRANCH=None
BUG=b:148149387
TEST=make buildall -j
Change-Id: Ic56a7b5ef20fb8258487d1d350fc5f8a55e33049
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324989
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In the RTC interrupt, it calls host_set_single_event() directly, that
eventually tries to lock a mutex. Trying to lock a mutex in the
interrupt context should be forbidden. So move the call to a deferred
function.
BRANCH=None
BUG=b:162434716
TEST=Build the board scarlet, which uses stm and enables RTC host
command.
Change-Id: I3f5ab85549a801f4f5d72cf5661a65c9f9d28e0c
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2327249
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In the RTC interrupt, it calls host_set_single_event() directly, that
eventually tries to lock a mutex. Trying to lock a mutex in the
interrupt context should be forbidden. So move the call to a deferred
function.
BRANCH=None
BUG=b:162434716
TEST=Running suspend_stress_test doesn't result any EC crash.
Change-Id: I80d1f1d8cefa4b8d01e707edff602dfdc860fc35
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2327248
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL adds clock enable support for stm32g4 family.
BUG=b:148493929
BRANCH=None
TEST=verfied that via scope that led toggle happens at 1 second window
when using one second hook call.
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Ie3d353ec40206e93cfac7b8738166ffee6c8442c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195548
Tested-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL adds stm32g4 chip specific changes. Most of gpio code can be
reused as is. This file enables clocks and IRQs for supported GPIO
banks. This was based on F4 family as the reference.
BUG=b:148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I47d0b08675b53597b5a0e938d576682e63cc59e0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195546
Tested-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL adds support to configure rcc module for stm32g4. The driver
from the F4 family was used as a reference. Support for RTC was not
ported as it's not being used for honeybuns.
The function wait_for_ready() was moved to the common clock file for
the F-family so it would not need to be replicated for G4 as well.
BUG=148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I980c8889965a2e5da401ccd6291079a0bdfa8e4f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195545
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL updates stm32 specific system.c for the stm32g4 chip family. A
comment was added to clarify what's required for enabling the backup
domain. In addition, debug mode and detection of a warm boot.
BUG=b:148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I8b5063419ae6dc1be165b8bb3754703c1e728ae9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195544
Tested-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL adds config-chip for stm32g41xb variant of the stm32g4 chip
family.
BUG=148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I418179153b631e2d7abb597fbf77374f94c4c501
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195543
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The initial version of this file had a cut/paste error. Fixing the
base address for APB1 bus
BUG=148493929
BRANCH=None
TEST=make BOARD=quiche is successful
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I5c2abc0342bde4a66f166f87971617110c5acfd5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324403
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Google is working to change its source code to use more inclusive
language. To that end, replace the terms "whitelist", "blacklist",
and similar with inclusive alternatives.
BUG=b:162262297
BRANCH=None
TEST=`grep -Eirl "(white|black)[ _\-]*list" .`
The only results are in "private/nordic_keyboard/sdk8.0.0"
which is not our code.
Signed-off-by: Paul Fagerburg <pfagerburg@google.com>
Change-Id: Ie5210b98e1096c22d0e9284c101a42820bd3d79d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2321549
Tested-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
wait_for_ready is a generic function which loops until bits in a
register are set. This patch move it to util.c to make it available
for all.
There are more places where the function is applicable but this CL
keeps the scope under chip/stm32/clock-stm32. There is no
functionality change.
BUG=none
BRANCH=none
TEST=buildall
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I796599344c1d86ab7144d1d6b434ec54cf1cc55d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2317887
Reviewed-by: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Adds the USB SPI protocol V2, this protocol supports larger
SPI transfers that are delivered in multiple USB packets.
This enables us to perform 2 optimizations on the USB SPI
transfer speed for large USB packets:
* USB packets can be grouped together reducing the total
number of packets exchanged. The host can write multiple
data sections sequentially without the device responding
with a packet for each one. Going the other direction,
the host can continue to poll the device for data until
the transmission is complete.
* Only a single SPI transaction is required, this eliminates
overhead in setting up and getting data from SPI transactions.
Benchmark results show a typical 35% improvement in performance
on Servo Micro platforms with these changes on operations which
involve large SPI transfers reading or writing from the flash.
Signed-off-by: Brian Nemec <bnemec@chromium.org>
Blocked on upstream changes to flashrom:
Depends-On:https://review.coreboot.org/c/flashrom/+/41533
BUG=b:139058552
BRANCH=servo
TEST=Tested with Servo Micro with the reading, erase, write,
and verify operations with updated copies of flashrom.
Change-Id: I04b6cf8449e32cc1b75d3501939958887eb57f5b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224765
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Brian Nemec <bnemec@chromium.org>
Tested-by: Brian Nemec <bnemec@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL adds the registers definition file for stm32g4. It was based
off the registers file for the stm32f4 chip family.
BUG=b:148493929
BRANCH=None
TEST=verfied that the GPIO, clocks, and EC console over LPUART
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I4de8e4ed955714d35e75e0c0c5de83a3d8c4c996
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2092492
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement fast role swap function from initial SNK to new SRC
for chip it8320 and it81202.
BUG=none
BRANCH=none
TEST=1.When we detect FRS cc low signal, we can output properly
GPIO signal.
2.FRS false-positives test: PD traffic(ex.power nego,
data and power swap, soft and hard reset) on the CC line
after FRS is enabled.
Change-Id: I3a7bc6a684e57fb19e50c41305751b2fca1ffe2d
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1786462
Reviewed-by: Diana Z <dzigterman@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Google is working to change its source code to use more inclusive
language. To that end, replace the terms "sane", "sanity check", and
similar with inclusive/non-stigmatizing alternatives.
BUG=b:161832469
BRANCH=None
TEST=`make buildall -j` succeeds. `grep -Eir "sane|sanity" .` shows
results only in third-party code or documentation.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I29e78ab27f84f17b1ded75cfa10868fa4e5ae88c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311169
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
BUG=b:161327069
BRANCH=none
TEST=No complaining bad data from SPI continuously after sysjump.
NOTE:
We might get one bad data message after sysjump
(eg: "sysjump rw" command). Because EC isn't ready to receive
data but request from AP might be already started.
Change-Id: Ibe83c0b54c234022338a30c35b1b0564f7e5f266
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2301323
Tested-by: Eric Yilun Lin <yllin@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Adds memory maps for mapping SCP address to AP address and vice versa.
BRANCH=none
BUG=b:146213943
BUG=b:156222459
TEST=make BOARD=asurada_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I5e5e34044f54d304bcbe591bf48d6e955d4ed512
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2306900
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
| |
BRANCH=none
BUG=b:146213943
BUG=b:160382789
TEST=make BOARD=asurada_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: Ifc2cfc127213c6951eab1aea733a6e90e3594827
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2299601
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Supports IPI handler which handles IPI messages from AP.
BRANCH=none
BUG=b:146213943
BUG=b:156223050
TEST=make BOARD=asurada_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: Ie24ff872c94d79a5559248c64c5618659f6d028d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2275711
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When we receive hard reset, we should do Vbus on-off cycle
and should keep cc connection. So I change the event setting
from PD_EVENT_TCPC_RESET to PD_EVENT_RX_HARD_RESET for ITE TCPC.
Stand alone TCPCs also use hard reset event instead of calling
pd_execute_hard_reset(), because waked up pd_task() may have chance
setting to other state.
BRANCH=None
BUG=b:159394180
TEST=On board reef_it8320, and it81202_pdevb:
1.TCPMv1: Rx Hard reset -> done Vbus cycle, and keep cc connection,
When we're SRC and SNK.
2.TCPMv2: Rx Hard reset -> done Vbus cycle, and keep cc connection,
When we're SRC and SNK.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: Ie94757580e8fed4fb33896f9c1e071def49ff03d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2284504
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
When Rx received data reaches FIFO target count, the status of Rx byte
reach interrupt bit is set then start to parse transaction.
BUG=b:160662061
BRANCH=none
TEST=EC can receive more than 128 bytes(up to 256 bytes) from host.
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Change-Id: I3e922265e35f5bc46e794e92adb1bede20f73498
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2284513
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The npcx monitor LFW (little firmware) can be used in two scenarios:
1. For npcx5 which supports the external flash and doesn't support UUT,
it is used by the openocd via servo JTAG to flash the EC image.
2. For npcx7 (and newer chips) which support the internal flash and UUT,
it is used by the UUT via UART to flash the EC image.
For case 1, the DEVALT0.bit7 (NO_F_SPI) should be cleared in order to
program the external flash. In case 2, this bit should be set because
the internal flash is used. Otherwise, the GPIOA0 (F_CS0) will also
toggles while programming the internal flash.
Before this CL, the monitor unconditionally clears this bit when
programming the flash.
In this CL, the monitor decides to set/clear this bit according to
the value of the tag filed in the monitor header.
(Assuming that when UUT is used, the target is always the internal
flash.)
BUG=none
BRANCH=none
TEST=No error for "make buildall"
TEST=Programming the internal flash via UUT, make sure the GPIOA0 doesn't
toggle with scope.
Change-Id: I9f1695351b201767cc5ed32877fb395c1e459bc8
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2272419
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add two additional stack sizes for tasks that need more
stack space.
BRANCH=none
BUG=b:155813111
TEST=make -j buildall
Manual: Changed waddledee's TypeC ports0 and 1 to
ULTRA_STACK_SIZE and TRENTA_STACK_SIZE and
make -j buildall without errors.
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I927d5b978c705f49d1b3a85a09c4020d7fd9ee84
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2280486
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Supports ipi_send() which sends IPI messages to AP.
BRANCH=none
BUG=b:146213943
BUG=b:156223050
TEST=make BOARD=asurada_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: Ia146b29607bc5bf4150b637368b3a99986de677d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2275709
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
|