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* coil: pmu PERIPH_MASTER_MATRIX->PERIPH_MAIN_MATRIXMary Ruthven2021-01-061-1/+1
| | | | | | | | | | BUG=b:175244613 TEST=make buildall -j Change-Id: I3b5d64b1344c9b72ab8c93c68713cce58601b007 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613458 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: pmu PERIPH_I2CS->PERIPH_I2CPMary Ruthven2021-01-062-3/+3
| | | | | | | | | | BUG=b:175244613 TEST=make buildall -j Change-Id: I4bce647f39655249ddbaa16af917fdd8bf0ebd63 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613457 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: pmu PERIPH_SPS->PERIPH_SPPMary Ruthven2021-01-063-5/+5
| | | | | | | | | | BUG=b:175244613 TEST=make buildall -j Change-Id: I8c276d800c6c69fd12bca0b75dc1f8f60a30c096 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613456 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* coil: remove usbc, usb_pd, charge_manager, and tcpmMary Ruthven2021-01-062-371/+0
| | | | | | | | | | | | | This code uses coil terms we're removing, but we don't use it in platform/cr50. Remove the code instead of replacing the terms. BUG=b:175244613 TEST=make buildall -j Change-Id: Ia64e1ff4df941d2fe19e95e84dee8b743616aa88 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2613135 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* gsctool: add ti50 image supportJett Rink2021-01-061-0/+3
| | | | | | | | | | | | | | | | | | Based on the input image, we determine if this is a CR50 image or a Dauntless image. The magic lets us determine which type of image it is. For D2 images, we scan for the RW header instead of using hard coded offsets as this will allow us to change where the RW is located (if RO contracts or expands). BUG=b:172465629 TEST=sent image to D2 from gsctool via CCD TEST=flash new H1 image to volteer using to slot B Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I7554c978a9ba83b423fbaf43c62f9f0d6711d071 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2585926 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* fips: move FIPS power-up test completion to PMU_PWRDN_SCRATCH22Vadim Sukhomlinov2020-08-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Status of completion of power-up tests was in long life register which survives reboots and even firmware upgrades, which is not an intended behavior. Moving status to PWRDN register makes it reset on graceful reboots and firmware upgrades, but avoid running tests on wake from deep sleep. This switch also enables use of multiple bits to indicate status of tests, which makes it more fault tolerant. BUG=b:138577491 TEST=make BOARD=cr50, then deassert DIOM3 to trigger deep sleep FIPS power-on tests shouldn't run on wake. Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: I098940e45afd5b5b9447b2780ff69372a922c03f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2330976 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* g build.mk: fix awk program bugVadim Bendebury2020-07-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | The recent modification of chip/g/build.mk introduced a bug where an awk script error is reported if the board name does not contain an underscore. It went unnoticed because it does not prevent make from reporting success and most boards do not care about the results of running of this awk script. This patch fixes the problem. BUG=none TEST=ran make for cr50 and hslt_d2c, observed proper modification of the manifest, verified that no script errors are reported any more. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I0981411ec7bc17e4473d4b33125f76b75983d974 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2317059 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* signer: modify manifest tag field to include board nameVadim Bendebury2020-07-231-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | Personalization infrastructure expects the image header tag filed to be set to the board name in ASCII. This patch modifies the chip g makefile to paste the board name into the manifest, the signer copies the value into the image header. BUG=b:161498484 TEST=verified that the manifest is updated as expected: $ diff util/signer/ec_RW-manifest-dev.json /tmp/h1.signer.F2Pu6d 33c33 < "tag": "00000000000000000000000000000000000000000000000000000000", --- > "tag": "68736c74206432630000000000000000000000000000000000000000", and observed the personalizer test harness to retrieve the expected board name from the running image. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I9ecf009e21c2ab77b03c9de1ebb176197923e6e1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2310850 Reviewed-by: Andrey Pronin <apronin@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* usb_spi: add support for custom SYS_RST and EC_RST setupMary Ruthven2020-07-221-10/+11
| | | | | | | | | | | | | | | | | | | | | Don't touch the SYS_RST_L or EC_RST_L signals when flashing the AP if flashrom is run with custom_rst=True. BUG=b:154885210 TEST=manual on bob ecrst on flashrom -p raiden_debug_spi:target=EC -r ec.bin ecrst on flashrom -p raiden_debug_spi:target=AP,custom_rst=True -r ap.bin check ecrst is still on flashrom -p raiden_debug_spi:target=AP -r ap.bin Change-Id: Ia1ab8c853c25ced994e053c9e19a18d0d0f1cb45 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2301239 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* [DCRYPTO Hardening] Adding the ecdsa test that can be invoked through console.Baur Krykpayev2020-07-113-10/+212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This test's main goal is to be used against future changes in the dcrypto engine. All it does is comparing signature received from the ecdsa sign function to the golden results. Signed-off-by: mschilder@google.com BUG=b:137659935 TEST=something of a test itself and is run by calling the command through the console connection via host. The test sequence is following: - call the dcrypto_ecdsa_sign function on the known input. - call the dcrypto_ecdsa_verisign on the same input (this function is added in the following CLs in the chain). - compare both results to the golden value. Test passes if both results match to the golden value. To run the test compile the CR50: make -j BOARD=cr50 CRYPTO_TEST=1 in the console run: dcrypto_ecdsa Change-Id: I07437f6a69ba79bdcce8c92976a374733b17d339 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2269337 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Andrey Pronin <apronin@chromium.org>
* system: make sure CR50_DEV images will not update info mapVadim Bendebury2020-07-071-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | Despite all make tricks, sometimes switching between make invocations with CR50_DEV defined and not defined, the code which updates the IFNO1 RW rollback space runs even when CR50_DEV was defined at compile time and the image header rollback space is set to all zeros. This causes complete clearing of the INFO1 RW rollback space, which in turn prevents from running images built without CR50_DEV=1. Let's add a check to see if the currently running image has the entire rollback space in the header erased, and not proceed with the INFO1 space update in this case. BUG=b:160013710 TEST=verified that images built both with CR50_DEV defined and not defined run properly. - removed '#ifndef CR50_DEV' block around lines 610..719 and built and ran the image, observed the "Skipped updating INFO1 RW" map message. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I63a54ba2a82cd250d1e4018768b7a55c406b69c0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2271016 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* trng: adjust TRNG timeout to reduce TRNG resetsVadim Sukhomlinov2020-06-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Time it takes for TRNG to come-up with 32-bit of randomness varies, and once TRNG started to use 1-bit alphabet, it's average increased. We handle this timeout by resetting TRNG and writing record in the flash log. With current setting of EMPTY_COUNT set to 400 it's almost never happens under normal use, and is harmless, but adds unnecessary records in the log under heavy use like TRNG health tests. Adjusting EMPTY_COUNT to higher value reduce probability of TRNG reset when value is just delayed, but TRNG is not stalled yet. BUG=b:138578157 TEST=tpmtest -t0 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: Ic0152da05934a70dd16b3e4178361bfcefbdda26 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2252481 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: William Wesson <wesson@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* cr50: use NIST-compliant configuration of TRNGVadim Sukhomlinov2020-06-171-69/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | According to NIST SP 800-90B only vetted conditioning mechanism should be used for post-processing raw entropy. See SP 800-90B, 3.1.5.1 Using Vetted Conditioning Components. Use of non-vetted algorithms is governed in 3.1.5.2, but assumes conservative coefficient 0.85 for entropy estimate, which increase number of requests to TRNG to get desirable entropy. More details on entropy estimate tests are in associated bug. Entropy measurements using NIST assessment tool didn't report noticeable change in entropy estimate. However, more changes are needed to use DRBG instead of raw TRNG for all purposes. TRNG changes reviewed also at https://crrev.com/c/1926384 BUG=b:138577834 TEST=test/tpm_test/nist_entropy.sh Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: I5a578b90b8b7a77fae6a218eec48e87e7644ab44 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2240519 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* hmac_drbg: define error codes, add parameter checkVadim Sukhomlinov2020-06-152-14/+21
| | | | | | | | | | | | | | | | | | | Added check for output len as defined by NIST for HMAC_DRBG and define error codes instead of constants. Propagate status for hmac_drbg_generate_p256 BUG=b:138578157 TEST=make buildall ; make BOARD=cr50 ; tpmtest.py Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Change-Id: I16a1eac51ca11a6419a86922cfe59c13d9c703a0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2243762 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* dcrypto/hmac: another fix for HMAC SHA256 computeVadim Sukhomlinov2020-06-051-1/+1
| | | | | | | | | | | | | | | | | | | | For long HMAC keys we should also compare length with SHA256 block size rather than size of opad. It updates previous patch. https://crrev.com/c/1850535 introduced change in LITE_HMAC_CTX structure which change size of opad field. HMAC computation was using sizeof(opad) instead of SHA256_BLOCK_SIZE and that caused incorrect values. BUG=b:158094716 TEST=make BOARD=cr50 CRYPTO_TEST=1 ; test/tpm_test/tpmtest.py Change-Id: I9c7d63ad3f1751b09b6968379082e875b3558bef Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2231962 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* dcrypto/hmac: fix HMAC-SHA256 computationVadim Sukhomlinov2020-06-042-14/+19
| | | | | | | | | | | | | | | | | | https://crrev.com/c/1850535 introduced change in LITE_HMAC_CTX structure which change size of opad field. HMAC computation was using sizeof(opad) instead of SHA256_BLOCK_SIZE and that caused incorrect values. BUG=b:158094716 TEST=make BOARD=cr50 CRYPTO_TEST=1 ; test/tpm_test/tpmtest.py or rfc6979 and hmac_drbg in Cr50 console. Change-Id: I58c166381b9f95f02f9f0c26a04a88e552d8057f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2229280 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* remove eraseflashinfo from DBG imagesMary Ruthven2020-06-021-56/+0
| | | | | | | | | | BUG=b:158019009 TEST=make -j BOARD=cr50 CR50_DEV=1 Change-Id: If9554fcf499fb08b301d6f58764e9a4983b6884b Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227075 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* remove CR50_SQAMary Ruthven2020-06-025-66/+8
| | | | | | | | | | | | | | | | | | | | | | | SQA images won't be built anymore. This change removes the SQA support. It deletes all SQA ifdefs and replaces CR50_RELAXED with CR50_DEV. BUG=b:158011401 TEST=manual build regular image and check eraselfashinfo and rollback aren't included. build image with CR50_SQA=1 and check it's no different than the regular image. build DBG image and make sure it still starts open, it has the eraseflashinfo and rollback commands, and it can flash old cr50 images. Change-Id: I5e94c88b1903cfcf0eee0081fc871e55fc8586c7 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227149 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* fizz: remove board from cr50_stabVadim Bendebury2020-06-0256-20712/+0
| | | | | | | | | | | | | | | | Not sure why this board was kept in, probably because fizz was mixed up with fuzz. BUG=none TEST='make buildall -j' succeeds Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I4b08333d12bdfe8001b7e1c2b7c5860aef947a22 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227168 Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* Introduce BOARD_CFG_LONG_INT_AP_BIT in TPM_BOARD_CFG registerNamyoon Woo2020-06-011-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch assigns the bit offset 0 in TPM_BOARD_CFG register to indicate the status of INT_AP_L extension. The bit 1 means INT_AP_L pulse extension is activated, and 0 means it is not. BUG=b:148691139 TEST=tested on atlas and on careena. 1. Checked the default TPM_BOARD_CFG (PWRDN_SCRATCH21) value was zero and the INT_AP_L assertion duration was 4~10 microseconds. > md 0x400000f4 1 // memory dump on GC_PMU_PWRDN_SCRATCH21 400000F4: 0x00000000 2. Attempted to change the board configuration (with a hacked UART command.). The register value was unchanged. > brdcfg 0x01 TPM_BOARD_CFG = 0x00000000 > md 0x400000f4 1 400000F4: 0x00000000 3. Forced to write the board configuration with a hacked UART command. The register value was changed. > brdcfg 0x01 force TPM_BOARD_CFG = 0x80000001 > md 0x400000f4 1 400000F4: 0x80000001 4. Checked the INT_AP_L assertion duration extended to 110 microseconds or longer. 5. After cr50 deep sleep, checked the pulse duration was still extended. - turned AP off. - disconnected Suzy-Qable. - waited three seconds - connected Suzy-Qable, and checked the reset cause was 'hibernate rbox'. > md 0x400000f4 1 400000F4: 0x8000001 6. With 100 usec long INT_AP pulse, checked trunks_cliend regression_test, stress_test and ext_command_test runs good. Checked dmesg and found no TPM errors through all tests. (ap) $ trunks_client --regression_test (ap) $ trunks_client --stress_test (ap) $ trunks_client --ext_command_test 7.checked no character loss during uart_stress_tester. (chroot) $ uart_stress_tester.py -c -t 600 /dev/ttyUSB2 /dev/ttyUSB1 8. the shortest duration of INT_AP_L assertion and deassertion observed in logic analyzer were 110 usec and 152 usec. 9. measured the depthcharge exit timestamp and cr50 flash time with or without INT_AP pulse extended to 100 usec, on atlas and helios: -----------------+-------------------+------------------ | atlas | helios -----------------+-------------------+------------------ boot (sec) | 1.398 -> 1.402 | 1.004 -> 1.011 cr50 flash (sec) | 10.800 -> 14.609 | 16.024 -> 16.466 -----------------+-------------------+------------------ Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I2b9f9defb63cf05f9d91b741ccb4b49c4c6bc8e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202839 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* Introduce TPM_BOARD_CFG registerNamyoon Woo2020-06-011-0/+1
| | | | | | | | | | | | | | | | | | This patch adds the TPM vendor-defined register, TPM_BOARD_CFG, which indicates the board configuration status. This register is attributed as one-time-programmable and the value is maintained across deep sleeps. Cr50 allows a write on this register right after a cr50 reset until it receives a TPM2_PCR_Extend command. BUG=b:148691139 TEST=none Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I89ae5a53c15990ef78812aec5da81a59f04d7d98 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202838 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* Use a long pulse of INT_AP_L for SPSNamyoon Woo2020-05-291-8/+49
| | | | | | | | | | | | | | | | | | | | This patch adds a feature to extend each level of GPIO_INT_AP_L at least for 100 microseconds. The assertion (low GPIO_INT_AP_L) duration might be shorter only if AP asserts a SPS CS before INT_AP_L deassertion, because it means means AP recognized GPIO_INT_AP_L assertion already. This patch increases the flash usage by 280 bytes. BUG=b:148691139 TEST=None Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Ie74b236bc5352e9fc21fe600c12946e50955160a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114430 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* close RO window after useVadim Bendebury2020-05-294-8/+35
| | | | | | | | | | | | | | | | | | | | The code opening the RO windows to make it possible to update or enable the RO images, leaves the window open, allowing subsequent writes into the RO space. It has been acceptable until now, because RO updates are usually followed up by reboots. With introduction of the AP RO hash, there is a need to close the window (specifically, disable write access) when not in use. This patch adds a function for that and uses the new function everywhere where flash_open_ro_window() is called. BUG=b:153764696 TEST=verified successful Cr50 RO and AP RO hash updates. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Ia595e5c7ce0beb1a67ef3513117984d18655a60c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2204973 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Plug in the AP RO verification implementationVadim Bendebury2020-05-292-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds plumbing necessary to invoke the AP RO verification function in response to the operator entering the 'magic sequence' of holding the power button pressed and pressing/releasing the refresh button three times within five seconds. The code used during the 'Open box RMA' verification process is used, with the physical presence confirmation phase bypassed. This patch also makes sure that attempts to use CCD to program AP or EC flash while AP RO verification is in progress would fail. BUG=b:153764696, b:154966209 TEST=with the next patch applied, generated AP integrity verification data using the ap_ro_hash.py script and then ran the verification procedure, observing the 'hash match' message on the Cr50 console. Also verified that the Open Box RMA procedure still succeeds. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Ic101fb892554ebb05f9ebe6d1546bfb439f74043 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171399 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Add AP RO integrity check implementation.Vadim Bendebury2020-05-222-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds code which accepts the vendor command communicating the list of the AP firmware sections to verify and the expected cumulative sha256 sum value of the sections. The vendor command payload is checked for sanity: each range offset is not expected to exceed 32M bytes (the largest possible SPI flash size) and each size is not expected to exceed 4M bytes. If any inconsistencies are found in the payload, or the flash integrity space is already programmed, an error is returned to the AP. It the command validity check succeeds, the payload of the vendor command is prepended by a header including the number of the flash regions to check and a 4 byte checksum of the stored information. This combined information is stored in the dedicated H1 flash space, specifically the RO_B region, at offset of 0x3000, 2K bytes page below the region used for the flash log. The valid RO range in upgrade_fw.c:set_valid_sections() is modified to prevent erasing of the AP RO hash value during Cr50 RO updates. The new file also introduces a function used to verify the AP flash when requested. The returned value indicates one of three conditions: - valid verification information not found - AP flash integrity verification failed - AP flash integrity verification succeeded A new console command allows to examine the contents of the space where the list of ranges and the sum are stored. CR50_DEV builds also allow to erase the page. BUG=b:153764696 TEST=with the rest of the patches applied verified successful execution of the AP RO verification sequence. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I1894ef897a86e9d60b9f5bcff3a680f632239e1b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171398 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* board_id: refactor to expose function checking INFO1 board ID spaceVadim Bendebury2020-05-202-0/+27
| | | | | | | | | | | | | This patch makes it possible to check if the INFO1 Board ID space is programmed or not. BUG=b:153764696 TEST='make buildall -j' Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Ic771956a08e276c2e1a426729a8ecdae3f86a04f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2204974 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* usb_spi: refactor to allow use in different contextsstabilize-quickfix-13099.93.B-cr50_stabstabilize-13099.94.B-cr50_stabstabilize-13099.90.B-cr50_stabstabilize-13099.85.B-cr50_stabstabilize-13099.73.B-cr50_stabstabilize-13099.72.B-cr50_stabstabilize-13099.70.B-cr50_stabstabilize-13099.118.B-cr50_stabstabilize-13099.110.B-cr50_stabstabilize-13099.101.B-cr50_stabrelease-R84-13099.B-cr50_stabVadim Bendebury2020-05-142-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code which allows to read a section of AP or EC flash and calculate the section's SHA256 sum does not allow calculating the sum over multiple non-adjacent flash areas. This patch changes the implementation to allow calculations over more than one region. Initialization, calculation and reporting of the result become three separate API entries. The loop counting the number of the read flash chunks, is being simplified, a watchdog kick added to the brief loop interruptions, as it turns out that sleeping alone is not enough to prevent watchdog expiration when calculating hash over large SPI flash ranges. Also simplified prototypes for usb_spi_board_enable() and usb_spi_board_disable(). BUG=b:153764696 TEST=created an RO descriptor for the Atlas DUT and verified that 'gsctool -O' succeeds. Cq-Depend: chrome-internal:2939596 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Iec7b8634c7c80ebc7600c5b708879eb322bc7fec Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2163569 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* crypto_api: use const voidVadim Bendebury2020-05-144-12/+11
| | | | | | | | | | | | | | | | | | | This is a minor API clean up, it is not entirely clear why const void pointers were not used originally, but using this type for input data (and void pointer for output) makes interfacing with the library much easier. Also modified cases where the first parameter of DCRYPTO_SHA1_hash() was typecasted unnecessarily. BUG=none TEST=make buildall succeeds, Cr50 image supports booting a Chrome OS device just fine. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Ic8a670aa7b26598ea323182845c184b7f1d715a1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2163568 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* idle: reduce set of idle command actionsMary Ruthven2020-05-081-9/+7
| | | | | | | | | | | | | Remove 'deep sleep' and 'invalid' idle actions from the idle console command. BUG=b:156032428 TEST='idle s' and 'idle w' work when the console is open. Change-Id: I9da2fa0d679ef89ecb2eaaad82541bd3e9e16140 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2189616 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* sps: do not generate AP_INT_L pulse until controller is readyVadim Bendebury2020-05-041-19/+32
| | | | | | | | | | | | | | | | | | | The recent interrupt pulse extension brought to fore an old bug where the AP_INT_L pulse is generated by the SPS driver before the controller is actually ready to accept the next SPI frame. This patch rearranges the code to make sure that the pulse is generated after all controller clean up. BUG=b:154458891 TEST=verified that Atlas device is still booting fine. Will test it on other devices which seemed to be triggering the bug. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I480760b4afea24295f96abde2fc75c414017c27f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171452 Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* prevent EC UART TX channel lockup caused by EFS introductionNamyoon Woo2020-04-041-22/+31
| | | | | | | | | | | | | | | | | | | If UART-EC TX is disabled, the USB input data used to be ignored in UART-EC TX interrupt handler, but it neglected to call uartn_tx_stop(), which was a defect. In this patch, those data shall be ignored when they arrive from USB (in USB RX stream handler), which is earlier than UART-EC TX interrupt, and uartn_tx_start() won't be called. BUG=b:153198965 TEST=Repeated to lock and open CCD, and checked EC-UART is RO or RW. Checked EC-EFS2 working, and uart_stress_tester as well. Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I1c3c2c5a7626850f6389616bbe1f69188d5eca6d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2135140 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* Prepare for transitioning to packet mode consoleVadim Bendebury2020-03-311-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A very few changes are needed to support the packet mode: - provide functions to report how much room is left in USB/UART transmit buffers; - compile out cprintf/cprints/cputs just in case to be able to catch cases where util_precompile.py fails to convert them for whatever reason; - do not add CR to every LF, this messes up packet transmissions, and the terminal is doing the right thing anyways - there is a problem with the USB channel in packet mode: the device reboots as soon as an attempt to send something to the host is undertaken. The problem can be rectified by disabling the deferred function path in the Cr50 console USB channel. A bug was open to track it down, but in packet mode using deferred function in this path is less critical, as the amount of sent data always is at least as much as the packet header size BUG=b:149964350, b:152116489 TEST=with the rest of the patches applied packet mode console works fine. When packet mode is disabled the conventional mode console works fine. Change-Id: Ib010cede36adc87cf80f49e5d76ec9e274d9e608 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114238 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: add CONFIG_USB_CONSOLE_DEFAULT_DISABLEDMarius Schilder2020-03-201-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | To avoid some sort of race in private-cr52 endpoint initialization, which results in a reboot loop. Calling usb_console_enable() in HOOK_LAST instead appears stable, at cost of missing some early console output. While at it, reduce some SRAM usage and improve legibility by moving to bool from int. Strictly opt-in; behavior unchanged for existing code. BUG=chromium:1063240 BRANCH=cr50 TEST=make buildall; cr52 build w/ usb_console now enumerates w/o resets. Signed-off-by: mschilder@google.com Change-Id: I352edb4c045df401cb99573da5765b88deb45d0d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2111450 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Commit-Queue: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Auto-Submit: Marius Schilder <mschilder@chromium.org>
* remove CONFIG_USB_HID_KEYBOARD and CONFIG_USB_UPDATENamyoon Woo2020-03-132-160/+0
| | | | | | | | | | | | | | | | | | | | | | This path removes CONFIG_USB_HID_KEYBOARD support and CONFIG_USB_UPDATE support because they are not used in any cr5X board configuration. Ths patch also removes some subsidiary configs as upload hook script guides. > CONFIG_USB_PAIRING > CONFIG_TOUCHPAD_VIRTUAL_OFF > CONFIG_USB_CONSOLE_READ BUG=none BRANCH=cr50 TEST=make buildall Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: Iafa553fdf58772744b1d9a5c7f5460f42264f468 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2103045 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* introducing an unittest of EC-EFSNamyoon Woo2020-03-115-19/+136
| | | | | | | | | | | | | | | This patch adds a test case for EC-EFS functions. BUG=b:150650877 BRANCH=cr50 TEST=make run-ec_comm make runhosttests make buildall -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: I90cdc3aa73cf8946da4cf094de5ca0adfaaa0a7c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2096338 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* EC-CR50 communicationNamyoon Woo2020-02-222-10/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports EC-CR50 communication. EC activates EC-CR50 communication by setting high DIOB3, and send a command packet to CR50 through UART_EC_TX_CR50_RX. Cr50 processes the packet, and sends a response packet back to EC. EC deactivates EC-CR50 communication by putting low DIOB3. This patch supports two kinds of EC-CR50 commands: - CR50_COMM_CMD_SET_BOOT_MODE - CR50_COMM_CMD_VERIFY_HASH Cr50 stores some of EC-EFS context in a powerdown register before deep sleep and restores it after wakeup. This patch increases flash usage by 1456 bytes. BUG=b:119329144 BRANCH=cr50 TEST=Checked "ec_comm" console command on Octopus and reworked Helios. Checked uart_stress_tester.py running without character loss. Change-Id: I23e90b9f3e860a3d198dcee718d7d11080d06e40 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1961145 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* restructure EC-EFS moduleNamyoon Woo2020-02-201-0/+3
| | | | | | | | | | | | | | | - add ec_efs, which tracks the system boot mode. - add ec_comm.h header file for EC-EFS related functions. - revised vboot.h header file. BUG=b:141143112 BRANCH=cr50 TEST=none Change-Id: Iec1bf466b832bac5ad6be8a52304c1d699a38fb2 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055363 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* control EC USB-UART bridgeNamyoon Woo2020-02-192-7/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL separates the control on USB-UART bridge of EC device from EC UART control. USB-UART bridge shall be enabled if CCD connection is detected and the CCD capability is enabled. Otherwise, EC USB-UART shall be disabled. By doing so, CCD capability can be observed even when EC-CR50 communication enables EC UART. This patch increases the flash usage by 204 bytes BUG=b:148247228 BRANCH=cr50, cr50_mp TEST=ran firmware_Cr50CCDServoCap on Helios. > ccd State: Locked Password: none Flags: 0x000001 Capabilities: 0000000000000000 ... > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC I2C USBEC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTAP+TX UARTEC USBEC CCD ports blocked: (none) > ccd State: Opened Password: none Flags: 0x800001 Capabilities: 5555454115000000 ... > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC I2C USBEC+TX CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX CCD ports blocked: (none) Change-Id: I6bb560a05831105ff68a9e13e4b28b002ed98096 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018061 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* use gpio_set_wakepin() to enable or disable wake pinsNamyoon Woo2020-02-131-4/+2
| | | | | | | | | | | | | | | | | This uses gpio_set_wakepin() to setup the wake pins instead of writing to the PINMUX EXITEN registers directly. This patch reduces the flash usage by 248 bytes. BUG=b:35587259 BRANCH=cr50 TEST=checked pinmux configuration hasn't changed on coral. Checked firmware_Cr50DeviceState running good on coral. Change-Id: Ic4ef1751e34b85ea2719f257ebd9b7ad52355eec Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2047923 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* make DIOB3 interruptible and wakable for EC-EFS2Namyoon Woo2020-02-081-0/+16
| | | | | | | | | | | | | | | | | | | | | If the board supports EC-CR50 communication, Cr50 enables both rising/falling-edge triggered interrupt on DIOB3 pin and makes it wakable as well.Cr50 connects GPIO_AP_FLASH_SELECT to DIOB4. If the board does not support EC-CR50 communication, Cr50 connects GPIO_AP_FLASH_SELECT to DIOB3. If EC puts high on DIOB3 to activate EC-CR50 communication, CR50 enables UART_EC RX and TX. BUG=chromium:1035706 BRANCH=cr50 TEST=none Change-Id: I1221a1a19219274622ab710568ce7c66ab2f1da7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1989581 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: add gpio_set_wakepin() to configure wake pinsMary Ruthven2020-02-071-19/+80
| | | | | | | | | | | | | | | | | | | | | | | Cr50 needs a cleaner way to enable and disable wakepins. This change adds gpio_set_wakepin() to enable the wake pin or disable. The gpio_set_flags() or gpio_set_flags_by_mask() remain unaffecting wake-pin configuration. This patch increases the flash usage by 16 bytes. BUG=b:35587259 BRANCH=cr50 TEST=verify pinmux has the same output before and after the change on octopus. Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/533674 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org> Change-Id: I0387c673aedc046ce9cf6b5f0d683c40f3079281 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044355
* revise the uart tx connect/disconnect functionsstabilize-quickfix-12871.27.B-cr50_stabstabilize-12871.91.B-cr50_stabstabilize-12871.65.B-cr50_stabstabilize-12871.57.B-cr50_stabstabilize-12871.253.B-cr50_stabstabilize-12871.24.B-cr50_stabstabilize-12871.103.B-cr50_stabstabilize-12871.102.B-cr50_stabstabilize-12859.B-cr50_stabrelease-R81-12871.B-cr50_stabNamyoon Woo2020-01-221-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reduces redundant condition checking in connecting or disconnecting UART TX. BUG=none BRANCH=cr50 TEST=manually checked ccd state with/without servo connection and/or ccd connection. [AFTER] > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: disconnected Servo: connected CCD EXT: disabled State flags: CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI CCD ports blocked: (none) > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTAP+TX I2C SPI CCD ports blocked: EC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: I2C SPI CCD ports blocked: AP EC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: ignored CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI CCD ports blocked: IGNORE_SERVO WARNING: enabling UART while servo is connected may damage hardware Change-Id: Icea2978b15e15bbf7cea8e48fd2bf4fdecc78f46 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013823 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* extend INT_AP_L pulseNamyoon Woo2020-01-162-0/+19
| | | | | | | | | | | | | | | | | This patch extends INT_AP_L pulses to be at least 6.5 micro seconds. It is a tentative solution to to meet Intel TGL/JSL requirement on interrupt duration. BUG=b:130515803 BRANCH=cr50 TEST=checked INT_AP_L pulse length ranges extended to 6.5 ~ 11 usec with logic analyzer on Hatch. Checked dmesg and coreboot log has no TPM errors. Change-Id: Iea8d0a779fff7cbda0c8647f3c1de719c3c3d7e0 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002958 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* drop chip factory mode supportVadim Bendebury2020-01-131-3/+0
| | | | | | | | | | | | | | | | There is no need to keep the code supporting chip factory mode in Chrome OS production branches, this code is never used outside of the chip factory environment. BRANCH=cr50, cr50-mp BUG=none TEST=built an image, verified that an Atlas device boots up into the previously created Chrome OS account. Change-Id: If72635b014d15ef6e97fbc4fd5b54b61ec23299a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994369 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* drop unnecessary boards, chips and cts testsVadim Bendebury2020-01-07322-92506/+0
| | | | | | | | | | | | | | | | | | | | The only board which would be built from this branch is Cr50. bds, fizz and host boards are necessary for proper make infrastructure operation and tests. lm4 and npcx are chips used by the bds and fizz boards, so they are also kept around. BRANCH=cr50, cr50-mp BUG=b:145912698 TEST='make buildall -j' succeeds Change-Id: I937b2b8642c1fe91578fc9615438ae22c165b20f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986942 Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* SQA images should allow support rollback to 0.0.22Vadim Bendebury2019-12-192-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rolling back to 0.0.22 requires erasing the INFO1 rollback protection space, as current RW level is at two, and 0.0.22 is at one. The only way to erase INFO1 is to run a node locked prod signed 0.3.22 image. But 0.3.22 will destroy board ID along with the rollback spaces AND it is not capable of rollback, so to roll back to a lower than 0.3.22 version one still needs to run the SQA image. 0.3.22 will not allow to restore the Board ID either. Another problem is that SQA image would update the rollback INFO1 space, thus again preventing 0.0.22 from running. This patch alleviates the situation by allowing the SQA images to write Board ID fields and preventing SQA images from updating rollback space in INFO1. BRANCH=cr50 BUG=b:146522336 TEST=with the new image was able to downgrade a device from 0.4.24 to 0.0.22 Change-Id: I8babf15ae32036dc612ae9c808c773a2b3355762 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1975092 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: change OWNERS to cr50 team membersMary Ruthven2019-12-101-1/+0
| | | | | | | | | | | | | | Change the OWNERS to cr50 team members and remove OWNERS files from all subdirectories. BUG=none BRANCH=none TEST=none Change-Id: I5ddff7c433a55b6724d92c026e9e64e82e1492ad Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957850 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chip/host: Avoid concurrent recipes of libcryptoc.astabilize-12748.B-cr50_stabYicheng Li2019-12-063-28/+3
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DCRYPTO compiles and links thirdparty/libcryptoc for cr50. CONFIG_LIBCRYPTOC does similar things for other boards that configures it, including host. This resulted in cr50_fuzz having concurrent recipes for libcryptoc, as it has both configs. This change separates CONFIG_DCRYPTO from the responsibility of building and linking libcryptoc. Libcryptoc is now solely handles by CONFIG_LIBCRYPTOC. BRANCH=none BUG=b:144811298 TEST=make -j buildall > /dev/null Observed no more "warning: overriding recipe for target 'build/host/cr50_fuzz/cryptoc/libcryptoc.a' " Change-Id: I2186cbead773629456da254df5f82b96e9646fc2 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949554 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit a018043265ecb3466863ff9020ab25d552105c61) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956404 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* g: update rollback info map for both RO and RW sectionsVadim Bendebury2019-12-061-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both RO and RW sections have their respective rollback spaces in INFO1, but until now Cr50 code did not honor the RO binaries' headers rollback maps and did not update the appropriate iNFO1 space. With this patch both RO and RW info maps are updated to the lowest level of the two images found in the flash when invoked during board_init() or to match the currently active RO/RW when invoked through vendor command indicating successful OS startup. BRANCH=cr50, cr50-mp BUG=b:136284186 TEST=tried the new image on a chip with freshly erased INFO1 space: first running a DBG image, which does not touch INFO1 maps: > vers ... RO_A: * 0.0.11/bc74f7dc RO_B: 0.0.11/4d655eab RW_A: * 0.4.24/DBG/cr50_v2.0.2744-d79516a9d RW_B: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d .. > sysinfo ... Rollback: 0/1/1 0/128/128 ... Then running an image with debug extensions disabled: > vers ... RO_A: * 0.0.11/bc74f7dc RO_B: 0.0.11/4d655eab RW_A: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d RW_B: * 0.4.24/cr50_v2.0.2744-d79516a9d ... > sysinfo ... Rollback: 1/1/1 2/128/2 ... Change-Id: I259a3f46c03199633ca85389872449d667f172fb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949548 Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit 94cfd7cee548047d8e0f5dee2995c4c03fba665d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954342
* g: display both RO and RW info map statusVadim Bendebury2019-12-061-25/+36
| | | | | | | | | | | | | | | | | | | | | | | Cr50 firmware is required to update the rollback prevention map in INFO1 for both RO and RW images. This patch adds code to display the state of the RO map and both RO_A and RO_B headers in addition to previously reported RW information. BRANCH=cr50, cr50-mp BUG=b:136284186 TEST=loaded the new image and observed reported rollback state: > sysinfo ... Rollback: 0/1/1 0/128/128 ... Change-Id: I32206545b6a59a5693e4274e62fcf0627780f61f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949546 Reviewed-by: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit 565c54c270bd93ee30e8f8560d3d1691d128e762) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954341
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