summaryrefslogtreecommitdiff
path: root/chip
Commit message (Collapse)AuthorAgeFilesLines
* stm32l: use USART1 as consoleVincent Palatin2012-02-081-1/+1
| | | | | | | | | | | | | The Daisy board will have the EC UART on the debug connector wired to USART1 (PA9/PA10 pins) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=Run Discovery board with mini-servo attached to PA9/PA10 and see the traces. Change-Id: I97c59ba388fddb150ff6c76ec3317deedb567546
* Merge "Initial bq24725 charger driver import"chrome-bot2012-02-072-97/+0
|\
| * Initial bq24725 charger driver importRong Chang2012-02-072-97/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Battery charging state machine contains many file changes. This is the 1st part of the break down. Refactor original test code into board dummy driver. Normalize charger API. And import link's charger IC driver. Signed-off-by: Rong Chang <rongchang@google.com> BUG=chrome-os-partner:7855 TEST=build without warning and error BOARD=bds make BOARD=link make BOARD=discovery make Change-Id: I34b6e9862a45331378916bc77653d4adb22ca548
* | More complete x86 power moduleRandall Spangler2012-02-071-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Supports turning system on and off via power button. Also added 'powerbtn' command, which sends a power button press of the specified duration, and deprecated the 'x86power s0' command, since pressing the power button is a more correct way of powering on/off the system. Note that current coreboot doesn't seem to boot reliably; when it fails, the x86 asks for S5 and then S0 a second later. It boots about every 3rd try. No indication this is due to the EC; the EC just was ignoring these requests until this CL. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7851 TEST=reboot, 'powerbtn', system should power on 'powerbtn', system should power off 'powerbtn 5000', system should power off regardless of previous state press power button, system should power on press power button again, system should power off hold power button 8 sec, system should power off regardless of previous state Change-Id: I89f419553289b20c78a57bc8cb1699932b095aa1
* | Merge "Fix power button being held down for 8 sec"Randall Spangler2012-02-071-14/+11
|\ \
| * | Fix power button being held down for 8 secRandall Spangler2012-02-071-14/+11
| |/ | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7932 TEST=hold down power button >8 sec; PCH_PWRBTNn should stay low Change-Id: If3168984982343735f0c31fb5951374808eb1caf
* | Handle up/down arrow keys for UART console.Vic Yang2012-02-071-0/+4
|/ | | | | | | | | | | | | | | | | | | | | | Record commands used previously and use up/down arrow key to navigate in the command history. Also removed the command '.' of repeating last command as we can use up arrow key now. Also changed the behaviour of uart_write_char() to be blocking on transmit FIFO full, so that we do not lose echoed character and do not need to flush. BUG=chrome-os-partner:7815 TEST=Type 'help' and enter. Then type 'aaaa' and up arrow key, should show 'help', and pressing enter prints help. Type 'hellp' and enter. Then type 'aaaaaa' and up arrow key, should show 'hellp'. Should be able to use left/right arrow key and backspace to correct it to 'help', and pressing enter prints help. Type 'help' and enter. Then type 'aaa', up arrow key, and down arrow key. Should show 'aaa'. Change-Id: I65c615d61bf63acb31bea329aa91a3202d4db0ad
* Add UART1 receive support (UART to x86 console)Randall Spangler2012-02-062-18/+22
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7488 TEST=type things into the x86 console UART; should appear on the u-boot prompt Change-Id: I75fd225842c03d11d79280fb7453ad37695279e3
* Refactor temperature sensor code and add support of Link I2C temp sensor.Vic Yang2012-02-044-1/+123
| | | | | | | | | | | | Refactor board/chip-specific code into corresponding directories. Add support of the four I2C temp sensor in Link. Use table lookup to handle different types of temperature sensors. BUG=chrome-os-partner:7527 TEST=Correctly read EC internal temperature on bds. Compile for link succeeded. Change-Id: I694cfa54e1545798d877fafdf18c5585ab5f03e2
* Merge "Use udelay for more stable manual IRQ firing."chrome-bot2012-02-031-7/+17
|\
| * Use udelay for more stable manual IRQ firing.Louis Yung-Chieh Lo2012-02-031-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Original code tests SND bit, but it is not reliable to indicate the SERIRQ frame has been sent out because the EC always clears it immediately. Unfortunately the SIRQRIS is always asserted in continuous mode so that we cannot rely on it. So, the udelay(4us) method is the best way we can use now. Note: the quiet mode? Forget it. My EC never sends out further frames after the first has been sent. BUG=none TEST=on bds board. Change-Id: Ica79b463f3dbe7435fe75f3db4cef00ad7ad5ec0
* | Split out GPIO console commandsVincent Palatin2012-02-031-116/+0
|/ | | | | | | | | | | | | The GPIO console commands are common to all platform, let's push them in the common code. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=link && make BOARD=bds && make BOARD=discovery on BDS console, try gpioget command. Change-Id: I26e6d26b8d661e78b80d5d5f665e81f4daef0c11
* stm32l: basic GPIO supportVincent Palatin2012-02-034-5/+90
| | | | | | | | | | | | No interrupt support yet. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on Discovery EC console, using "gpioget" and "gpioset" commands check we can switch the LED and read the button state. Change-Id: I01294643d3df070a535dab5a6be02c296487fca5
* correct typo for STM32L GPIO bit set/reset register (BSSR --> BSRR))David Hendricks2012-02-021-1/+1
| | | | | | | | | Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=none TEST=none Change-Id: I2f452e4f842ac3b67157f94c5e533b53d0d8baec
* stm32l: update clock settingsVincent Palatin2012-02-022-7/+27
| | | | | | | | | | | | | | | | Add a final wait to ensure the clock is ready before returning. Setup the Flash according to the manual recommendations. The low-speed oscillator and RTC are now done in the system module with other RTC inits. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run the EC firmware on the Discovery and manually exercise various path through the console. Change-Id: I4e6149b6fd55c8fc72dbdf6bfc4a10665e0246bd
* stm32l: implement reset cause and scratchpadVincent Palatin2012-02-021-3/+51
| | | | | | | | | | | | | | Allow to get proper reset reason. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=On the discovery board, try the reset button, the "reboot" command and a blocking wait, and see the proper reset reason displayed. Initialize the scratchpad register with "setscratchpad" command and check we can read it back after reboot. Change-Id: I1fe1eec4987f7c9816454de4fd3b4addda4ad05a
* stm32l: add watchdog supportVincent Palatin2012-02-023-0/+85
| | | | | | | | | | | | | | | | | | Use the Independant WatchDog. The Window WatchDog would provide a nice early warning interrupt before actually rebooting but the max period (128 ms) is probably too short for our purpose. The full GPIO support and the reboot cause detection will be implemented in later steps. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on Discovery board, do blocking waits of 500ms and 1500ms, and check the latter reboots the platform and the former does not. Change-Id: I26e4d8b26b733269b7811cc3b3a09daf98ea364a
* Merge "Fix the missing IRQ problem."Louis Yung-Chieh Lo2012-02-021-1/+39
|\
| * Fix the missing IRQ problem.Louis Yung-Chieh Lo2012-02-021-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem comes from the different assumption of interrupt mode in EC and the PCH. The PCH assumes IRQ1 is edge-triggered and triggered at a rising edge. However, the auto-IRQ functino of EC is level-triggered and uses low-active to assert an IRQ. This makes the deadlock so that the kernel never gets an interrupt until a byte is manually pulled from host. So, the solution is manually firing an IRQ_1 to host after EC puts a byte to port 0x60. Note that the auto IRQ needs to be disabled in order to avoid the interference with manual IRQ generation. This CL also moves chip specific code to lm4/lpc.c and handle some minor keyboard commands. BUG=none TEST=on hacked baord. Change-Id: Ib57f5a4d749cb019e4c3c00da110054c4f335c7b
* | Fix a bug that ADC input is not correctly configured.Vic Yang2012-02-022-5/+38
|/ | | | | | | | | | The ADC input pin was always configured as BDS. Modified it to configure the correct pin. BUG=none TEST=On Link, "rw 0x4002451C" show 0xff instead of 0xf7. Change-Id: I1efd5cd59ad65f55cd673529afa6153add63ecac
* Merge "Refactor ADC code and add Link charger current ADC support"chrome-bot2012-02-013-75/+109
|\
| * Refactor ADC code and add Link charger current ADC supportVic Yang2012-02-023-75/+109
| | | | | | | | | | | | | | | | | | | | | | Refactor ADC code and move board/chip-specific part to corresponding directories. Implement function and console command to read Link charger current. BUG=chrome-os-partner:7527 TEST=Read EC temperature and POT input on BDS. Change-Id: I7fafd310ea49d9b2781f10c3453f5488da29a08a
* | stm32l: add timer supportVincent Palatin2012-02-011-3/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the STM32L doesn't have any 32-bit timer, we use 2 chained 16-bit counters to emulate a 32-bit one : * TIM2 is the MSB half-word (Slave timer) * TIM3 is the LSB half-word (Master time) Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run timer_calib and timer_dos on the Discovery board, and check waitms and gettime console functions against wall clock. Change-Id: I8917207384d967fd87321797856e3d58b237f837
* | stm32l: ensure we transmit as soon as characters are availableVincent Palatin2012-02-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Force starting the transmission immediatly when ordered by the UART buffering layer. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC console on Discovery and measure the timestamp of each characters on the serial port. Change-Id: I036a3fa0a60baa27de4ba0ceb386841a429535ac
* | stm32l: avoid spurious USART interruptsVincent Palatin2012-02-011-3/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The TX empty interrupt needs an actual write to DR to be cleared. So, we de-activate it before filling the TX buffer to ensure the interrupt won't fire after the last write. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC console along with a lower priority task on Discovery board, and check the task is scheduled as expected. Change-Id: I56c33c6dd7ccfd238fd9d5910780d12945467010
* | stm32l: add UART driverVincent Palatin2012-01-312-5/+61
|/ | | | | | | | | | | | simple UART driver to get the serial console on the USART3. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run on Discovery board and check we get the first message on the UART and the console is echoing the characters. Change-Id: Id85999a5ddbd75804e9317a1b8c2fd4afb89eb38
* Change COMx port to COM1Randall Spangler2012-01-301-3/+3
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7804 TEST=boot and check UART2 output; should have coreboot debug output Change-Id: Ia0d16498180bb7b7d466d10268a959097e385fac
* stm32l: initialize clocksVincent Palatin2012-01-301-0/+40
| | | | | | | | | | | | | Run from internal clock at 16Mhz, but enable PLL to get a better precision. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run on discovery board and check software is still alive after clock initialization. Change-Id: I8425482825015adf96c30e67a9320d0df2f4f2b7
* Add register definitions for STM32L SoCVincent Palatin2012-01-301-0/+237
| | | | | | | | | | | | Define IRQs and register addresses for basic peripherals to do STM32L bringup. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=mostly untested, there should be typos over there... Change-Id: Ib6d90436e25be74f724112619cdae7acccfaf085
* Add workaround for fan controller to handle speeds more than 7000 rpmRandall Spangler2012-01-271-5/+17
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7718 TEST=manual // enable fan gpioset enable_vs 1 // set fan speed to 7000 fanset 7000 faninfo // should report duty cycle about 65%, fan speed about 7000 rpm, status = 2 fanset 4000 faninfo // should report duty cycle about 25%, fan speed about 4000 rpm, status = 2 fanset -1 // should report duty cycle 100%, fan speed about 8800 rpm, status = 3 Change-Id: Ib7d7df14ad240811e6e79bc1fc4ecf0e6841c334
* Fix setting GPIO outputs and keyboard scanningRandall Spangler2012-01-272-34/+19
| | | | | | | | | | | | | | Keyboard scanning was not properly configuring GPIOs on link. Among the problems, it was setting GPIO level then direction, when it needs to set direction first. Also fixed this in gpio pre-init. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7761 TEST=1) press keys on keyboard; see keyboard state change on console 2) 'gpioget PCH_PWRBTNn' should report 1 after boot, not 0 Change-Id: I54010aa6eef1de4822574f964de369b459ee6d0f
* add the skeleton for STM32L chip and discovery boardVincent Palatin2012-01-266-0/+238
| | | | | | | | | | | | All hardware drivers code is stubbed excepted a few configuration settings. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=discovery Change-Id: Ic9e88a0f51ab626679c8aeb6192272e66a3f79b8
* Merge "Split reset cause and image copy code."chrome-bot2012-01-261-198/+5
|\
| * Split reset cause and image copy code.Vincent Palatin2012-01-261-198/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 3rd series 2/2 All the RO/A/B firmware copy code could be generic to all our platforms. The console commands are a 'standard' API. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on BDS EC console, check the reset cause with the 'sysinfo' command. Change-Id: Ieeb84571085d88b5747a09da4c33d3852bb0da96
* | Merge "Split UART code"chrome-bot2012-01-261-405/+52
|\ \ | |/
| * Split UART codeVincent Palatin2012-01-261-405/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 3rd series 1/2 Most of the code is handling the buffering and the printf, thus put it in an hardware independant location and only implement the UART dependant portions in the chip driver. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run on BDS and stress the console. Change-Id: I9376f2fa1dad341eac808e1756dbeff32900bd51
* | Add i2cread commandRandall Spangler2012-01-261-2/+59
|/ | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=from console, do 'charger' then 'i2cread 1 0x12 2'; should print 0x00 0x10 Change-Id: I70947e2c5ddc267afd6752add838ee5280f1fbfd
* Fix missing GPIO interruptsRandall Spangler2012-01-261-3/+3
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=push and release power button; should see debug messages Change-Id: I4a08b56247baa85555514623db7a04ab4638ca0e
* Increase link image size to 40KBRandall Spangler2012-01-261-1/+1
| | | | | | | | | | | with x86 power module enabled, it no longer fits in 32KB. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=make Change-Id: I38c9054efd8a072cc5800cc87936e53e2df00e58
* Ensure the panic UART is set to the right UARTVincent Palatin2012-01-261-0/+6
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 2nd series 4/4 Add a build time assertion which checks whether the UART used in the C uart code is the same one as the one defined for assembly panic code. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=build for BDS with both good and bad address in CONFIG_UART_ADDRESS Change-Id: I28dd6089bc938f06be0654d7bed75d7d698fafe0
* Make more features optionalVincent Palatin2012-01-262-3/+13
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 2nd series 3/4 Some modules won't be used on other designs, make them optional. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run the EC firmware on BDS and check that the commands from the optional features are still available and working. Change-Id: I979864ed94dc4da90c1010bd2e4589d84bc2d046
* Move SoC-independant headers to another directoryVincent Palatin2012-01-262-86/+0
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 2nd series 1/4 The atomic operations are SoC independant since they are only using LDREX/STREX instructions which are just core specific ARMv7-M). The watchdog header defines the API which is common to all platforms. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and check a few console commands
* NVIC registers are not SoC specificVincent Palatin2012-01-252-7/+2
| | | | | | | | | | | | | Preparatory work to introduce a second SoC : 5/5 All Cortex-M3/4 have the same NVIC registers at the same address. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and check a few console commands Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
* Add configuration parameters for the panic UART codeVincent Palatin2012-01-251-0/+6
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 4/5 Allow to use the common code for most SoC. Also simplify the UART code, we don't need speed on the panic path. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=trigger a panic and check the UART output on BDS Change-Id: I11f7bbc571ab9efbc21fb7b805bf4e271b192c3b
* Move OS files to a CPU specific directoryVincent Palatin2012-01-257-1218/+3
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 3/5 We split the drivers files which contain SoC specific drivers from the OS files which only depend the actual CPU core. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and test a few commands on the console. Change-Id: I598f8b23e074da9bd6b0e2ce6689c1075fe854f0
* Split the timer code between OS code and hardware dependant code.Vincent Palatin2012-01-253-80/+104
| | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 2/5 The hwtimer.* files implement the driver for the SoC timer block. The timer.* files provides the OS level clock/timer functions. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=on BDS, check 'waitms' and 'gettime' on the EC console. Change-Id: Icbc58d9be59ee268e2d5a94f8b20de0cabcdc91d
* Go back to SoC independant IRQ vectors declarationVincent Palatin2012-01-252-113/+264
| | | | | | | | | | | | | | | | | Preparatory work to introduce a second SoC : 1/5 Instead of putting hardcoded IRQ SoC name in the vector table, upgrade the DECLARE_IRQ macro to expand its argument. Also add a parameter to set the size of the NVIC table to save flash memory. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC on BDS and see timer IRQs firing. Change-Id: I44fefdabdd37d756492a71f24554979c72c1b50f
* Indicate which signals in GPIOGET have changed since the last callRandall Spangler2012-01-251-4/+29
| | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=at EC console, gpioget twice, then toggle an output using gpioset, then gpioget again May see *'s the first time. Second time, should see no *'s. Third time, should see a * only the toggled output (and any input signals which respond to it). Change-Id: Ibc1870839201008592b7982049cc352c1779a0e3
* Merge "Initial mutex implementation"Vincent Palatin2012-01-251-0/+46
|\
| * Initial mutex implementationVincent Palatin2012-01-251-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | They are designed to protect shared hardware resources (e.g. I2C controller). Please refrain using them as a general purpose synchronization primitive for the tasks to avoid unintended slippery effects (e.g. priority inversion), use the provided message-passing functions instead for that purpose. The mutex variable (ie the "struct mutex") should be initially filled with 0, but this is the default compiler behavior if you declare it as a global variable. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make qemu-tests Change-Id: I328f7eadf5257560944dbbbeda0b99d5b24520e8
View Lorry Controller Status