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* g: improve trng error handlingVadim Bendebury2019-05-241-1/+69
| | | | | | | | | | | | | | | | | | | | | | | | We want to be able to track TRNG stalls happening in the field. This patch adds a log message to report detected TRNG stalls. The code detecting the stall is being modified to monitor a different status bit as per chip designer recommendation. A console command allowing to test TRNG is being added, compiled in only if TEST_TRNG is defined. BRANCH=cr50, cr50-mp BUG=b:27646393 TEST=compiled the test command in, ran the command rand 10000000 several times, observed reasonable stats and no stall reports. Change-Id: Idcf83ff2c41e23f601b8da8c46fa4d4d1cde0270 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1601470 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* nvmem: make page header checksums different between prod and devVadim Bendebury2019-05-241-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When moving an H1 between prod and dev Cr50 images, it is important to quickly determine that the NVMEM contents are not retrievable. The first object verified by the initialization routine is the page header, but since SHA value is used for integrity verification, it does not change despite the fact that the mode (and encryption keys as a result) changed. Using encrypted header value for integrity verification guarantees that when transition between prod and dev modes happen the initialization function discovers it right away and reinitializes NVMEM instead of trying to interpret corrupted objects. The host/dcrypto stub used for unit tests and fuzzing needs to be modified to ensure that page headers read from uninitialized flash do not look valid (where encrypted value of 0xffffffff is 0xffffffff). BRANCH=cr50, cr50-mp BUG=b:129710256 TEST=make buildall -j successd, as well as migration of a Chrome OS device from legacy to new nvmem layout. Change-Id: I613513cc67b14f553d2760919d6058f8dbed6e41 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1615423 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* nvmem: do not run when crypto is disabledVadim Bendebury2019-05-242-0/+9
| | | | | | | | | | | | | | | | | | There is no point in trying any nvmem operations when encryption/decryption services are not available. Test changes necessary to make sure test app compiles and runs successfully. BRANCH=cr50, cr50-mp BUG=b:132800220 TEST=The device does not crash any more after tpm is disabled. Change-Id: I97f9afc6e4d5377162500fc757084e4d5a57d37d Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1615424 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* ish: refactor statistic collection and commandJack Rosenthal2019-05-221-59/+45
| | | | | | | | | | | | | | | | | This commit re-writes the power manangment statistic collection and idlestats command to no longer use conditional compilation, and to reduce repetitive code. BUG=b:132178013,b:132929262 BRANCH=none TEST=observed output of idlestats command on arcada_ish, everything appears to be normal Change-Id: I3075eba2ae3f681a2d7d1891f5014de4b6db24a2 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1617079 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: Change G2F cert CN to "CrOS"Louis Collard2019-05-212-8/+19
| | | | | | | | | | | | | | BUG=b:132310780 TEST=flash to soraka, retrieve G2F cert, check CN retrieve anonymous U2F cert, check CN unchanged BRANCH=none Change-Id: Id409ac5d534f2ee9e16376d690f58b184f5ac1a6 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1614581 Reviewed-by: Andrey Pronin <apronin@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* ish: fix printf format for idlestats commandJack Rosenthal2019-05-181-11/+11
| | | | | | | | | | | | | | %ld is for signed numbers, but these are unsigned. BUG=b:132929262 BRANCH=none TEST=used idlestats command on arcada, verified correct output Change-Id: Iffe405ae0d62159d8036248593ed0993e7a5742a Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1617068 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* g: do not destroy manufacturing space by flasheraseVadim Bendebury2019-05-172-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | When modifying flasherase behavior last time around, it was mistakenly presumed that the manufacture_space field was set during Chrome OS device manufacturing. In fact it is set during chip manufacture and should be preserved. BRANCH=none BUG=b:132720245 TEST=using a device with H1 with cert seeds present: - install CR50_DEV=1 image containing this patch - install a recent prod image (it is not yet running, as its version is lower than the ToT) - on Cr50 console run . flasherase . rollback - observe the released image start and successfully complete TPM manufacture process. Change-Id: Id028ffc51bb69810a0564c915b1be944ff5f1d89 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1615422 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* common: chip_save_reset_flags takes uint32_tJack Rosenthal2019-05-174-4/+4
| | | | | | | | | | | | | | | The getters and setters for the reset flags should take and return the same type. `uint32_t' seems the more appropraiate type than `int', so change the setter to take `uint32_t'. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I50928a114858dd51034a048520efa849f5182bd0 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1615648 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ish: fix reading current interrupt vectorHyungwoo Yang2019-05-161-1/+2
| | | | | | | | | | | | | | | | | When we switched to using REG32 macros for registers, we made a mistake in using address of LAPIC's ISR. The original CL that changed this was CL:1586458 BRANCH=none BUG=none TEST=Tested on Arcada platform Change-Id: Ia64806a4cb0fa5d150b41407b0f6c9f34f0168e8 Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1611746 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ish: save and restore reset flags across resetJack Rosenthal2019-05-162-8/+28
| | | | | | | | | | | | | | | | | In order to implement watchdog reset counter, we need to be saving and restoring reset flags. b:132457636 explains the details of the memory layout chosen for the soft-register. BUG=b:132366384,b:132457636 BRANCH=none TEST=reset arcada_ish using: `reboot' command, watchdog expiration, and cold-reset, observed the correct value for "reset cause" printed during boot Change-Id: I84b965803d37703fac6494fb55a97c674ce64b89 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1606074 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: move panic data into AON ROMJack Rosenthal2019-05-161-4/+7
| | | | | | | | | | | | | | | | Currently the panic data is placed in a region that conflicts with the aontaskfw stack. With the extended ROM space, we can put the panic data in a safer location. BUG=b:132457636 BRANCH=none TEST=ran 'crash divzero', observed the panic data copy across reset without any issues Change-Id: I876f3f071e000017c8f2ee744838711da928857c Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1610998 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: increase AON ROM size by 256 bytesJack Rosenthal2019-05-163-5/+9
| | | | | | | | | | | | | | | | | | | | We need to reserve some space in AON persistent memory not to be used by the shim loader. This memory will be used for panic data, reset flags, and watchdog reset counter. We can reduce the size of the panic data for further soft-registers, as needed. Each of these things will be moved into the reserved section in a child CL. BUG=b:132457636 BRANCH=none TEST=entered d0i0, d0i1, d0i2, d0i3, and rebooted to test aontaskfw is working Change-Id: I41f39d28a6b5a3424f1c89b0e0884e72df04225f Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1610997 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: fix GPIO interrupt enabling and statusHyungwoo Yang2019-05-141-0/+5
| | | | | | | | | | | | | | | | | | | | currently the GPIO interrupt mask register and status register are not initialized on warm reset. so some interrupts can be enabled even before corresponding things are ready. this patch disables all GPIO interrupts and clears pending interrupts during gpio initialization(gpio_pre_init()). BRANCH=ish BUG=b:130717887 TEST=tested on Arcada platform Change-Id: I01c237f667c7a3b6d1eb63d81c9ab604a6213453 Reviewed-on: https://chromium-review.googlesource.com/1611749 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* host: Fix test breakageRaul E Rangel2019-05-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There seems to be a breakage on ToT: BUILD host-cr50_fuzz VERSION ec_version.h make obj=/mnt/host/source/src/platform/ec/build/host/cr50_fuzz/cryptoc SUPPORT_UNALIGNED=1 \ CONFIG_UPTO_SHA512=y -C /mnt/host/source/src/third_party/cryptoc make[2]: '/mnt/host/source/src/platform/ec/build/host/cr50_fuzz/cryptoc/libcryptoc.a' is up to date. CC RO/chip/host/dcrypto/aes.o In file included from chip/host/dcrypto/aes.c:8: In file included from board/host/dcrypto.h:24: In file included from ./chip/g/dcrypto/dcrypto.h:22: In file included from ./chip/g/dcrypto/internal.h:13: include/util.h:82:16: error: attribute declaration must precede definition [-Werror,-Wignored-attributes] __attribute__((visibility("hidden"))) int atoi(const char *nptr); ^ /usr/include/stdlib.h:361:32: note: previous definition is here __attribute__ ((__nothrow__ )) atoi (const char *__nptr) ^ 1 error generated. make[1]: *** [Makefile.rules:480: build/host/cr50_fuzz/RO/chip/host/dcrypto/aes.o] Error 1 make: *** [Makefile.rules:281: host-cr50_fuzz] Error 2 BUG=none BRANCH=none TEST=make runtests -j Change-Id: Idf2c901a0c12fa4ebfabdf7d1205430153b8de9f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1605511 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ish: set firmware status to running during pre-initJack Rosenthal2019-05-141-0/+3
| | | | | | | | | | | | | | This adds a firmware status update to FWSTS_FW_IS_RUNNING during boot. BUG=b:132060059 BRANCH=none TEST=Observed firmware status is 7 (IS_RUNNING) during boot before HECI ready. Change-Id: If41c86838a956023754be960472b8c641416b7c9 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1597674 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: add more explanations comments for reset flow in aontaskJett Rink2019-05-141-3/+29
| | | | | | | | | | | | | BRANCH=none BUG=none TEST=ISH still reset properly on arcada Change-Id: I08a5935c5e8d1728e2984cbc70d75e380eb66f55 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1601349 Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* ish: fix lapic table readJett Rink2019-05-141-1/+1
| | | | | | | | | | | | | | | | | When we switched to using REG32 macros for registers, we also changed the math for the offset of the lapic. Fixing the pointer math. The original CL that changed this was CL:1586458 BRANCH=ish BUG=none TEST=ISH runs normally Change-Id: I1beea99ede496a2eee2adf96adeec21b3f1e1fd4 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1600158 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* ish: update firmware statusHyungwoo Yang2019-05-142-0/+5
| | | | | | | | | | | | | | | Currently we missed some FW status updates that are used by host in taking critical action. BUG=b:132060059 BRANCH=none TEST=tested on Arcada platform Change-Id: I7ad607869f821eae99e37704ab3d6567d180aadd Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1601780 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: fix bugs in fwst check functionsHyungwoo Yang2019-05-141-2/+2
| | | | | | | | | | | | | | | currently functions to check the status of ilup(IPC link up) and hup(HECI up) are changing values of FW status which is bug. BRANCH=none BUG=none TEST=tested on Arcada platform Change-Id: I1839304af619a3ee5a0856fe83560aa21a99e60a Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1601779 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish/ish5: fixed both-edge triggered gpio configuration blocking D0ix issueHu, Hebo2019-05-122-42/+97
| | | | | | | | | | | | | | | | | | | | | | | | | ISH PMU does not support both-edge interrupt triggered gpio configuration. If both edges are configured, then the ISH can't stay in low power mode because it will exit immediately. As a W/A, we scan all gpio pins which have been configured as both-edge triggered, and then temporarily set each gpio pin to the single edge trigger that is opposite of its value, then restore the both-edge trigger configuration immediately after exiting low power mode. BUG=b:132001235 BRANCH=none TEST= tested on arcada platform, console should freeze after entered low power mode Change-Id: I83a43d9fbee6cfd1a6820bdb44c1446f109ffb32 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1600310 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* stm32: Decouple printf logic from directly calling USB console driverWai-Hong Tam2019-05-111-56/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When calling printf functions, it was to call the USB console driver directly, i.e. copying all the bytes to USB package buffer and enabling the transmission. If the next printf is called immediately before the USB transmission is done, it will wait (polling the EP_TX_VALID status). This implementation limited each printf function can only transmit 64 bytes, i.e. the USB max package size. The remaining bytes will be dropped silently. To fix this issue, this CL puts a queue between the printf logic and the driver. The size of the queue is 2048-byte (no overflow happened on a normal boot and console commands). The printf logic now fills the queue and schedules a deferred hook to handle the transmission. When the transmission is done, an interrupt will be triggered that schedules the deferred hook again to check any remaining bytes need to be transmitted. For the incoming bytes, replace the circular buffer to a queue structure for better reusability. No major logic changes. BRANCH=servo BUG=b:129423678 TEST=Manually added a printf call to show >64 bytes and verified it. TEST=Manually added a printf call to show >2048 bytes and the bytes after the 2048-th dropped silently. Change-Id: Icb2310421d7bcbbff8d7cd753c732390acc43ab8 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1597960 Commit-Ready: Todd Broch <tbroch@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* ish: combine watchdog expiration and panic handlerJack Rosenthal2019-05-091-27/+0
| | | | | | | | | | | | | | | | | | watchdog_warning implements similar functionality to exception_panic, but worse, as the value it prints for EIP is wrong, and it does not have the no-double-panic logic of the panic handler. This commit removes watchdog_warning and integrates the relevant functionality into exception_panic. BUG=b:129983997 BRANCH=none TEST=observed watchdog reset with 'waitms 10500' Change-Id: I78375337aa85be5424850e29a8204c409384d019 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1599732 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish/ish5: remove watchdog disable during D0ixHu, Hebo2019-05-093-26/+3
| | | | | | | | | | | | | | | | | | | | | | ECOS will reload watchdog in hook task for every HOOK_TICK_INTERVAL time, and this will make HPET timer 1 wakeup ish. Therefore, we do not need to disable watchdog during D0ix. D3 and reset prep flow still need disable watchdog. BUG=b:132112137 BRANCH=none TEST='waitms 10500' console command can trigger watchdog timeout and ish reboot Change-Id: I11aad5ece0ce96bc53738512290c1e42bf175479 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1598713 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ish: remove erroneous REG32 in ish_fwsts.hJack Rosenthal2019-05-071-1/+1
| | | | | | | | | | | | | | I'm a screw-up and forgot this in CL:1578435. Since ish_fwst_is_hup_set is not used (yet), this did not cause any issues. BUG=b:130573158,b:132060059 BRANCH=none TEST=make buildall -j Change-Id: I38a25a648b2235bade143fd20acb50a1318da992 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1596312 Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32f0: Set ADC sampling rate before every readDaisuke Nojiri2019-05-043-24/+39
| | | | | | | | | | | | | | | | | | | | | | | Currently, the sampling rate is set only once in adc_init. This patch makes EC set the sampling rate every time ADC is sampled. This patch also adds STM32_ADC_SMPR_DEFAULT so that zero can be used to specify the default sampling rate. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b/131579158 BRANCH=none TEST=Verified ADC readings match with externally measured voltage for LCM_ID, BATT_ID, and USBC_THERM. TEST=buildall Change-Id: I73a1352dec907c2a8724e2f3f3d0258a706910a7 Reviewed-on: https://chromium-review.googlesource.com/1589253 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* ish: preserve panic data across resetJack Rosenthal2019-05-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit stores panic data across reset by storing panic data in the last 256 bytes of AON memory (before AON ROM). > crash divzero ========== PANIC ========== Reason: Divide By Zero Error Code = 0xFF00B60C EIP = 0xFF010008 CS = 0x00010202 EFLAGS = 0x00103085 EAX = 0x00000001 EBX = 0xFF01B118 ECX = 0x00000000 EDX = 0x00000000 ESI = 0x00000000 EDI = 0xFF017E0E Resetting system... =========================== ... ISH reset ... > panicinfo Saved panic data: (NEW) Reason: Divide By Zero Error Code = 0xFF00B60C EIP = 0xFF010008 CS = 0x00010202 EFLAGS = 0x00103085 EAX = 0x00000001 EBX = 0xFF01B118 ECX = 0x00000000 EDX = 0x00000000 ESI = 0x00000000 EDI = 0xFF017E0E BUG=b:129425206 BRANCH=none TEST=see console output above (on arcada_ish) Change-Id: I5c9e458b53076eafe7fa50ba851f2c6e863f2247 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1593418 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: ensure all CONFIGs are undef'ed in include/config.hJack Rosenthal2019-05-045-64/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some people have been bypassing the pre-submit checks: confs=($(grep -Eor "\bCONFIG_[A-Z_]*" chip/ish/config_chip.h | sort | uniq)) for opt in "${confs[@]}"; do grep "$opt" include/config.h >/dev/null || echo "$opt is not defined in include/config.h!" done >>> CONFIG_ISH_AON_SRAM_BASE_END is not defined in include/config.h! CONFIG_ISH_AON_SRAM_BASE_START is not defined in include/config.h! CONFIG_ISH_AON_SRAM_ROM_SIZE is not defined in include/config.h! CONFIG_ISH_AON_SRAM_ROM_START is not defined in include/config.h! CONFIG_ISH_AON_SRAM_SIZE is not defined in include/config.h! CONFIG_ISH_SRAM_BANKS is not defined in include/config.h! CONFIG_ISH_SRAM_BANK_SIZE is not defined in include/config.h! CONFIG_ISH_SRAM_BASE_END is not defined in include/config.h! CONFIG_ISH_SRAM_BASE_START is not defined in include/config.h! CONFIG_ISH_SRAM_SIZE is not defined in include/config.h! This is not good! This commit renames each of these to an existing option defined in include/config.h, or undefs the relevant option in include/config.h. BUG=b:131749055 BRANCH=none TEST=make buildall -j TEST=script above reports no options which weren't defined TEST=arcada_ish, (specifically power management, which was greatly affected by this commit) functions as normal Change-Id: Idfbd1105880174b5e160c47c4ec1d88c352d6bc6 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1592420 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish/heci: print protocol for discarded msgsJett Rink2019-05-031-1/+1
| | | | | | | | | | | | Print the protocol id of discarded messages on console BRANCH=none BUG=none TEST=verified that protocol is being printed correctly Change-Id: I089ad0c55b89a321edcbf24f25ec13e13fda60b3 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1594109
* ish: make sure last_deadline always validHyungwoo Yang2019-05-031-0/+9
| | | | | | | | | | | | | | | | If there's no timer event with current clksrc_high then last_deadline should have the maximum value(0xFFFFFFFF) within the clksrc_high since we always get timer event at every new clk_high. BRANCH=none BUG=none TEST=Tested in Arcada platform Change-Id: Iebea955b1aefc7d986b493a8be84b8fd25812441 Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1593092 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* ish/ish5: fix some HPET issues.Hu, Hebo2019-05-022-14/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 1: extra timer 0 and timer 1 interrupt issue no wait settling before write HPET generical interrupt status register, may cause clear irq failed since value may write failed. this can cause extra timer interrupt issue. 2: new comparator value update for timer 1 may failed need wait settling before update timer 1 comparator value in __hw_clock_event_set() 3: need check main counter value's validity after exit TCG low power mode in low power TCG mode, the main counter value will become invalid, after exit TCG mode, HW will restore it, but FW need to wait check if it's valid. BRANCH=none BUG=b:131515624 TEST=tested on arcada platform Change-Id: I84586285ddb150cbae453f24dd172d238ec5b324 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1583664 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* kukui_scp: Enable MPU to protect code RAM and data RAM in RW image.Yilun Lin2019-05-022-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kukui_scp is loaded into SRAM. We would like to protect the memory from a modified code RAM content and executing injected code in data RAM. BRANCH=None BUG=b:123269246 TEST=Apply MPU test patch https://crrev.com/c/1530265. Test data ram XN: 1. mpu 0 # disable MPU 2. mpu_test # see it prints 3. mpu 1 # enable MPU 4. mpu_test # memory access violation, and reset. 5. mpu_test # memory access violation, and reset # again. (MPU enabled by default) Test code ram RO: 1. rw 0x8 0x5566 # Write to code RAM and see memory # access violation and reset. 2. mpu 0 # disable MPU 3. rw 0x8 0x5566 # Nothing happended 4. rw 0x8 # Read 0x5566 5. mpu 1 # enable MPU 6. rw 0x8 0x5566 # memory access violation. Change-Id: I6af5029d8c55d795543d4759b2c9168a06eb9ff1 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530264 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* ish: refactor IPC usage of REG macros into registers.hJack Rosenthal2019-05-024-78/+60
| | | | | | | | | | | | | This is the final CL needed to resolve b:130573158. BUG=b:130573158 BRANCH=none TEST=arcada_ish functions as normal after changes Change-Id: Ia4cc9bfa95938b9f57fc1cd241cd6821b42a3ce6 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1578435 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: move REG32 macros for interrupt control into header filesJack Rosenthal2019-05-013-39/+43
| | | | | | | | | | | | | | | This is a good portion of the fixes needed for b:130573158, but we still have the HECI registers to deal with. I have those in a separate CL as they were giving me a significant amount of trouble. BUG=b:130573158 BRANCH=none TEST=arcada_ish is functioning as normal after changes Change-Id: I9c209a329d61f7f55c260006cdffbfc705521195 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1586458 Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm/it83xx.c: Bx and Dx transmit status bit of pd register swapRuibin Chang2019-04-302-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | Chip Bx and Dx transmit status bit (PD register offset 0x18, MTCR) swap. Bx: bit5, 1'b0 = none 1'b1 = goodcrc not received and retry times arrive bit1, 1'b0 = transmit OK 1'b1 = goodcrc not received or Tx discarded Dx: bit5, 1'b0 = transmit OK 1'b1 = goodcrc not received or Tx discarded bit1, 1'b0 = none 1'b1 = goodcrc not received and retry times arrive BRANCH=None BUG=None TEST=Test by device which do not respond goodcrc message Change-Id: Ia07ad4bdb7f4800b62a25eb88ac42e42311faa7d Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1545800 Reviewed-by: Jett Rink <jettrink@chromium.org>
* mt_scp: Generate IPI tables with util gen_ipi_table.Yilun Lin2019-04-302-25/+10
| | | | | | | | | | | | | | | | | | | | IPI table is board-specific. This CL removes the original IPI table in chip layer, and uses gen_ipi_table to generate the table for each board to reduce the maintenance effort. TEST=make BOARD=kukui_scp, and see build/kukui_scp/ipi_table_gen.inc exists. Push to Kukui, and see SCP boots. TEST=modify IPI_COUNT in board.h and see it generates a new ipi_table_gen.inc BUG=b:130508869 BRANCH=None Change-Id: I0c05319447d15917e8833aa80d61166c4e396370 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1568890 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/(mec1322|mchp): Drop math expressions in MEMORY ORIGIN/LENGTHNicolas Boichat2019-04-292-4/+18
| | | | | | | | | | | | | | | | | binutils/ld 2.32 does not allow expressions in MEMORY regions (for some reason 2.31.1 was fine with that). Replace the expression with a constant, and add 2 assertions to check that the values are sane. BRANCH=none BUG=chromium:957361 TEST=make buildall -j with latest coreboot-sdk, no error Change-Id: I679f1a0ff24e96f215a52cdd6f2cde8540901b8e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1587256 Reviewed-by: Sean Abraham <seanabraham@chromium.org>
* npcx: disable the selection of JTAG0 signals due to strapCHLin2019-04-276-196/+259
| | | | | | | | | | | | | | | | | | | | | | | | It was observed that pressing recovery key combination + the other keys, some keys on the keyboard become invalid after system reboots. (see b:129908668 for more detail.) It is because the hardware strap pin for JTAG0 signals is unintentionally triggered. This CL reverts the selection of JTAG signals and set them back to keyboard scan function at system initialization. The revert applies to all real platforms except npcx_evbs. BRANCH=none BUG=b:129908668 TEST=pass "make buildall" TEST=Press the specific key combination, after the system reboots, the keyboard function works normally. On npcx EVBs, the JTAG0 is still functional. Change-Id: I7ede1ea4609466fea50a97b1f60308e4cdfd4544 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1575887 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Revert "kukui: scp: calibrate ULPOSC1&2"Yilun Lin2019-04-262-183/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e08a71fd05bfc9e32dd64b7e15840e7232d72788. Reason for revert: SCP will hang with this CL. Original change's description: > kukui: scp: calibrate ULPOSC1&2 > > ULPOSC generates clock for SCP core and peripherals. The calibration > process adjust 2 values, div and cali. Both values are positive > correlated to OSC frequency. The frequency function is: > f(div, cali) = k1 * (div + k2) / R(cali) * C > Where: > R(cali) = k3 / (1 + k4 * (cali - k4)) > > The actual frequency is not linear to cali parameter. This change > selects the div that generates closest frequency when cali == 32. And > then adjust cali to get better output. > > BRANCH=none > BUG=b:120176040,b:120169529 > TEST=manual > check SCP console command: > > ulposc > ULPOSC1 frequency: 248 MHz > ULPOSC2 frequency: 330 MHz > > Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 > Signed-off-by: Rong Chang <rongchang@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/1520571 > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Bug: b:120176040, b:120169529, b:131273034 Change-Id: Ifaeb9a7835a35556587fac4c039b9fde6d66504d Reviewed-on: https://chromium-review.googlesource.com/1583481 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* ish: cleanup of UART-related functionalityJack Rosenthal2019-04-262-196/+164
| | | | | | | | | | | | | | | | | | | This commit cleans up UART-related ISH code: * Moving REG{8,16,32} macro usages into header files * Changing ifdef logic in code to use IS_ENABLED macro * Reduce repeated code in uart_defs.h * Change hexadecimal masks in uart_defs.h to use BIT(n) macros * Change disabling of UART2 to use common logic in uart_stop_hw BUG=b:130573158 BRANCH=none TEST=UART on arcada_ish is functioning as normal Change-Id: Ia05feea2de8c14e44e4d3f9dd7c790bcb81cd1c0 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1582457 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ish: fix s/w generated interrupt requestHyungwoo Yang2019-04-261-1/+2
| | | | | | | | | | | | | | | | | Current s/w generated IRQ uses LAPIC's ICR but it causes pending interrupts for other IRQs in IOAPIC and leads LVT error with illegal vector. So instead of using ICR, we use "int" instruction. BRANCH=none BUG=b:129937881,b:124128140 TEST=Tested on Arcada platform Change-Id: I49c4120e7355f9a98d20d5ed259c4fdf6bad5196 Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1568786 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* chip/g: prevent USB read queue overflowNamyoon Woo2019-04-263-2/+8
| | | | | | | | | | | | | | | | | | | | CR50 should check whether USB RX queue has enough space for host data. If not, it schedules to retry it in another deferred call. BUG=b:130908211 BRANCH=cr50 TEST=manually ran "echo 'help' > /dev/ttyUSB0" more than 30 times. Without this CL, it used to break cr50 console input, and it worked as if it is 'read-only'. After applying this CL, cr50 console input works normal even after excessive input stream. Change-Id: Ieace84b51c31800b52d2c4a9334e6ffe7888e592 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1576326 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* ish: refactor bit-mask constants to use BIT macroJack Rosenthal2019-04-245-97/+92
| | | | | | | | | | | | | | | We should be using the BIT(n) macro rather than (1 << n), as it prevents errors, and makes the intended purpose a little bit easier to read. BRANCH=none BUG=none TEST=make buildall -j Change-Id: Ia727ac2f8e5abfb852ba78d5cba19d7c8af72839 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1567688 Reviewed-by: Jett Rink <jettrink@chromium.org>
* minute-ia: hard reset if we panic while handling a panicJack Rosenthal2019-04-241-13/+9
| | | | | | | | | | | | | | | | | ish_pm_reset is a rather complex procedure, and encountering a panic while it is happening could lead to an infinte loop of handling panics. This will preform a reset of the Minute-IA core if a panic occurs and the system is already resetting from panic. BUG=b:130752748,b:130587334 BRANCH=none TEST=copied some invalid opcodes into switch_to_aontask procedure, observed the hard reset after forcing a panic Change-Id: I43459d78da9b67297f84e3a736d3f92da42a814c Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1576835 Reviewed-by: Jett Rink <jettrink@chromium.org>
* kukui: scp: calibrate ULPOSC1&2Rong Chang2019-04-242-66/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | ULPOSC generates clock for SCP core and peripherals. The calibration process adjust 2 values, div and cali. Both values are positive correlated to OSC frequency. The frequency function is: f(div, cali) = k1 * (div + k2) / R(cali) * C Where: R(cali) = k3 / (1 + k4 * (cali - k4)) The actual frequency is not linear to cali parameter. This change selects the div that generates closest frequency when cali == 32. And then adjust cali to get better output. BRANCH=none BUG=b:120176040,b:120169529 TEST=manual check SCP console command: > ulposc ULPOSC1 frequency: 248 MHz ULPOSC2 frequency: 330 MHz Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520571 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* tasks: convert TASK_EVENT_CUSTOM macro to bitJett Rink2019-04-246-12/+12
| | | | | | | | | | | | | | | | | | | | | We should ensure that all custom task definition are non-zero and fit with the globally defined events. Add compile time check and change semantics to specify bit number (instead of making all callers use the BIT macro). This also fixes an error with TASK_EVENT_PHY_TX_DONE for ITE being 0. The bug that made that happen hasn't landed on any firmware branches that use it though. BRANCH=none BUG=none TEST=builds Cq-Depend:chrome-internal:1178968,chrome-internal:1178952 Change-Id: I5e1d1312382d200280c548e9128e53f4eddd3e61 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1570607 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* mkbp: take timestamp closer to hardware interruptJett Rink2019-04-246-16/+66
| | | | | | | | | | | | | | | | | We want to ensure that the timestamp we take for last mkbp is as close to the actual hardware interrupt from EC->AP. BRANCH=none BUG=b:129159505 TEST=passing CTS sensor run (except test 133 nullptr) with this change Change-Id: I94b214f021f0b63ff2883e5fe8e32acc83ce208f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1560390 Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* ish/ish5: add console in use timeout mechanism in low power managmentstabilize-12121.BHu, Hebo2019-04-233-9/+62
| | | | | | | | | | | | | | | | | | | | | | | | on ISH, uart interrupt can only wakeup ISH from low power state via CTS pin, but most ISH platforms only have Rx and Tx pins, no CTS pin exposed, so, we need block ISH enter low power state for a while when console is in use. we have two default timeout values for this mechanism: 1: after ISH boot, have 15 seconds window can input console commands 2: refresh 60 seconds timeout for console use after each console input BUG=b:129246461 BRANCH=none TEST=verified on arcada platform Change-Id: Ic3bb33a7984e1bf55654403c76287617c8828daa Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1574375 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* kukui: scp: move CPU clock selection to clock moduleRong Chang2019-04-232-2/+6
| | | | | | | | | | | | | | | | CPU clock management should be in clock module. BUG=b:120169529 BRANCH=none TEST=manual build and load on kukui, check SCP console command: > rw 0x405C4000 read 0x405c4000 = 0x00000803 Change-Id: Ic13e9a51cf682af33799b713849fd3a445e6cfdb Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538097 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: Set CPU clock to default before ULPOSC calibrationRong Chang2019-04-231-0/+1
| | | | | | | | | | | | | | | | | | ULPOSC 1 & 2 calibration may fail if SCP CPU clock selection is configured to one of them. The SCP reset mechanism does not reset the clock selection. So before calibration, set CPU to default clock. BUG=b:125695639 BRANCH=none TEST=manual build and load on kukui, check remoteproc init correctly. check SCP uart console command 'ulposc', output non-zero clocks. Change-Id: I6807017808a663f8e80363dc0672748ab1957978 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538096 Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ish: fix extra timer interruptHyungwoo Yang2019-04-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | currently we often clear timer interrupt status before the main counter gets increased. Due to this, HPET timer generates extra interrupt since the counter and the comparator have still the same value(?). This introduces wrong wall clock and some extra interrupts for events. ... [17178.756500 HC 0x67 err 9] [21476.327769 HC 0x67 err 9] <= extra interrupt changed wall clock ... [30051.881380 HC 0x67 err 9] [34363.588056 HC 0x67 err 9] <= extra interrupt changed wall clock ... [38653.530377 HC 0x67 err 9] [42961.575341 HC 0x67 err 9] <= extra interrupt changed wall clock This patch make sure there's no extra interrupt. BRANCH=none BUG=none TEST=Tested on Arcada platform Change-Id: Ia57f4f2e91b52f0466f248388643d997d60b3221 Signed-off-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1573199 Commit-Ready: Jack Rosenthal <jrosenth@chromium.org> Tested-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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