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* stm32f05: decrease default system stack sizeAlec Berg2015-07-291-0/+4
| | | | | | | | | | | | | | | Decrease default system stack size on stm32f05 which only has 8k of RAM. BUG=none BRANCH=none TEST=tested on glados. just ran glados_pd and plugged various peripherals into type-C port and saw nothing unusual. Change-Id: Ic051a1387903662414c8e4fdc431e6ecfd7ad57f Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289555 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: keep 32KHz on for ROSC accuracyKyoung Kim2015-07-281-7/+1
| | | | | | | | | | | | | | | | | | 32KHz osc is necessary to key ROSC in +-2% accuracy. If 32KHz osc is off/on during the heavy sleep, UART produces garbage characters to Tx port until its clock to be stabilized. BUG=none TEST=Cyan BRANCH=none Change-Id: Ie045b9f152eb7dc8d888a2840babefac68081cef Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/288421 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* stm32: Define second DMA controller present on STM32F3Gwendal Grignou2015-07-272-11/+49
| | | | | | | | | | | | | Define second DMA controller, to be used by SPI3 on STM32F373. BRANCH=smaug TEST=Check with dmahelp the DMA engine is activated. BUG=chrome-os-partner:42304 Change-Id: Id2490ab91092b1ed738f5318bdeebfbe93f09171 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288511 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Change interface to dma_testGwendal Grignou2015-07-271-2/+1
| | | | | | | | | | | | | | Allow to test any DMA channel. BRANCH=smaug TEST=Use dmahelp on Ryu BUG=chrome-os-partner:42304 Change-Id: I68606cdd34aa03bbeed9b5a4ababcad780384cc0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288510 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Atomic: Mark the modified uint32_t volatileAnton Staaf2015-07-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | The atomic_* functions are often used in contexts where the data they will operate on are volatile (due to being shared between tasks or a task and an interrupt handler). Adding volatile here makes using the atomic_* functions a little easier in those cases and removes a cast from the call sites (which could be obscuring a bug, if for instance the variable was modified to be a uint16_t). Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I71356eb3cf2c0506df38532eee767c7d78f9240e Reviewed-on: https://chromium-review.googlesource.com/287516 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* Cr50: Enable TPM-protocol data over the SPI busVadim Bendebury2015-07-254-3/+294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a module which runs on top of the SPS driver and implements the TCG SPI TPM protocol. Basic register read and write functions are implemented as well as rudimentary TPM state machine (claiming/releasing locality). An enhancement is made to the SPS driver to ensure that when the CS is deasserted the transmit FIFO is reset too, on the off chance of the CS going away mid transaction for whatever reason. In this implementation the slave is guaranteed to stall the master for a few bytes in both receive and transmit transactions, which is further aggravated by the fact that RX FIFO threshold is set to 8 (this is the minimum number of bytes the master has to send to wake up the slave). This could be fine tuned later, for instance made a parameter of the receive callback registration function. BRANCH=none BUG=chrome-os-partner:43025 TEST=trunksd initialization (with minor changes to accommodate new VID/DID and some status bits, to be published) succeeds with the cr50 connected to the USB/SPI cable. Change-Id: I28d37c3b57dde9adf59e81426efe4f58880cf0b0 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/285252
* sps: expose RX FIFO write pointerVadim Bendebury2015-07-252-0/+6
| | | | | | | | | | | | | This is necessary for proper TPM SPI flow control operation. BRANCH=none BUG=chrome-os-partner:43025 TEST=none yet Change-Id: I571cab87c843aebaac24657d340ae3b51a5560b4 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/287128 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: Use distinct configuration option for SPI Slave supportVadim Bendebury2015-07-253-7/+7
| | | | | | | | | | | | | | | | | | | | SPI slave and master interfaces require very different code to support, they should have separate configuration options. Host command code printouts should use their own console channel. Using SPS to designate SPI Slave interface is not universally acceptable, a bug has been opened to discuss the alternatives and clean up the code. BRANCH=none BUG=chromium:512613 TEST=make buildall -j Change-Id: I6683286a221c4689ecc247fdfe8ebca529f3f458 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/286469 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* nuc:Ian Chao2015-07-2512-183/+317
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ECST tool to modify the header used by npcx booter. Modified drivers: 1. i2c.c: Modify for i2c_port design. 2. i2c.c: Fixed bugs when mutil-tasks use the same i2c port and pull-up issue. 3. hwtimer.c: Fixed bug whcih event expired time is behide current timer. 4. lpc.c: Add intializing host settings after pltrst is deasserted. 5. uart.c/clock.c/register.h: Fixed bug which cannot enter deep-idle when gpio is any-edge trigger mode. 6. task.c: Add workaround method for hard fault issue. 7. keyboard_raw.c: Modified for support CONFIG_KEYBOARD_KSO_BASE 8. lpc.c: Modified for support CONFIG_KEYBOARD_IRQ_GPIO 9. lpc.c: fixed obe interrupt bug during 8042 initialization 10.Adjust path of flat files for new Makefile rules 11.Fixed build error on lpc.c without CONFIG_KEYBOARD_IRQ_GPIO BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Icf9494174b245b4026e396be877d578f36b6f6a5 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/284036 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* glados: V2 Board ChangesShawn Nematbakhsh2015-07-241-1/+1
| | | | | | | | | | | | | | | Changes for glados proto 2 build. These changes are behind GLADOS_BOARD_V2, which is not defined by default in order to support existing boards. BUG=chrome-os-partner:42933 TEST=Verify that Glados v1 board continues to boot AP. Verify compilation on GLADOS_BOARD_V2. BRANCH=None Change-Id: I68634f95f94d3d37f18d676c01219f92b6ddfc45 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/287291 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* it8380dev: fix reset causeDino Li2015-07-221-4/+8
| | | | | | | | | | | | | | | | | | | | symptom: there are many reset cause while chip power on. root cause: there is no default value for bram. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. "power-on" reset cause still exist. 2. console "reboot" hard, preserve, and ap-off. 3. console "sysjump" rw and ro. Change-Id: Ie190ade4990bfaf46e73746ac5019f61307c81e5 Reviewed-on: https://chromium-review.googlesource.com/286281 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* USART: Add DMA based transmitterAnton Staaf2015-07-218-0/+230
| | | | | | | | | | | | | | | | | | | | | | | This adds a new transmission implementation for the multi UART driver. It is a DMA based transmitter that can directly read from the TX queue with zero copy overhead. The DMA channel used as well as the maximum DMA transmission size are configurable per UART at the board level. This also updates the Ryu AP UART to use DMA transmission. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Manually verify that the AP UART forwarding works Change-Id: I3cb27d0f9015043d75a38c12919388afe90dc4af Reviewed-on: https://chromium-review.googlesource.com/286274 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* mec1322: hibernate: Fix wake-on-AC for USB-CShawn Nematbakhsh2015-07-201-7/+55
| | | | | | | | | | | | | | | | | Fix hibernate so that plugging a USB-C charger properly wakes the system. In addition, change the default hibernate behavior to restart after wake. BUG=chrome-os-partner:42104 TEST=Run 'hibernate' on Glados. Verify that wakes occur when power button is pressed, lid switch is toggled, or when a charger is attached to either USB-C port. BRANCH=None Change-Id: I54b8d58e20c35f25883238df24e7f23bb743abaa Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/286660 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: GPIO: Use common macro for converting mask to GPIOShawn Nematbakhsh2015-07-194-11/+11
| | | | | | | | | | | | | | The same calculation is used across the code, so move it to a common macro. BUG=chrome-os-partner:42104 TEST=Verify Glados still boots AP. BRANCH=None Change-Id: I90da348f37fc670971737cfc5ddcfb9c34096c4b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/286169 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: heavysleep in idle task and console deepsleepKyoung Kim2015-07-173-2/+491
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented mec1322's heavysleep in idle task to reduce further EC power down on S3. MEC1322 needs sleep-enabled for all blocks to acheive max power down including UART. Real heavysleep will be effective only when console/uart is not active. To enable this commit, board-specific commit is required. For example, check commit, "Enabling heavysleep idle task at S3". Test: 1. Put device into S3 mode by typing 'powerd_dbus_suspend" in Linux shell. 2. wait at least 1 min till EC console sleeps 3. measure EC power. Since idle task is continuously scheduled, EC will enters/exits to/from heavy sleep mode frequently in S3 and power consumption will be changed dynamically. For acurate power measurement, high-sampling-rate measurement system might be required and using DMM might not give accurate number. BUG=None TEST=Tested on evt1p0/evt1p7/DVT BRANCH=None Change-Id: I435ca347cab2f4d51cefeee802c3bf30fb393fa1 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283603 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* cr50: restore SPS driver performanceVadim Bendebury2015-07-175-392/+373
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There have been a few changes made to the sps driver recently, which were not necessary but caused performance degradation: the continuous loopback test is showing transmit underrun (0xff bytes stuck into the frames). This patch restores the driver to its state before the recent changes and then makes a few modification to account for the new API: - added a way to specify idle byte transmitted on MISO - port number is dropped The actual differences between the old and new version of the driver can be seen as follows: git diff dbf027f chip/g/sps.c The restored driver passes the loopback test successfully. BRANCH=none BUG=none TEST=used the enhanced 'spiraw' utility which sends frames of random size in 10..1010 bytes, and then clocks the line to receive the same amount of bytes back, syncs up in the returning stream of bytes and compares received and transmitted data. # run 'spst 100' on the target $ src/examples/spiraw.py -l 100 -f 2000000 FT232H Future Technology Devices International, Ltd initialized at 2000000 hertz $ which is an indication of the successful loop back of 100 frames. The cli command on the target exits and reports the stats: > spst 100 Processed 100 frames rx count 108532, tx count 51366, tx_empty count 100, max rx batch 11 Before this change spiraw.py was reporting numerous mismatches on the host side. Change-Id: Iaa8c94e439ac32a6f10f12ddbdbf445865807386 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/286015 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* build-infr: Add support for shared RO library.Aseda Aboagye2015-07-171-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces the build infrastructure changes needed for creating a shared RO library. (libsharedobjs). The end goal is for the library to contain various objects that can be shared with both the RO and RW EC images. Now, there are 3 make goals: ro, rw, and libsharedobjs. In order for changes that are only specific to a single image (ie: RW only) to be applied correctly, the object files are now built separately for the RO, RW, shared objects library targets. NOTE: Certain EC targets are incompatible with this model due to the fact that only one image is present within flash at a time. BRANCH=none BUG=None TEST=make -j buildall tests TEST=make -j BOARD=cr50 xrefs TEST=make BOARD=samus dis TEST=Built samus EC image and compared that the final EC image was identical to the upstream version (except for the git SHAs & version strings). CQ-DEPEND=CL:285934 Change-Id: I8e67f089710be9c6d7017718109262394bdad2f5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/274079 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* cyan: fix issues with write protectionAndrey Petrov2015-07-161-63/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Fixes cyan/board.h to use correct SPI part * Adds new flash protection regions in spi_flash_reg.c * Sets SRP register in flash_physical_protect_at_boot() * Fixes a bug in COMPARE_BIT macro * Makes spi_flash_set_status() fail only when both HW pin is asserted AND SRP(s) are set * Makes sure set_flash_set_status() completes before returning BUG=chrome-os-partner:40908 BRANCH=master TEST=on Cyan: With WP pin de-asserted: flashrom -p ec --wp-enable flashrom -p ec --wp-status, make sure it is enabled flashrom -p ec --wp-disable flashrom -p ec --status, make sure it is disabled flashrom -p ec --wp-enable Assert WP pin (either with screwdriver or dut-control) flashrom -p ec --wp-disable make sure it failed Change-Id: I338cc906b73e723fdbb37f7c2fd0c4da358b6c8e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/276671 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* mec1322: Allow multiple hibernate wake sourcesShawn Nematbakhsh2015-07-162-23/+37
| | | | | | | | | | | | | | | | | Allow multiple GPIOs to wake the EC from hibernate by requiring boards to define hibernate_wake_pins and hibernate_wake_pins_used. In addition, clean up the GPIO-skipping hibernate code, and skip setting PCH_RTCRST as an input due to a bug on certain boards. BUG=chrome-os-partner:42104 TEST=Manual on Glados. Run 'hibernate' from EC console, verify that EC wakes with power button press or with "dut-control lid_open:no". BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I13a6e062393cab8ed7129eda253585951f771109 Reviewed-on: https://chromium-review.googlesource.com/285924 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* ADC: Add common priority for the ADC initVijay Hiremath2015-07-166-6/+6
| | | | | | | | | | | | | | Added common priority for the ADC init to ensure board level priority is defined for the ADC pre init. BUG=none TEST=make buildall -j BRANCH=none Change-Id: Id1649df6a68ab53bd110e58a0722bd4c70cbffc5 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/286040 Reviewed-by: Shawn N <shawnn@chromium.org>
* USART: Add flexibility needed to support DMAAnton Staaf2015-07-155-112/+185
| | | | | | | | | | | | | | | | | | | | | | In order to support DMA transfers in one or both directions the usart driver needs to be configurable with producer/consumer operations and interrupt handler functions. These are now packaged up in the usart_rx and usart_tx structs, and versions for interrupt driven RX and TX are provided. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I3fd14c675c90873e903195b8e20d2070d2eda5ac Reviewed-on: https://chromium-review.googlesource.com/285023 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* Ryu: i2c speed to 1MHzGwendal Grignou2015-07-141-1/+1
| | | | | | | | | | | | | | | | | | To avoid FIFO errors - the fifo becomes full will we wait for the AP to read the vectors, increase the i2c speed between EC and AP. Target 1Mhz, 400KHz observed due to a limitation of the Tegra I2C controller. BRANCH=smaug TEST=Verify with analyzer that speed is now 400KHz. The duty cycle is still not right. Check that FIFO underrun do not happen during tests. BUG=chrome-os-partner:40280,chrome-os-partner:39233,chrome-os-partner:39900 Change-Id: Id6c2dfb10c34a919ec99a58bc0082207f7748b7e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284613 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Cr50: Restore spstest commandBill Richardson2015-07-144-0/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I accidentally removed this when poking around with the SPS driver. This adds it back as a separate file. Enabling CONFIG_SPS_TEST will restore the "spstest" console command to use for low-level driver tests. Note that invoking it will replace any other registered SPS handler. BUG=chrome-os-partner:40969 BRANCH=none TEST=manual Connect the EC to the build host with an FTDI USB-to-SPI adapter. On the EC console, invoke spstest Build and run the external ftdi_dongle test: git clone sso://user/vbendeb/ftdi_dongle cd ftdi_dongle/src make ./examples/spiraw.py -l 10 -f 2000000 Change-Id: Ia6165e3be06d976c59c3e849349da0f7f5006f56 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284943 Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* mec1322: Fix reset cause detectionDivya Jyothi2015-07-133-48/+11
| | | | | | | | | | | | | | | | | | | | | | | Mec1322 cannot distinguish between Power-on and reset condition. MEC1322_EC_WDT_CNT was used to determine the power-on condition. VBAT_POR cannot not be used to distinguish no battery condition. All of the feautures that need support need to determine VCC1_REST which is used for reset considion. lfw and main code use the same condition. When VCC1_RESET is asserted we need to set the image type to RO image for sysjump to work correctly. This in turn will affect Recovery mode,software sync and Flashrom. All of these conditions were tested with this patch. BUG=chrome-os-partner:40526 TEST=Recovery mode,Software Sync,Flashrom BRANCH=None Change-Id: I65f2aa9f56863597116b875ea436d4413887b92b Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283605 Reviewed-by: Shawn N <shawnn@chromium.org>
* Cr50: Pass SPI and SPS modes to sps_register_rx_handler()Bill Richardson2015-07-133-21/+36
| | | | | | | | | | | | | | | | | | | This lets the RX interrupt handler configure the wire protocol (clock polarity and phase) and SPS communication mode that it would prefer. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall This is just a refactoring, since the sps_hc.c module is the only thing that uses this (in one mode only). I tested it using extra/ftdi_hostcmd and it still works. Change-Id: I9ed26e9fa66de65e72f188184f4f3f41a5b5562a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284922 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: cleanup: Rename the "sps" console command "spshc"Bill Richardson2015-07-131-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "sps" console command declared in sps_hc.c is misleading. It shouldn't be "sps", when it's actually part of the host command protocol stuff. This CL changes the command name to "spshc" instead. The command just enables or disables SPS host commands. Note that because there's no notification if something else calls sps_unregister_rx_handler(), there's no way for the sps_hc.c module to know whether it's still registered. BUG=none BRANCH=none TEST=make buildall Using a test program, such as extra/ftdi_hostcmd/, I can send host commands to an EC attached via an FTDI USB-to-SPI adapter. On the EC console, this: spshc off causes the test program to fail, and this: spshc causes it to work again. Change-Id: Ie0edbde179b570f170ff9464313e5e33ab985f21 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284942 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Clear the TX FIFO when the SPS CS deassertsBill Richardson2015-07-112-9/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the SPI slave chip select is deasserted, it means that the SPI master doesn't want to hear any more from the EC. We need to clear any bytes left in the TX FIFO, so that the next SPI transaction doesn't send those leftover bytes out. Since the EC's SPI protocol for host commands uses software flow control, those leftover bytes could screw up the messages. I expanded a comment explaining how that works. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall And, with the EC connected to the build host via an FTDI USB-to-SPI adapater, I used the extra/sps_errs/ test program to see the original problem and that this CL fixed it: cd extra/sps_errs make ./prog -v ./prog -v -c 22 ./prog -v This sends a complete EC_CMD_HELLO message, then a truncated message, then sends the whole message. Before this change to sps.c, the third message response begins with the leftover bytes from the aborted second message. Bad third message: Transfer(12) => 03 64 01 00 00 00 04 00 a5 a5 a5 a5 Transfer(12) <= a9 a8 a7 a6 f8 f8 f8 f8 f8 f8 f9 f9 ^^ ^^ ^^ ^^ Good third message: Transfer(12) => 03 64 01 00 00 00 04 00 a5 a5 a5 a5 Transfer(12) <= f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f9 f9 ^^ ^^ ^^ ^^ Change-Id: Id6e431f91be0204921edee2f774b6c487966ddff Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284746 Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* Cr50: Handle 11-bit SPS FIFO pointers correctlyBill Richardson2015-07-101-30/+52
| | | | | | | | | | | | | | | | | The SPS module uses mirroring for the buffer management (see https://en.wikipedia.org/wiki/Circular_buffer#Mirroring). This just tweaks the logic to handle that correctly. BUG=b:20894690 BRANCH=none TEST=make buildall Also tested with extra/ftdi_hostcmd Change-Id: Icb9593b71fd3c745bd333c7ee1a9492fab022e1f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283902 Reviewed-by: Sheng-liang Song <ssl@chromium.org>
* flash_ec: move openocd configs from chip/ to util/Myles Watson2015-07-097-288/+0
| | | | | | | | | | | | | | Avoid duplicating servo configurations for every chip. BRANCH=none BUG=chrome-os-partner:22990 TEST=None. This is an intermediate step to make it clear what's happening. CQ-DEPEND=CL:273950 Change-Id: I448543b6ab9d39423955e8d2589b6035c59e838a Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273906 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Implement host commands over SPI busBill Richardson2015-07-082-0/+297
| | | | | | | | | | | | | | | | | This adds a module that attaches to the SPS driver to process host commands delivered over the SPI slave interface. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall This feature is not yet enabled, so there's nothing new to test. That will come next. Change-Id: If57a6fce698a7eb050e2a68b7f4d18d8b0e2956f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/284010 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix stack overflow exception in host-command task.Chiranjeevi Rapolu2015-07-081-0/+1
| | | | | | | | | | | | | | | | Increase host-command task stack size by 128 to avoid stack overflow exception. BRANCH=None BUG=chrome-os-partner:42071 TEST=Test for general functionality and confirm that no stack overflow happens. Change-Id: I5513dbca84cf556357c25cddbcde00e0db6d271b Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282810 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* it8380dev: add flash module and fix system jumpDino Li2015-07-085-12/+820
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add flash control module for emulation board. 2. Fix system jump for Andes core. 3. Change the physical size of the flash on the chip to 256KB. note: 1. Only IT839x series supports flash write protect by registers. 2. Static DMA method of flash code only for IT839x series and IT838x Dx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command flashwp and flashinfo 1-a. flashwp enable 1-b. WP asserted and reboot 1-c. flashinfo RO protected now 1-d. WP deasserted and reboot 1-e. No protected 1-f. flashwp disable 1-g. WP asserted and reboot 1-h. No protected 2. console sysjump and sysinfo 2-a. sysjump rw 2-b. jumping to image RW 2-c. sysinfo, Copy : RW, Jumped : yes 2-d. sysjump ro 2-e. jumping to image RO 2-f. sysinfo, Copy : RO, Jumped : yes 3. RO/RW firmware image test 3-a. sysjump rw 3-b. use console command "eflash" to erase RO region, erase OK and system still work. 3-c. reflash firmware 3-d. sysjump rw, sysjump ro 3-e. use console command "eflash" to erase RW region, erase OK and system still work. Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8 Reviewed-on: https://chromium-review.googlesource.com/271390 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* Cr50: Simplify the API for the SPS driverBill Richardson2015-07-073-322/+155
| | | | | | | | | | | | | | | | | | | | | | The SPS (SPI Slave) driver handles incoming traffic from the SPI master. This abstracts the basic hardware functions into a clean API so that the response to the SPI bytes can be put into separate files. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall If CONFIG_SPI is not defined, incoming SPI traffic is completely ignored. Even when it's enabled, nothing is reacting to the traffic so incoming SPI bytes return 0xFF bytes to the master (SPI traffic is always bidirectional). Change-Id: I9bbcebc9c5223b942362200fe43a11ac57dfff40 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283581 Reviewed-by: Sheng-liang Song <ssl@chromium.org>
* cr50: cleanup a few strings & messagesBill Richardson2015-07-012-3/+4
| | | | | | | | | | | | | | Add a description for the USB HID interface, neaten a bit of console output. No new functionality. BUG=none BRANCH=none TEST=make buildall Change-Id: Ie85a0192bc4ab9fa87afb4be41d496545a3b548a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/283051 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: protect spi_transcation() with mutexAndrey Petrov2015-07-012-2/+17
| | | | | | | | | | | | | | | | | | Concurrent SPI transactions are not possible, however in case of external SPI and flashrom update scenario both host command and vhash trigger transactions. This adds mutex for the SPI transcation BRANCH=None BUG=chrome-os-partner:38103 TEST=on Cyan, run hundreds of flashrom cycles to make sure there are no read, erase or write errors Change-Id: If346ebe635387d477dcea5f406a5c31579142e2d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282113 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* mec1322: correct reset cause state in lfwDivya Jyothi2015-07-011-5/+12
| | | | | | | | | | | | | | | | | | Reset cause was recorded / corrected only in RO/RW images. lfw still has old implementation.This caused sysjump RO/RW to not jump appropriately. BRANCH=None BUG=chrome-os-partner:38103 TEST=on Cyan,sysjump RO and sysjump RW console commands nd make sure it jumps to the right image. Change-Id: I37138f552fdd385c98d770d242d896ffc014697c Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282210 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* mec1322: reload watchdog on LFW entryAndrey Petrov2015-07-011-0/+9
| | | | | | | | | | | | | | | | | | When RO/RW sysjump is made watchdog is not disabled. Since LFW needs to load firmware image into SRAM over SPI, there is a certain chance watchdog counter will fire in the middle of it. BRANCH=None BUG=chrome-os-partner:38103 TEST=on Cyan, run hundreds of flashrom cycles and make sure there is no watchdog reset Change-Id: Idafcc6a1c9fb35f04be398a68e3ec05bb2b1425d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282112 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* mec1322: fix flash_physical_read()Andrey Petrov2015-07-013-18/+6
| | | | | | | | | | | | | | | | | | | | | | | flashrom on target issues a salvo of flash read commands with small buffer size (128 bytes). Since there is no yield this starves other tasks/events including hooks and as result watchdog is never reloaded. This change makes read function yield to other tasks. In addition, spi_enable()/disable chaining leads to situations where a SPI can be disabled in the middle of transcation. This is addressed by keeping SPI permanently enabled in LFW entry function, as well as in RW/RO early init functions. BRANCH=None BUG=chrome-os-partner:38103 TEST=manual on Cyan, run flashrom -p ec -w xx in cycles, swaping xx so that flashrom does flash. Make sure there is no watchdog triggered Change-Id: Id5c50239a1d5c64054d7c660dd03b2be4678221c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282111 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* STM32 PWM: Add error case in conditional compilationAnton Staaf2015-06-301-1/+3
| | | | | | | | | | | | | | | | | | | Ensure that a new chip doesn't default to one of the possible alternate function selection schemes, requiring it to pick one or implement something new. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I3650fa0c99bbf541039a778f4d6398f0a549f1b2 Reviewed-on: https://chromium-review.googlesource.com/282601 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* STM32F: Remove support for this familyAnton Staaf2015-06-3020-2024/+478
| | | | | | | | | | | | | | | | | | There are no boards left that use this family of STM32 parts. If we add one later we can resurect support. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: If985a9e9f93c935e98c93f33c075ce00cb9a91ac Reviewed-on: https://chromium-review.googlesource.com/282532 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* it8380dev: add pin 3.3v/1.8v selectionDino Li2015-06-303-2/+100
| | | | | | | | | | | | | | | | | | | add GPIO_SEL_1P8V flag for 1.8v/3.3v selection. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. To configure 1.8V/3.3V pin to 1.8V, set GPIO_SEL_1P8V flag in gpio.inc. 2. The corresponding bit will be set as default value if the pin is not listed in gpio.inc. Change-Id: Ica02aabe40b83fcb4d33bd28d717a0633bdef5f3 Reviewed-on: https://chromium-review.googlesource.com/281842 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add i2c control moduleDino Li2015-06-309-17/+546
| | | | | | | | | | | | | | | | | | | | Add i2c control module for emulation board. To rename CONFIG_ to CONFIG_IT83XX_ for IT83XX series configuration. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command "i2cscan" found devices correctly. 2. console command "i2cxfer". 2-a. port2 + battery, i2cxfer r, r16, and rlen OK. 2-b. port1 + slave evb, i2cxfer r, r16, rlen, w, and w16 OK. Change-Id: I67165f7dcdef538ba6dd03b47f1621a73cc68379 Reviewed-on: https://chromium-review.googlesource.com/263678 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* nuc: Add SHI driver for arm-based platform in chip folder.Ian Chao2015-06-2625-655/+1709
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* Fix assertion crash in __wait_evt()Chiranjeevi Rapolu2015-06-254-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() is called from MEC1322_IRQ_ACPIEC0_IBF interrupt context, causing deadlock and assertion in __wait_evt(). In the interrupt context it now checks for mutex lock first. If the mutex is already locked,, it will disable ACPI interrupts and defer the memmap mutex lock. Added LPC interrupt disable/enable functions as needed. Increased deferred function count where needed. BRANCH=None BUG=chrome-os-partner:40820 TEST=Test for suspend-resume, cold, warm reboots and other general stability. Change-Id: I3dda0d4635a6b6281faf200c8c7b6fcba8877254 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/280418 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* it8380dev: add fan control moduleDino Li2015-06-257-25/+855
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. pwm, add frequency select function for pwm channels. 2. timer, add external timer 3~8 apis. 3. add fan control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console command "faninfo, fanset, fanduty, and fanauto" fanset 3333 Setting fan 0 rpm target to 3333 faninfo Actual: 3390 rpm Target: 3333 rpm Duty: 35% Status: 1 (changing) Mode: rpm Auto: no Enable: yes faninfo Actual: 3301 rpm Target: 3333 rpm Duty: 34% Status: 2 (locked) Mode: rpm Auto: no Enable: yes fanduty 80 Setting fan 0 duty cycle to 80% faninfo Actual: 5952 rpm Target: 3333 rpm Duty: 80% Status: 2 (locked) Mode: duty Auto: no Enable: yes faninfo Actual: 5971 rpm Target: 3333 rpm Duty: 80% Status: 2 (locked) Mode: duty Auto: no Enable: yes fanauto faninfo Actual: 3330 rpm Target: 3333 rpm Duty: 36% Status: 2 (locked) Mode: rpm Auto: yes Enable: yes fanset 8000 Setting fan 0 rpm target to 8000 faninfo Actual: 6793 rpm Target: 8000 rpm Duty: 100% Status: 3 (frustrated) Mode: rpm Auto: no Enable: yes fanset 3456 Setting fan 0 rpm target to 3456 faninfo Actual: 5053 rpm Target: 3456 rpm Duty: 56% Status: 1 (changing) Mode: rpm Auto: no Enable: yes faninfo Actual: 3440 rpm Target: 3456 rpm Duty: 34% Status: 2 (locked) Mode: rpm Auto: no Enable: yes /* force stop the fan */ [87.035136 Fan 0 stalled!] [87.035520 event set 0x00000400] [88.035712 Fan 0 stalled!] [89.036288 Fan 0 stalled!] [90.036864 Fan 0 stalled!] [91.037440 Fan 0 stalled!] [92.038016 Fan 0 stalled!] [93.038592 Fan 0 stalled!] [94.039168 Fan 0 stalled!] /* release */ faninfo Actual: 3427 rpm Target: 3456 rpm Duty: 35% Status: 2 (locked) Mode: rpm Auto: no Enable: yes Change-Id: Icbe1917902d033a8be42b8d834ffc6045d08b985 Reviewed-on: https://chromium-review.googlesource.com/266625 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add peci control modulestabilize-7204.BDino Li2015-06-247-3/+489
| | | | | | | | | | | | | | | | | | | Add peci control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command "pecitemp" get CPU temperature normally. 2. console command "peci" manual test peci commands. (GetDIB, GetTemp, RdPkgConfig, and WrPkgConfig) Change-Id: I48b63a391adf04f159adca401acb369a6acc3799 Reviewed-on: https://chromium-review.googlesource.com/265171 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* mec1322: Correctly get reset causeDivya Jyothi2015-06-242-2/+25
| | | | | | | | | | | | | | | | | | Since the reset cause was not recorded correctly recovery mode(Esc+Refresh+Power) was not working. With this change power-on reset state and VCC1_RST# only state are distinguinshed. BUG=chrome-os-partner:41479 BRANCH=none TEST=Esc+Refresh+Power boots to recovery screen Refresh+Power reboots the system Change-Id: I63eff488c970302e7afe8a677a57ad27d4d9918e Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://chromium-review.googlesource.com/280782 Reviewed-by: Shawn N <shawnn@chromium.org>
* it8380dev: add sspi control moduleDino Li2015-06-234-1/+168
| | | | | | | | | | | | | | | | | | | | | | | | Add sspi control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EVB + Winbond W25Q80 SPI ROM To define CONFIG_SPI_FLASH, CONFIG_SPI_FLASH_SIZE, and CONFIG_SPI_FLASH_W25X40 console "spi_flashinfo" can get SPI information > spi_flashinfo Manufacturer ID: ef Device ID: 40 14 Unique ID: c8 60 84 a1 1f 6a 7f 2f Capacity: 1024 MB Change-Id: I6c4d4d977536484d47a2207ed80dd0ea08a7c8fd Reviewed-on: https://chromium-review.googlesource.com/267403 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* cleanup: fix all the header guardsBill Richardson2015-06-1827-80/+80
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash_ec: remove unused USB and unprotect optionsMyles Watson2015-06-181-15/+0
| | | | | | | | | | | | | | There is no need for the usb flag, remove it. There is no need for the unprotect flag, remove it. BRANCH=none BUG=chrome-os-partner:22990 TEST=run flash_ec before and after Change-Id: I201bad7f5be63a90bb8168e21baef2c6fa8d85b4 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273904 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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