| Commit message (Collapse) | Author | Age | Files | Lines |
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clang warns that the types do not match:
chip/ish/host_command_heci.c:140:9: error: implicit conversion from
enumeration type 'enum ec_error_list' to different enumeration type
'enum ec_status' [-Werror,-Wenum-conversion]
return EC_SUCCESS;
BRANCH=none
BUG=b:172020503
TEST=none
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ief6c5ecb4a6850a5560357f6f9c7cb7c5bd22797
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3193272
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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"test_mockable_static" is static, but the declaration created by
DECLARE_IRQ is not static. The mismatch generates a compiler warning
when building with clang:
chip/stm32/clock-f.c:325:6: error: unused function '__rtc_alarm_irq'
[-Werror,-Wunused-function]
void __rtc_alarm_irq(void)
BRANCH=none
BUG=b:172020503
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I39e2de93b057b5565c54ffb83e1633a13db1ce46
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172039
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478, b:200642229
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
TEST=jump to RW & check sysinfo after reset-pin/watchdog/debug reset
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I9801efe7fe7645e7b81df9c5cc69372df0a178a8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3178700
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Yuval Peress <peress@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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We are already disabling -Wignored-attributes to work around the
declaration and definition order issue:
error: attribute declaration must precede
definition [-Werror,-Wignored-attributes]
However, although there are no compiler errors, the linker (lld) will
still fail:
ld.lld: error: undefined symbol: clock_control_irq
>>> referenced by clock.c:347
(src/platform/ec/chip/mt_scp/mt8183/clock.c:347)
>>> lto.tmp:(irq_13_handler)
...
ld.lld: error: undefined symbol: clock_fast_wakeup_irq
>>> referenced by clock.c:355
(src/platform/ec/chip/mt_scp/mt8183/clock.c:355)
>>> lto.tmp:(irq_44_handler)
Tested with the compare_build.sh script to validate that the resulting
binaries are identical.
BRANCH=none
BUG=b:172020503
TEST=CC=arm-none-eabi-clang make BOARD=kukui_scp -j
TEST=./util/compare_build.sh --boards all -j 50
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ib622fb98784a4c3ad3c199c72ee7604c7f709d6c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3182621
Reviewed-by: Diana Z <dzigterman@chromium.org>
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We change event timer's clock to 32.768kHz before entering low power
mode. And will restore the clock to 8MHz (by checking PLL control
register's setting in ISR) when chip wake up from the low power mode.
So we need to ensure the setting is taken into PLL control register
before wfi instruction. The original implementation can't ensure event
timer’s clock is restored to 8MHz when chip wake up. So we fix it.
This also fix wfi (wait for interrupt) instruction fail issue on RISV-V
core chips when a timer count down to zero (MTIP@mip is set to 1 until
HW reload timer counter).
Once CPU executed wfi instruction, CPU should stay there until interrupt
is fired or MEIP@mip is non-zero. But currently, HW checks entire mip
value (should check MEIP@mip only) to decide whether or not to ignore
wfi instruction.
The issue will cause EC premature wake from idle task even there is no
interrupt fired.
BRANCH=asurada, icarus
BUG=none
TEST=-On asurada, increase CPU clock to 96mhz.
Plug out/in type-c adapter to wake chip up from low power mode,
no pre-watchdog warning fired. (x100)
-buildall
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I72bb2566c5b22bc132ab304a38a5a1b5b968e463
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3168672
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
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This implements missing I2C driver functions to get or set the I2C bus
speed on NPCX family chips.
BRANCH=none
BUG=b:201039003
TEST=with follow-on patches, switched I2C bus speed between 400 kHz
and 1 MHz.
Change-Id: Ie0d8de1ca2c4884e52f5fe947ad19a50b0c76fb9
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3170292
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This adds code to the npcx I2C driver to keep track of the speed setting
used to configure the port. This can be used to determine the current
speed setting without decoding chip registers.
BRANCH=none
BUG=b:201039003
TEST=with follow-on patches, switched I2C bus speed between 400 kHz
and 1 MHz.
Change-Id: Ib7a61e23ec406deff80afead2e2aa6b64578ea1d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3181502
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BRANCH=none
BUG=b:201039003
TEST=buildall passes
Change-Id: I5b34e5266f28452d30d76489e4afaef4cb2287e2
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3181501
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This splits the implementation of i2c_freq_changed() into a per-port
worker function and a top-level iterator function. This change makes
i2c_port_set_freq() available to set a port's I2C speed.
BRANCH=none
BUG=b:201039003
TEST=with follow-on patches, switched I2C bus speed between 400 kHz
and 1 MHz.
Change-Id: Ifb5613ac3a59cbd64f01f3a396f978db5e77d9f1
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3170291
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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clang complains that the types do not match:
chip/mt_scp/mt8183/ipi.c:349:9: error: implicit conversion from
enumeration type 'enum ec_error_list' to different enumeration type
'enum ec_status' [-Werror,-Wenum-conversion]
BRANCH=none
BUG=b:172020503
TEST=make buildall -j
TEST=CC=arm-none-eabi-clang make BOARD=kukui_scp -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I14e850f5e2ace5c3f3e59c7bc2aa90b3eaf92a9d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3182620
Reviewed-by: Edward Hill <ecgh@chromium.org>
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This reverts commit 20222d48571fa44c76fdb0ededd0ed042e9f8244.
Reason for revert: brya thinks it's in EC-RW when it's really still in EC-RO.
Original change's description:
> npcx: correct the image copies indication bits for npcx9
>
> In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
> of the MDC register) to indicate what the current image copy is.
> In npcx9, these two bits are used by the booter. We need to change them
> to another two empty scratch bits which are not used by the booter.
>
> BUG=b:165777478
> BRANCH=none
> TEST=pass "make buildall"
> TEST=check the related bits changed by "sysump ro" and "sysjump rw"
>
> Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
> Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
> Tested-by: CH Lin <chlin56@nuvoton.com>
> Reviewed-by: caveh jalali <caveh@chromium.org>
> Auto-Submit: CH Lin <chlin56@nuvoton.com>
> Commit-Queue: caveh jalali <caveh@chromium.org>
Bug: b:165777478
Change-Id: I24cdfec0d5c8cd998f087525ae21b2a3daea43a7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172266
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Tested-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Commit-Queue: caveh jalali <caveh@chromium.org>
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If there is an I/O expander driver for keyboard, there is no need
to enter the keyboard_raw_interrupt().
BUG=b:199337186
BRANCH=none
TEST=make buildall -j4
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change-Id: Ie24f5b5592325a76d9a36a689657bdd2e05c8fb1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3151046
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
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STM32L5 can have up to four UARTs, one more than previous Lx series.
These files were copied from usart-stm32l.{h,c}, modified only by
making one more copy of the appropriate declarations.
BUG=b:192262089
TEST=Compile with hyperdebug board (from later in the chain)
BRANCH=none
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Change-Id: I8bd2d13de67fc74b59c16a79a87fd4615912be09
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3133814
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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The register for enabling USB register clock appears to have been
identical across F0, F3, and G4 families, but for L5 it is
different. Rather than having #ifdef in usb.c (as I recently
committed), this CL will move the clock logic into
clock_enable_module() where it arguably belonged all the time.
Additionally: Some of the chip families make use of a clock_mask in
their implementation of clock_enable_module(), but since the module_id
enum has more than 32 value, until now, some values (among those
MODULE_USB) would result in overflow, causing new_mask to be identical
to clock_mask, and the USB case could have never been reached.
BUG=b:192262089
TEST=Compile servo_v4 without linker errors
BRANCH=none
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Change-Id: I7c29339f45eb513e3e78f662797a70543912c8c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130733
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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Use 32k clock instead of ULPOSC can significantly reduce the power
consumption of SCP under S3 stage, and still able to kick SCP WDT.
BRANCH=none
BUG=b:197937562
TEST=low scp power in S3 stage
Change-Id: If2f68a5b11e93c7e6badf2e4893f649700b5af2e
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3131409
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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This CL read (load operation) an EC's extended interrupt enable register
one time after configured. The load operation will ensure chip-level's
interrupt has been disabled before enabling CPU interrupt.
This CL will also assert failure if EC get interrupt number 0 in ISR.
BRANCH=dedede
BUG=b:197308582
TEST=No system reboot on storo during the drop test.
Change-Id: I593d78626d1e3bb92e5316d1ff78f0ee54711741
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124483
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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This CL read EC's IER one time after configured. The load operation
will ensure chip-level's interrupt has been disabled before enabling
CPU interrupt.
BRANCH=asurada, icarus
BUG=b:179206540
TEST=create stress test on it8xxx2 evb:
- Loop calling task_disable_irq() and task_enable_irq() to
enable and disable IRQ 13 (keyboard KSI interrupt).
- Toggle KSI continuously.
Without the patch, EC will hit IRQ 0 issue in two seconds.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I56bad182bd101d45b00368083b60aabbd9fb8bdb
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139652
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
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Configure interrupt enable register is redundant on nds32 core chip
(IT8320). We just need to configure extended IER.
BRANCH=asurada, dedede
BUG=b:197308582
TEST=buildall passes, storo and hayato boot.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I8f99f7b937ac98d95b2f50f5be7b461ae3e9a413
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3134888
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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The npcx eSPI driver only prints if eSPI_DEBUG is on. Without ESPI_DEBUG,
critical eSPI errors are hidden and it may not be obvious why the
system is failing. This change forces eSPI bus error messages to always
print.
This is inside of an interrupt_handler, so printing too much could
cause other interrupts to be missed. The error message is short and it
did not cause additional errors during testing. Since eSPI bus errors
are often fatal, this risk is acceptable.
BUG=None
TEST=Boot image with known eSPI errors, see error message
Boot with known good image, see no error message
Remove condition, boot good image, eSPI functions normally
BRANCH=None
Change-Id: Ic1431800560091001b73dafcd77362e061323c1a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3111457
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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As a followup to CL:3104290, give the TCPCI TRANSMIT and
RX_BUF_FRAME_TYPE types more consistent names. Most of them can be used
for receiving, not just transmitting. Fix lint errors thus revealed.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: I399ec479eacc18622fc4d3f55f8bdabf4560fcff
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3125995
Reviewed-by: Keith Short <keithshort@chromium.org>
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This reorganizes adc.h and adc_chip.h so that general code only needs to
know about adc.h. adc_chip.h is now included by adc.h directly and does
not need to be included in general code.
BRANCH=none
BUG=b:181271666
TEST=buildall passes (with next patch in series)
Cq-Depend: chromium:3120316
Change-Id: I8bc107c6900e831a57f7a7fb8668eb08bb179d6c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3120315
Reviewed-by: Keith Short <keithshort@chromium.org>
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Introduce L5xx mostly as copy of L4xx, though registers-stm32l5.c is
extensively modified.
BUG=b:192262089
TEST=Compile and upload board/hyperdebug to Nucleo board
BRANCH=none
Signed-off-by: Jes B. Klinke <jbk@opentitan.org>
Change-Id: Iccc7b05e4f2dfa732559b8099cf856882401e31c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3086362
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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This commit moves some of the standard library functions from util.c
file to util_stdlib.c file. It will allow to use util.c for both
CrOS EC and Zephyr builds and will make shim util file unnecessary.
BRANCH=main
BUG=b:177096231
TEST=Build both, CrOS EC and Zephyr firmwares
Compilation should finish without any problems
After flashing, both versions work as they should
Change-Id: If6f930a04d28bec35faa16759f43b36176bf3de7
Signed-off-by: Michał Barnaś <mb@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3081827
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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The current API for system_get_scratchpad mixes the status and the value
being read. Update the signature to allow both.
BRANCH=none
BUG=b:195481980
TEST=make testall && zmake testall
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I3a5f5ad523d507c53a5d474806f58afafb82e70c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074828
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Update RPM-PWM block's registers and configuration as POR, RPM based
Fan Control Algorithm via RPM-PWM hardware block is not supported or
validated in previous mchp projects.
BUG=none
BRANCH=none
TEST=Tested on ADL RVP and MCHP1727 MECC system via UART console
Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: Ibe15dfbec4f2c2d4558d27c8b101345ad81a09f3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3100925
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Fmeter is used to measure the clock speed on SoC.
SCP uses the fmeter with different config compared to kernel side clock
driver.
Restore the fmeter value to prevent wrong fmeter result for clock driver.
BUG=b:184793035
TEST=check fmeter result by following commands
echo 0 > /proc/sys/kernel/printk
clkdbg() { echo $@ > /proc/clkdbg; cat /proc/clkdbg; }
clkdbg set_parent vdec_sel mainpll_d4
clkdbg set_parent venc_sel univpll_d4
clkdbg fmeter
WAS:
64: hf_fvenc_ck : 312000
65: hf_fvdec_ck : 273000
IS:
64: hf_fvenc_ck : 624000
65: hf_fvdec_ck : 546000
Change-Id: If4d93b9b4e05258d0ad5f96953a99fd74acb6070
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063107
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Rename tcpm_transmit_type to tcpm_sop_type to reflect that it can be
used for Rx as well. Describe it in comments. This prepares to
consolidate enum pd_msg_type into this enum.
BUG=b:155476419
TEST=make buildall
BRANCH=none
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Change-Id: Ife97d4ad51c48f2e832b94e007954919e236a309
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3104290
Reviewed-by: Keith Short <keithshort@chromium.org>
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The position of SLEEP_KEY_MASK bit is not in its intended
position because TK_* enum is 1-indexed. Fix this bug by
shift the mask by 1.
BUG=b:196934919
TEST=evtest
BRANCH=trogdor
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I900636f032786510f7870948d1856d0bc4374800
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3097478
Reviewed-by: Rong Chang <rongchang@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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Add define to support irq in scp: VDEC_CAP_IRQ_IN_SCP BIT(16).
BRANCH=none
BUG=b:184793035
TEST=make BOARD=cherry_scp
Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com>
Change-Id: I7d4583f7c4bce07c6fb4f22bd9152edb23fe9e05
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3054225
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
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BRANCH=none
BUG=b:185977882
TEST=make BOARD=asurada_scp -j &&
make BOARD=cherry_scp -j
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: Id5eaa5ddc0e21c9b33a1a4197393de6c6ef331e6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3080541
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Use the hid usage mapping from drivers/hid/hid-input.c:
Page 0xB, Usage 0x2F -> KEY_MICMUTE
Page 0xC, Usage 0x7C -> KEY_KBDILLUMTOGGLE
BUG=b:194460146
TEST=Map the new keys to F1/F2 on homestar, and verify
1) kernal can get the expected key code.
Event: -------------- SYN_REPORT ------------
Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value b002f
Event: type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 1
Event: -------------- SYN_REPORT ------------
Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value b002f
Event: type 1 (EV_KEY), code 248 (KEY_MICMUTE), value 0
Event: -------------- SYN_REPORT ------------
Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value c007c
Event: type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), value 1
Event: -------------- SYN_REPORT ------------
Event: type 4 (EV_MSC), code 4 (MSC_SCAN), value c007c
Event: type 1 (EV_KEY), code 228 (KEY_KBDILLUMTOGGLE), value 0
2) `cat /sys/class/input/*/device/function_row_physmap`
BRANCH=trogdor
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Ibf342b881ee428598adaeb73a63bf242cd220004
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3073440
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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Optimize SPI flash read timing, MEC172x QMSPI controller controls CS#
by hardware, it will add several system clock cycles delay between CS
deassertion to CS assertion at the start of the next transaction, this
guarantees SPI back to back transactions, so 1ms delay can be removed
to optimze timing.
BUG=none
BRANCH=none
TEST=Tested on ADL RVP and MCHP1727 MECC system via FAFT ECBootTime job
save 720ms as EC performs 180KB RW code's SHA256 hash computation
Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: I5cf9c668efb1cd008b91cdd8aa09f7351c017af0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074767
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BRANCH=none
BUG=b:163885307
TEST=compare_build.sh matches
Change-Id: Ifdf9d33f9315e11c0c31a62b08864790b2fcaa5a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069988
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The usb hid driver always send 60 bytes feature report to the host,
this causes host side unhappy because the received data is larger
than expected.
Fix this bug by sending what we actually declared.
BUG=b:195264416
TEST=# cat /sys/class/input/*/device/function_row_physmap
C0224 C0227 C0232 C029F 70046 C0070 C006F C00E2 C00EA C00E9
BRANCH=trogdor
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: I536e4518a76606a05c006d459d6ffbb61858c2d2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066973
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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BRANCH=none
BUG=b:181607131
TEST=compare_build.sh matches
Change-Id: I37dd5c596bf758d4bd6d39f643ff731ff4a567ea
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3069987
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Harry Cutts <hcutts@chromium.org>
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Update SPI host interface config option for inclusive language.
BUG=b:163885307
BRANCH=none
TEST=compare_build.sh
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I808d5960fa3e746626465bedc626a95e0f0aaa3f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066271
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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BRANCH=none
BUG=b:163885307
TEST=compare_build.sh matches
Change-Id: I50d4263e93945ec0f3fd2d655fd173aa8a666d8f
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060261
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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BRANCH=none
BUG=none
TEST=compare_build.sh matches
Change-Id: Idd8bab55d02bafdbab6b0e136326ef47a464dc4c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060259
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: CH Lin <chlin56@nuvoton.com>
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This requests that cros lint (and repo upload hook) use the new
Chromium OS 4 space indent policy.
Since legacy python scripts still use 2 space, I added pylint ignore
statements to the individual files to disable indentation checking.
Note: There are still valid pylint errors in some of these legacy scripts.
BRANCH=none
BUG=none
TEST=cros lint util/*.py
Signed-off-by: Craig Hesling <hesling@chromium.org>
Change-Id: I439f5a87bc50f1f43a4996e574bbc0626922a88e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3064761
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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This renames the ITE chip specific SPI IRQ config from
IT83XX_IRQ_SPI_SLAVE to IT83XX_IRQ_SPI_PERIPHERAL.
BRANCH=none
BUG=b:181607131
TEST=compare_build.sh matches
Change-Id: Ib7a7674e6cf4f0bf81ee47b5f60225f77236f578
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061913
Commit-Queue: Harry Cutts <hcutts@chromium.org>
Reviewed-by: Harry Cutts <hcutts@chromium.org>
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This renames the ITE chip specific SPI speed configuration from
IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE to
IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE.
BRANCH=none
BUG=b:181607131
TEST=compare_build.sh matches
Change-Id: If2fcb086a8c35cf43ce15dc0963f3febbaa25f45
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061912
Commit-Queue: Harry Cutts <hcutts@chromium.org>
Reviewed-by: Harry Cutts <hcutts@chromium.org>
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BRANCH=none
BUG=b:181607131
TEST=compare_build.sh matches
Change-Id: I6f5ac12ff64fe870709dc91bca71e0901bed3420
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061911
Commit-Queue: Harry Cutts <hcutts@chromium.org>
Reviewed-by: Harry Cutts <hcutts@chromium.org>
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BRANCH=none
BUG=b:181607131
TEST=compare_build.sh matches
Change-Id: I045ae5f148fe6233abf921d99f381b2cce6966ad
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060260
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This CL fixes that i2c driver will prompt "I2C chx reset cause 1" issue
when one i2c transaction is separated into at least three i2c_xfer and
I2C_XFER_START flag is set at least two times.
eg.
- i2c_xfer with I2C_XFER_START flag
- i2c_xfer with I2C_XFER_START flag <= this will cause reset
- xxx
- i2c_xfer with I2C_XFER_STOP flag
BRANCH=none
BUG=none
TEST=no i2c reset on Asurada, Drawcia, and ADL-RVP.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I97161db0bb0c54de3ad55d82512a6a188036270f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058724
Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
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NPCX alternate switch function uses the GPIO number to select which
register should be set. Currently, we have a scenario to enable
CONFIG_PS2 & use ADC5(GPIO37) or ADC6(GPIO34) with NPCX9. The
CONFIG_PS2 condition hides the alternate table for ADC5/6. It makes
GPIO37 & GPIO34 are both set to PS2 function.
This CL adds NPCX_PS2_MODULE_2 & NPCX_PS2_MODULE_3 options to assign
PS2 function for alternate pin explicitly.
BUG=none
BRANCH=none
TEST=make buildall
TEST=Enable CONFIG_PS2 & check ADC5/6 functionality.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Id02fb8ecfd488db133351119be84c357dc18da15
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058151
Reviewed-by: caveh jalali <caveh@chromium.org>
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The IRQ triggering frequency of video encode/decode IRQ is propotional
to frame rate. Assign these IRQs with group 8 to prevent blocking IPI
IRQ handler (group 7).
BRANCH=none
BUG=b:189300514
TEST=make BOARD=cherry_scp
Change-Id: Iab7147fbecc02217656bef1493574461ad54cb29
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3010781
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
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BRANCH=none
BUG=b:189300514
TEST=video_decode_accelerator_tests test-25fps.h264
Change-Id: Ia6e777fe7a349586c676b6991643676019598d7a
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3038014
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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BRANCH=none
BUG=b:194047863
TEST=On spherion, no keyboard backlight blinking.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: I847291268720bf12ca98b3e38e29a556ec038cd0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3043075
Tested-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
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Due to increase of RW size, stm32l431 flash layout were change to RO:
124KB, PSTATE: 2KB, RW:130KB
BRANCH=kukui
BUG=b:188117811
TEST=make BOARD=munna; make buidall
Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com>
Change-Id: I8cf2d2dbdc8a2ae5e95d1d54c6672796eb02fc02
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3037292
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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