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* stm32: change stm32l431 flash layoutBossen WU2021-07-202-1/+54
| | | | | | | | | | | | | | | Due to increase of RW size, stm32l431 flash layout were change to RO: 124KB, PSTATE: 2KB, RW:130KB BRANCH=kukui BUG=b:188117811 TEST=make BOARD=munna; make buidall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I8cf2d2dbdc8a2ae5e95d1d54c6672796eb02fc02 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3037292 Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* mchp: Correct integrated SPI flash pins' configurationmartin yan2021-07-141-2/+2
| | | | | | | | | | | | | | | | | | | Corrected MEC1727 integrated SPI flash CS# (GPIO116) and CLK (GPIO117) alternative function as 1 (Internal SPI functionality) from 2 (General purpose SPI functionality). BUG=none BRANCH=none TEST=Tested on ADL RVP via EC UART console > sysjump RW: able to switch to RW from RO > sysjump RO: able to switch to RO from RW Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: I870925183e670022dc023812265a7ef496b5f255 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3021101 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* chip/mt_scp: add mt8195 irq supportTinghan Shen2021-07-134-113/+451
| | | | | | | | | | | | | | | | | Update IRQ definition for mt8195 and move IRQ definitions to chip-specific folder. BRANCH=none BUG=b:189300514 TEST=make BOARD=asurada_scp && make BOARD=cherry_scp Change-Id: I3bb4d97e374328fbe86d537b14cce11322365c10 Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2940337 Tested-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* chip/mt_scp: change uart clock to ULPOSCTinghan Shen2021-07-131-1/+1
| | | | | | | | | | | | | | | | Change UART clock to ULPOSC to keep SCP console alive when system suspend. BRANCH=none BUG=b:189300514 TEST=make BOARD=cherry_scp Change-Id: I144354fe946808c7ec68da4ea33e4ad11a7bf11f Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3003345 Tested-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* chip/mt_scp: support mt8195 clockTinghan Shen2021-07-139-98/+622
| | | | | | | | | | | | | | | | | | Supports mt8195 clock and move chip-specific clock registers from common to chip-specific. BRANCH=none BUG=b:189300514 TEST=make BOARD=asurada_scp && make BOARD=cherry_scp Change-Id: I8ef058f6314652050dead46e7f48d3420bbdd1d1 Signed-off-by: Roger Lu <roger.lu@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939167 Tested-by: tinghan shen <tinghan.shen@mediatek.com> Tested-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* driver/tcpm/ite_pd_intc: separate pd interrupt to ite_pd_intcRuibin Chang2021-07-091-78/+1
| | | | | | | | | | | | | | | | | Separate pd interrupt functions to ite_pd_intc for easier maintenance on cros_ec and zephyr. And enable PD interrupt functions for zephyr. BRANCH=none BUG=none TEST=1.can zmake hayato and make asurada 2.PD port functions work on board hayato Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Change-Id: I67082bb442da7dfb669e23d8315d81f4abe7ba76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999358 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* stm32: clock: avoid division by zero worries.Bossen WU2021-07-021-4/+4
| | | | | | | | | | | | | | | In chip_config.h, PLLM / PLLN / PLLR was predefined as 0. It raise concern that frequency calculation would have division by zero issue. Redefine PLLM / PLLN / PLLR as 1 to remove such worry. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: If57aa40af29e0176762a981bd5b2dac9528b1144 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999412 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : flashBossen WU2021-07-012-7/+44
| | | | | | | | | | | | | | | stm32l431 related driver: flash-stm32g4-l4.c system.c The stm32l476g-eval is the only board which would be possibly impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I273954c75651b20de58db53eba7e7d0e4553763d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2978652 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : adcBossen WU2021-07-012-1/+258
| | | | | | | | | | | | | | stm32l431 related driver: adc-stm32l4.c adc_chip.h The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I0ce73ee9ab02e1cfd20a178628d935d24a1907ce Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975521 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : dmaBossen WU2021-07-011-6/+29
| | | | | | | | | | | | | | stm32l431 related driver: dma The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: Ia513875963c2c65f6b63605fc113f139656a4028 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975520 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : i2cBossen WU2021-07-011-19/+25
| | | | | | | | | | | | | | | stm32l431 related driver: i2c-stm32l4 The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: If6187e6f3c2f82ab118524444c1849108bb82f82 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975519 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* mchp: Correct assigning I2C controller to a portVijay Hiremath2021-06-302-3/+15
| | | | | | | | | | | | | | | | | | Corrected default assignment of controller to I2C port based on the number of I2C ports being used rather than the port in use. This avoids overlapping of I2C controller assignment when the I2C ports used are not greater than MCHP_I2C_CTRL_MAX. BUG=none BRANCH=none TEST=Tested on ADLRVP, default I2C controller assignment is correct. Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Change-Id: I875b0f7e94162f923325e9ed07e7549cc760fdf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2980432 Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Move I2C_CONTROLLER_COUNT and I2C_PORT_COUNT to chipmartin yan2021-06-302-0/+8
| | | | | | | | | | | | | | | | | | Move I2C_CONTROLLER_COUNT and I2C_PORT_COUNT to registers-mec172x.h and registers-mec152x.h from board.h, both are chip specific BRANCH=none BUG=none TEST=Tested adlrvpp_mchp1727 and sklrvp_mchp1723 adlrvpp_mchp1521 and sklrvp_mchp Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Icd91e9877e0053c83c1a73d10470ffefedd90a01 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2982390 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* stm32: add stm32l431 ec in chip/stm32 : uartBossen WU2021-06-301-4/+28
| | | | | | | | | | | | | | | stm32l431 related driver: uart The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I861d1cf38430d6b1b5d7c09bd565d727961a4128 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975168 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : watchdogBossen WU2021-06-301-1/+30
| | | | | | | | | | | | | | stm32l431 related driver: watchdog. The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: I8488a3bfad31dadedc65078d29c117cfb2308f77 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2975160 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32: add stm32l431 ec in chip/stm32 : system / clock / timerBossen WU2021-06-307-498/+2575
| | | | | | | | | | | | | | stm32l431 related driver: system / clock / timer. The stm32l476g-eval is the only board which would be impacted. BRANCH=main BUG=b:188117811 TEST=make buildall Signed-off-by: Bossen WU <bossen.wu@stmicro.corp-partner.google.com> Change-Id: Idf335005d8188f6959835aa40179a6bd771c5114 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905165 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* chip/mt_scp: support MT8195 UARTTzung-Bi Shih2021-06-292-0/+10
| | | | | | | | | | | | | Supports MT8195 UART. BRANCH=none BUG=b:189300514 TEST=make BOARD=cherry_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I948e0208f664de72de027357d4ba7336715e92fa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993789 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* chip/mt_scp: move UART pinmux settings to chip specificTzung-Bi Shih2021-06-296-11/+67
| | | | | | | | | | | | | | | | The pinmux setting is chip-specific. Turns the common code into chip-specific. BRANCH=none BUG=b:191835814 BUG=b:189300514 TEST=make BOARD=asurada_scp && make BOARD=cherry_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I22b8171f42025f294392b0bf1a25a4153eb648f7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993788 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* stm32: rename CONFIG_STM32_SPI1_MASTER to …CONTROLLERHarry Cutts2021-06-252-9/+9
| | | | | | | | | | | | | In line with OSHWA terminology. BUG=b:181607131 TEST=make -j BOARD=hammer BRANCH=none Change-Id: I6d212e60d5aceb8497f00520b693006cc1af2d45 Signed-off-by: Harry Cutts <hcutts@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2981123 Reviewed-by: caveh jalali <caveh@chromium.org>
* chip/mt_scp: move rv32i specific to common folderTzung-Bi Shih2021-06-2525-30/+39
| | | | | | | | | | | | | BRANCH=none BUG=b:191835814 TEST=make BOARD=asurada_scp && make BOARD=cherry_scp && make BOARD=kukui_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I35e9fd5f7d3e83d35d09a093be09b194c821f63e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2985060 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* chip/mt8192_scp: fix unknown type errorsTzung-Bi Shih2021-06-251-0/+2
| | | | | | | | | | | | | | | Fixes unknown type errors such as: chip/mt8192_scp/ipi_chip.h:40:2: error: unknown type name 'uint32_t' uint32_t signaled; BRANCH=none BUG=b:191835814 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: If6f0f94540e099e547d7015e82bb4dacb88ebd3b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2985059 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* chip/mt_scp: move mt8183 specific to sub-folderTzung-Bi Shih2021-06-2519-83/+108
| | | | | | | | | | | BRANCH=none BUG=b:191835814 TEST=make BOARD=kukui_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ic8387200a741a4e7ef99e13772231a0ec0bc1fc1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2984255 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* chip/mt_scp: remove unnecessary path when includingTzung-Bi Shih2021-06-251-1/+1
| | | | | | | | | | | BRANCH=none BUG=b:191835814 TEST=make BOARD=kukui_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: If269a412af3e6455672a3d3f5de3e5fe1e4a63d0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2984253 Reviewed-by: Eric Yilun Lin <yllin@google.com>
* Fix compilation issues with nocturne SDKPatryk Duda2021-06-171-1/+2
| | | | | | | | | | | | | | | | | | | | | Compiler in nocturne cros SDK doesn't allow for variable declaration inside for loop. This patch removes variable declaration inside for loop in code which is used by nocturne board. This patch doesn't introduce any logical changes. BUG=b:160676144 BRANCH=none TEST=Make sure EC points to commit on cros/main. On nocturne SDK: cros_workon-nocturne start chromeos-ec emerge-nocturne chromeos-ec chromeos-bootimage Make sure that firmware compiles Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I75ff21d966d5e353d1f7873695127bac4357fb32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2965922 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* ish/heci: initialize msg.payload before using itPatrick Georgi2021-06-171-1/+1
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=one class of error less with gcc 11 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Change-Id: I7c0d2b28ae7805b390e485ff69ec0f6c2a7d5e98 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2959919 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
* mchp: Add ADC MAX reading value for MEC172xmartin yan2021-06-101-0/+5
| | | | | | | | | | | | | | | | | | | Update ADC_READ_MAX for MEC172x, its ADC is 12BIT resolution in default BRANCH=none BUG=b:190518298 TEST=Tested on ADL RVP via UART console > temps Ambient : 300 K = 27 C 34% DDR : 299 K = 26 C 31% Skin : 301 K = 28 C 37% VR : 297 K = 24 C 25% Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: If657d79d989b017fb34df437e28ceed291c9e1d3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2935558 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Update stack size MACROsmartin yan2021-06-101-5/+6
| | | | | | | | | | | | | | | | add ULTRA_TASK_STACK_SIZE and TRENTA_TASK_STACK_SIZE for PD tasks which requires larger stack size, and reduce other stack sizes which were configured for development purpose BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Ib055253a9a8e45da46b81f8f1ea2e60a8f738484 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2945630 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32/system: Disable caches before rebootPatryk Duda2021-06-101-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards (only STM32H7): - nocturne_fp (dartmonkey) - nucleo-h743zi This fixes problem with jumping to RW when reboot to RO was requested. Log from reproduction on dartmonkey (only relevant parts): --- UART initialized after reboot --- [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft ap-off] ... [1.045743 Jumping to image RW] *** We are in RW. Jump data are initialized and contains correct *** set of reset flags. Reset flags from backup RAM are cleared. reset flags from chip: unknown reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RW, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] ... > > reboot ro reboot ro Rebooting! *** Now we are in RO. RW saved reset cause in backup RAM (with *** stay-in-ro). Please note that RO also finds jump data and *** report that was sysjump! reset flags from chip: reset-pin power-on soft ap-off stay-in-ro reset flags from jump data: reset-pin power-on soft sysjump ap-off [1.056198 UART initialized after sysjump] [Image: RO, dartmonkey_v2.0.8961+9a30ce07ee] [Reset cause: reset-pin power-on soft sysjump ap-off] When RO is doing sysjump to RW, jump data structure is created in jump_to_image() function. The structure contains information about reset flags. When RW finds jump data in system_common_pre_init() magic field of the structure is set to zero to prevent detecting sysjump accidentally. Nevertheless, when reboot to RO is requested, RO is able to find the structure. As a result, correct reset flags from backup RAM are overwritten by incorrect reset flags from jump data. This happens because we are not flushing D-cache before reboot. All changes in RW which lives in cache (not saved in RAM) will be lost after reboot because cache is always disabled (even if it was previously enabled and we didn't turned it off). To enable cache we need to invalidate it first (see cpu_enable_caches()). Issue reproduces also with debugger connected, except situation when watchpoint is set on jump data magic field. BUG=b:170432597 b:188934337 BRANCH=none TEST=Compile dartmonkey firmware and run it on eg. icetower. In RW, issue 'reboot ro'. Make sure that jump to RO is not performed. TEST=Run flash_write_protect hardware unit test on icetower board using `./test/run_device_tests.py --board dartmonkey \ --tests flash_write_protect` Make sure that after reboot to RO, 'stay-in-ro' reset cause is printed Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: If56153a1a3ac7ae05700eac9ca60e398cf35f182 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922145 Reviewed-by: Craig Hesling <hesling@chromium.org>
* it8xxx2/spi: re-init spi module after disable emmc boot modeDino Li2021-06-101-0/+17
| | | | | | | | | | | | | | | | This CL reset and re-initialize SPI module after AP jumped to BL. So EC will have a good state to start receiving AP's commands. BRANCH=icarus BUG=b:184702635 TEST=on cozmo, confirm that EC doesn't miss the first command from AP after booting. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ib7cf0e9cb70a67950d53d3abc7df42969c9b4dc2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947422 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* stm32f4: undef CONFIG_CMD_CHARGENNamyoon Woo2021-06-101-0/+2
| | | | | | | | | | | | | | | | This patch excludes CONFIG_CMD_CHARGEN from stm32f4 build config set explicitly. stm32f4 has its own USB console implementation, which chargen doesn't support yet. The affected boards are polyberry, sweetberry and stm32f446e-eval. BUG=none BRANCH=all TEST=buildall Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: I0f3dadd55fa2c197fff32afbe3fecb773491003e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2951862 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* stm32/flash-stm32h7: Use udelay() in flash_physical_erase()Patryk Duda2021-06-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replacing usleep() with udelay() fixes problem with Forced Hard Fault during rollback_entropy hardware unit test (more precisely, when rollback entropy is added). Function rollback_update() calls unlock_rollback() before erasing rollback region. Surprisingly, unlock_rollback() also disables interrupts to "minimize time protection is left open". Next flash_erase() is called and then flash_physical_erase(). If erase operation is not finished, we will call usleep() to yield CPU to some other task. It sounds good, but remember that interrupts are still disabled. To switch context we need to use SVCall exception (see svc_handler()) which is masked when interrupts are disabled. Sometimes sector was erased before we checked, so no usleep() was called. That's why it was not reproducing always. Why Forced Hard Fault occurs when calling SVC with disabled interrupts? First of all, we need to know that some exceptions have configurable priority, SVCall belongs to this group (full list can be found at 2.4.2 Exception types PM0253 Rev 5 p.40). Next thing is that we are using 'CPSID I' instruction to disable interrutps. The instruction actually sets PRIMASK register (3.12.2 CPS PM0253 Rev 5 p.176). When PRIMASK register is set it prevents activation of all exceptions with configurable priority (PM0253 Rev 5 p.25), so SVCall is masked too. OK! But why we get Forced Hard Fault? Hard Fault is 'Forced' when some other fault was escalated to Hard Fault (FORCED bit is set in HFSR register). 2.5.2 Fault escalation and hard faults PM0253 Rev 5 p.48 provides us information when escalation to Hard Fault occurs, among others it can occur when "A fault occurs and the handler for that fault is not enabled". BUG=b:170432597, b:180761547 BRANCH=none TEST=Connect icetower using microservo. sudo servod --board icetower ./test/run_device_tests.py --board dartmonkey --test rollback_entropy Make sure that test is passed and no Hard Fault occur. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I0dc1dae899b81574456a127db9c5e7a498a6f69e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939676 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* include/flash: rename the APIsTim Lin2021-06-0917-189/+195
| | | | | | | | | | | | | | | | The names conflict when enabling both Zephyr's flash driver and CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h BUG=b:187192628 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* it8xxx2/irq: wait until two equal interrupt values are readDino Li2021-06-081-1/+5
| | | | | | | | | | | | | | | This CL ensures that CPU won't get an IRQ number which is in generating. BRANCH=none BUG=b:179206540, b:189534384 TEST=No panic of unhandled irq. Change-Id: I934fc9ba7aeef520f5e275e8889722c7357c77f1 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2935652 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com>
* COIL: chip/npcx: rename IS_SLAVE_CHAN_ENABLECaveh Jalali2021-06-042-5/+5
| | | | | | | | | | | | | | This renames IS_SLAVE_CHAN_ENABLE to IS_PERIPHERAL_CHAN_ENABLE. BRANCH=none BUG=b:163885307 TEST=buildall and compare_build.sh pass Change-Id: Iaab11a2485fdcde3992ecb457c204465acfdf732 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938042 Reviewed-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Harry Cutts <hcutts@chromium.org>
* COIL: espi: replace VW_SLAVE_BTLD_STATUS_DONE with ↵Caveh Jalali2021-06-043-50/+51
| | | | | | | | | | | | | | | | | VW_PERIPHERAL_BTLD_STATUS_DONE This replaces VW_SLAVE_BTLD_STATUS_DONE with VW_PERIPHERAL_BTLD_STATUS_DONE. BRANCH=none BUG=b:163885307 TEST=buildall, compare_build.sh pass Change-Id: I0b8c71fa7e590dc89357e22aafce0b67717af183 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938041 Reviewed-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Harry Cutts <hcutts@chromium.org>
* COIL: chip/npcx: Update some commentsCaveh Jalali2021-06-042-10/+10
| | | | | | | | | | | | | | This updates some comments to be OSHWA friendly. BRANCH=none BUG=b:163885307 TEST=buildall and compare_build.sh pass Change-Id: I9fdcf1a64febccb3622379ffb5f4e31efeb8bb12 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938040 Reviewed-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Harry Cutts <hcutts@chromium.org>
* COIL: Rename MODULE_SPI_MASTER to MODULE_SPI_CONTROLLERCaveh Jalali2021-06-032-4/+4
| | | | | | | | | | | | | | | | This renames the MODULE_SPI_MASTER to MODULE_SPI_CONTROLLER. BRANCH=none BUG=b:181607131 TEST=make buildall passes; "compare_build.sh -b all" shows no difference Change-Id: I4d33f57fd82c5b57f111c12387113dc82cebe60b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932466 Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org>
* COIL: Rename CONFIG_SPI_MASTER to CONFIG_SPI_CONTROLLERCaveh Jalali2021-06-032-2/+2
| | | | | | | | | | | | | | | | This replaces the CONFIG_SPI_MASTERR config option with CONFIG_SPI_CONTROLLER. BRANCH=none BUG=b:181607131 TEST=make buildall passes; "compare_build.sh -b all" shows no difference Change-Id: I3c921085179294765baadf7074652978fe04a4ed Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932465 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org>
* chip/npcx: Fix comment white spaceCaveh Jalali2021-05-271-1/+1
| | | | | | | | | | | | | | This fixes a missing white space in a comment. BUG=none BRANCH=none TEST=buildall passes Change-Id: Ifde65ab45be7fa6881195ecf723d999d9991f2aa Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921289 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* stm32g4: ucpd: Clear tx interrupts before enableScott Collyer2021-05-271-26/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ucpd driver enables, then disables tx interrupts before and after each message is sent. This CL fixes an issue where tx interrupts weren't guaranteed to be cleared prior to enabling. This was leading to instances where the tx data byte interrupt wasn't firing when expected. The failure was exposed following a VCONN swap when VCONN is turned on. The UCPD driver will remove Rp from the CC line which has VCONN. The following PS_Rdy message would fail. Debugging this issue also led to observe that when Rp is removed for VCONN active CC lines, Rp would be applied again when Rp is adjusted by TCPM as part of collision avoidance. BUG=b:189293176 BRANCH=quiche TEST=Tested on quiche against kohaku host machine. Repro case was very consistent. Verified that failures were present without the fix in this CL. Then verified that after fixing interrupt issue, there were no hard reset/soft reset events follwoing VCONN swaps. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I289b5b5a60bbe7e880ff6b7f6fd9e5b0182f67a0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2917643 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* chip/mt8192_scp: disalbe video hardware 4k capabilityYunfei Dong2021-05-272-1/+2
| | | | | | | | | | | | | | | | | | | Disables 4K capability because the platform doesn't support it temporarily. BRANCH=asurada BUG=b:187896757 BUG=b:168868411 BUG=b:185977882 TEST=VDAtest passes on Asurada Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Change-Id: I18211671fdfe13378affe28f201ca1ef67f4c36e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921691 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
* npcx9: fix the workaround for unexpected JTAG selectionJun Lin2021-05-275-12/+43
| | | | | | | | | | | | | | | | | | | | | There is a workaround to disable the JTAG selection when the JTAG is enabled unexpectedly by the strap pin. In npcx9, the register to control the JTAG selection is different. This CL uses the correct register to let the workaround work correctly. BRANCH=none BUG=b:165777478 TEST=pass "make buildall"; check the register is correctly configured; check JTAG can be disabled when "CONFIG_ENABLE_JTAG_SELECTION" is not defined and JEN strap pin is pulled down on npcx9_evb. Signed-off-by: Jun Lin <CHLin56@nuvoton.com> Change-Id: Ic7a8a7d99335610cbacfb1de285cdd8fbda70848 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2867125 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* stm32g4: flash: Add DBANK support to option bytes WRPScott Collyer2021-05-273-60/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds support for the option bytes for dual-bank (DBANK) mode in category 3 devices. The MCU being used on honeybuns, is a category 3 flash device and DBANK mode is enalbed in the option bytes by default. When DBANK mode is enabled, then more than 1 WRP register is needed to protect the RW image. In this mode, WRP register can only protect 64 flash pages in one flash bank. BUG=b:183686750 BRANCH=quiche TEST= Case 1: HW WP active and code executing in RW > flashinfo Usable: 256 KB Write: 4 B (ideal 4 B) Erase: 2048 B (to 1-bits) Protect: 2048 B flash-phy: WRP_RO: start = 0, end = 31 flash-phy: WRP_RW: start = 32, end = 127 Flags: wp_gpio_asserted ro_at_boot ro_now all_now Protected now: YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY Case 2: HW WP active active and code executing in RO flashinfo Usable: 256 KB Write: 4 B (ideal 4 B) Erase: 2048 B (to 1-bits) Protect: 2048 B flash-phy: WRP_RO: start = 0, end = 31 flash-phy: WRP_RW: start = 127, end = 0 Flags: wp_gpio_asserted ro_at_boot ro_now Protected now: YYYYYYYY YYYYYYYY YYYYYYYY YYYYYYYY ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ Case 3: HW WP disabled > flashinfo Usable: 256 KB Write: 4 B (ideal 4 B) Erase: 2048 B (to 1-bits) Protect: 2048 B flash-phy: WRP_RO: start = 127, end = 0 flash-phy: WRP_RW: start = 127, end = 0 Flags: ro_at_boot Protected now: ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I72c03029b0231ee864afc967905c50acba4ba5de Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911738 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32/system: Wait for RVU bit clear before updating IWDG_RLRPatryk Duda2021-05-262-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC is not waiting for IWDG_RLR value to be updated in watchdog_init() function. It's intended behaviour because updating value can take much time (even 48ms) which is not desired during initialization. It's also allowed by documentation too: RM0433 Rev 7 Section 45.4.4 Page 1920 https://www.st.com/resource/en/reference_manual/dm00314099.pdf If several reload, prescaler, or window values are used by the application, it is mandatory to wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset before changing the prescaler value, and to wait until WVU bit is reset before changing the window value. However, after updating the prescaler and/or the reload/window value it is not necessary to wait until RVU or PVU or WVU is reset before continuing code execution except in case of low-power mode entry. Documentation clearly states that before next Reload Register update we are obligated to wait until RVU bit in IWDG_SR register is cleared. Setting IWDG_RLR register when RVU bit is set causes new value to be ignored. This is exactly the behaviour observed while running flash_write_protect hardware unit test. Time of Step 2 execution is short enough to perform hard reboot (all reboots between test steps are hard) when RVU bit is set. As a result setting IWDG_RLR to 1 is ignored and watchdog is reloaded with old value. This is why it takes very long to perform hard reset and watchdog trace is printed. Platforms affected by this change: STM32H7: nocturne_fp (dartmonkey) nucleo-h743zi STM32F4: hatch_fp (bloonchipper) nucleo-f411re nucleo-f412zg polyberry sweetberry stm32f446e-eval BUG=b:170432597 BRANCH=none TEST=Run flash_write_protect hardware unit test on icetower board using `./test/run_device_tests.py --board dartmonkey \ --tests flash_write_protect` Make sure that test passes and no watchdog traces appear. TEST=Run flash_write_protect hardware unit test on dragonclaw 0.2 board using `./test/run_device_tests.py --board bloonchipper \ --tests flash_write_protect` Make sure that test passes and no watchdog traces appear. Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I2585dcbf3cb1a14107c7ae674c51999f082e3df7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2917115 Reviewed-by: Craig Hesling <hesling@chromium.org>
* chip/npcx/espi: Remove errata 2.22 for NPCX7+Raul E Rangel2021-05-251-0/+10
| | | | | | | | | | | | | | | | | | | Errata 2.22 requires that we disable the peripheral support while enabling the peripheral channel. This workaround was only required for NPCX5. This change removes the errata for NPCX7+. This workaround was also racy. If the host read the capabilities before the PLTRST# interrupt handler completed, then it might think that the device doesn't support the peripheral channel. BUG=b:188188172, b:188935533 BRANCH=none TEST=Boot guybrush to the OS. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I38bc7016280ab99135b1a9af8c76e4cceebfb605 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912927 Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* chip/npcx/espi: Fix race condition between PLTRST# and PCHANENRaul E Rangel2021-05-251-3/+3
| | | | | | | | | | | | | | | | | | The PLTRST# handler has a race condition. It sets the peripheral channel ready bit before the IO ports are memory mapped. This means that the AP can start sending IO requests before the mappings are ready. BUG=b:188188172, b:188935533 BRANCH=none TEST=On guybrush make an EC call after eSPI init. I no longer see a failure. Also verify zork still boots. Suggested-by: Rob Barnes <robbarnes@google.com> Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I09c58ef989b8bb90d7662afc63d23dc5498c293b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
* mchp: Default espi configurationPoornima Tom2021-05-202-29/+38
| | | | | | | | | | | | | | | | In ESPI communication, when no specific configs are defined, the default configuration must use Maximum frequency, all channels and all modes. BUG=b:186669325 BRANCH=none TEST=make buildall -j Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I61caa65f22d394093bfd1ebd39c9d065d5c1b2d0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784334 Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* chip/mt8192_scp: using mm21 instead of mt21cYunfei Dong2021-05-171-1/+1
| | | | | | | | | | | | | | BRANCH=asurada BUG=b:187782435 TEST=make BOARD=asurada_scp Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.corp-partner.google.com> Change-Id: I71d7dd7fa0764f7f8810553021b6a7d1b62d83f5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2896761 Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
* stm32: Add helper function for H7 flash ctrl regsJosie Nordrum2021-05-114-105/+199
| | | | | | | | | | | | | | | | | | | Add helper function definitions for H7 to API added in chromium:2220735. This should enable flash_physical test to run on Dartmonkey. Refactor code to pull flash registers function declarations from flash-reg.h instead of flash-f.h BRANCH=None BUG=b:157692395 TEST=On dartmonkey ./test/run_device_tests.py -t flash_physical => pass Signed-off-by: Josie Nordrum <josienordrum@google.com> Change-Id: I76846938748cbe77d534915856af0ebb7211d247 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2576799 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* panic.c: force sync before reenabling bus faultsJosie Nordrum2021-05-111-3/+0
| | | | | | | | | | | | | | | | | | Force a sync between data and instruction pipelines before allowing bus faults. Remove sync from flash-stm32h7.c BRANCH=None BUG=b:157692395 TEST=tested with crrev.com/c/2576799 Signed-off-by: Josie Nordrum <JosieNordrum@google.com> Change-Id: Id67324191b4447d9be10c0b5aecc87620aa69d1d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2706039 Tested-by: Josie Nordrum <josienordrum@google.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Josie Nordrum <josienordrum@google.com> Auto-Submit: Josie Nordrum <josienordrum@google.com>
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