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* ish: use correct I2C eventJett Rink2019-01-281-4/+2
| | | | | | | | | | | | | | | | | There is a section of event bits that are reserved for all tasks. We need to use one of the upper bits instead of a bit 7 which may conflict with other tasks eventually. BRANCH=none BUG=none TEST=i2c transaction still works Change-Id: Ie8b98f7a159159714f12dc87ce26b009ceee3f92 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1435479 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* ish: make unimplmented GPIOs perform no-opsJett Rink2019-01-282-5/+22
| | | | | | | | | | | | | | | When reading or writing to an UNIMPLEMENTED gpio right now, it would actually read or write GPIO0. Add guards to prevent unimplemented GPIOs from interacting with hardware BRANCH=none BUG=none TEST=build and real gpios still work Change-Id: If661ebe66a0b5d4fc4f69bee314c90bce0eedf11 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1435478 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* link_defs.h: Renames __ro_end to __data_lma_start.Yilun Lin2019-01-281-1/+1
| | | | | | | | | | | | | | | | | | The name of __ro_end is confusing. The variable is actually used as a label tagging that it is the starting address of .data LMA. Renames to __data_lma_start to be more decriptive. BRANCH=None TEST=make buildall -j BUG=b:122084384 Change-Id: I8990a2a1f3d0719739a8e649b881cb277fe5a9b8 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1433160 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Add support to store some code in DRAMNicolas Boichat2019-01-241-0/+5
| | | | | | | | | | | | | | | | | This allows to store specific code/data in a .dram region. This is used by mt_scp to run code off DRAM, as we plan to have more code than what can fit in SRAM. BRANCH=none BUG=b:122058243 TEST=make BOARD=kukui_scp -j objdump -x build/kukui_scp/ec.obj => Some code is loaded in DRAM TEST=Load kukui_scp, icachetest works Change-Id: Idbab809ba86cabe3b984944adc2781b37d2d544b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1391542
* mt_scp: Enable I/D-cache on bootNicolas Boichat2019-01-243-7/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable cache mapping on boot, add functions for cache support. Invalidate the cache on boot, and add benchmarching function. BRANCH=none BUG=b:117804463 TEST=Boot kukui_scp with TEST-ONLY CL. TEST=Run dcachetest command, see performance difference, and lack of coherency if the data is updated from AP side. > dcachetest cached: 19745 us (val: ef915230) cached+inval: 39402 us (val: ef915230) direct: 94096 us (val: ef915230) TEST=See that icachetest (cached) and perftest have similar performance: > icachetest run from DRAM (cached): 102779 us (total: 12a052eb9) run from DRAM (direct): 1867168 us (total: 12a052eb9) > perftest run from SRAM: 102566 us (total: 12a052eb9) TEST=cacheinfo reports sensible data: > cacheinfo Icache hit count: 12000127 Icache access count: 12000131 Dcache hit count: 960034 Dcache access count: 1024034 Change-Id: I3272f4ff9edc0059c4937908b1235346c582c680 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1391529 Reviewed-by: Rong Chang <rongchang@chromium.org>
* mt_scp/memmap: Enable memmap between AP and SCP.Yilun Lin2019-01-245-23/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCP/AP can access the AP/SCP address via memory address translation. TEST=Run memmap (TEST-ONLY CL), see direct mapping makes sense: Direct mapping: 00001000 INVAL 0f002000 INVAL 10003000 INVAL 1f004000 INVAL 20005000 40005000 => 20005000 OK 2f006000 4f006000 => 2f006000 OK 30007000 50007000 => 30007000 OK 3f008000 5f008000 => 3f008000 OK 40009000 INVAL 4f00a000 INVAL 5000b000 INVAL 5f00c000 INVAL 6000d000 6000d000 => 6000d000 OK 6f00e000 6f00e000 => 6f00e000 OK 7000f000 7000f000 => 7000f000 OK 7f010000 7f010000 => 7f010000 OK 80011000 80011000 => 80011000 OK 8f012000 8f012000 => 8f012000 OK 90013000 00013000 => 90013000 OK 9f014000 0f014000 => 9f014000 OK a0015000 10015000 => a0015000 OK af016000 1f016000 => af016000 OK b0017000 20017000 => b0017000 OK bf018000 2f018000 => bf018000 OK c0019000 30019000 => c0019000 OK cf01a000 3f01a000 => cf01a000 OK d001b000 1001b000 => a001b000 BAD df01c000 1f01c000 => af01c000 BAD (these are ok as 0x1* is mapped from both 0xd* and 0xa*) e001d000 a001d000 => e001d000 OK ef01e000 af01e000 => ef01e000 OK f001f000 9001f000 => f001f000 OK ff020000 9f020000 => ff020000 OK BRANCH=None BUG=b:114326670 Change-Id: I29298c2e5a897d08d21390c751bdd881170adb59 Signed-off-by: Yilun Lin <yllin@google.com> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1385910 Reviewed-by: Erin Lo <erin.lo@mediatek.com> Reviewed-by: Rong Chang <rongchang@chromium.org>
* it83xx: add enable/disable espi pad functionDino Li2019-01-223-4/+18
| | | | | | | | | | | | | | | We can call this function to enable/disable espi pad if needed. BUG=b:121105042 BRANCH=none TEST=buildall Change-Id: I61561b1a4657947e27053de3e8b2ef053651d949 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1426303 Commit-Ready: Justin TerAvest <teravest@chromium.org> Tested-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm/it83xx.c: don't reload cc parameter settings for DxRuibin Chang2019-01-221-0/+2
| | | | | | | | | | | | | | | | | | The USB-PD PHY trimming value is reloaded wrongly after software reset. BUG=b:123173731 BRANCH=none TEST=cc parameters are the same, after ec software reset and hardware reset on Bx and Dx. Change-Id: I0c7144afbb648680bb60cc128c8212abb43ccd68 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1426300 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* cleanup/ish: update copyright header to styleJett Rink2019-01-1910-10/+10
| | | | | | | | | | | | | (c) Copyright header is no longer the style. Update so presubmit check stops complaining BRANCH=none BUG=none TEST=presumbit no longer complains Change-Id: I0de5558467859cf0b735545161ed9d1c08e0fae4 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1422057
* mt_scp/ipi: Fix typo in IPI macro check.Yilun Lin2019-01-181-1/+1
| | | | | | | | | | | | | TEST=make BOARD=kukui_scp -j BUG=None BRANCH=None Change-Id: I18cef1540fd3fe76269a16edab6c622084417c7e Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1420248 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Pi-Hsun Shih <pihsun@chromium.org>
* ish: fix 32-bit quotient overflowJett Rink2019-01-162-7/+50
| | | | | | | | | | | | | | | | | Restructure the hw_clock_source_read to perform a divide by 12 operation on a 64-bit number without causing a 32-bit overflow for the quotient by performing the operation in stages. Also ensure that the 64-bit read doesn't tear (by rolling over) while we are reading it. BRANCH=atlas BUG=b:122314133,b:121454497 TEST=use fortime on atlas to put time next to rollover point and verify that we no longer get a divide expection (#DE) Change-Id: I0b5fe59bec9a703fddac657986106537d4e9e203 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1394753 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: Extend CR50 Bitbang Receive buffer.Namyoon Woo2019-01-161-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bitbang receive buffer in CR50 gets bigger so that 257 byte chunk transfer can be done without any data loss. BUG=b:112163028 BRANCH=cr50 TEST=manually tested by writing/reading EC binary in bitbang mode. (a) Flash EC binary $ flash_ec --board=${BOARD} --bitbang_rate 57600 \ --image ${EC_BIN_PATH} (b) Read EC binary $ dut-control --port=9999 ec_ec3po_interp_connect:off $ dut-control --port=9999 ccd_ec_boot_mode_bitbang:on $ dut-control --port=9999 cold_reset:on $ dut-control --port=9999 cold_reset:off $ dut-control --port=9999 ec_uart_parity:even $ dut-control --port=9999 ec_uart_baudrate:57600 $ dut-control --port=9999 ec_uart_bitbang_en:on $ time stm32mon -d ${RAW_EC_UART_PTY} -c -r ${EC_BIN_READ_PATH} \ -b 57600 ... Reading 262144 bytes at 0x08000000 262144 bytes read. real 1m0.739s user 0m0.024s sys 0m0.125s $ diff ${EC_BIN_PATH} ${EC_BIN_READ_PATH} $ Change-Id: I0ee76085eedf44b1cba2c686003335b109c0272c Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1394284 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: shi: enable sleep bit in suspend hook function.Mulin Chao2019-01-161-0/+6
| | | | | | | | | | | | | | | | | | | | | | | In order to make sure ec can enter deep sleep even if there's a CS drop at S5, the shi driver turns off it's interrupt in suspend hook function in case the sleep bit, SLEEP_MASK_SPI, is disabled in shi's ISR. However, in some cases, CS dropped before ec was informed by hook function. It will make ec cannot enter deep sleep at S5. This CL allows ec enter deep idle at S5. It will enable sleep bit, directly in suspend hook function even if CS drops before ec was informed. BRANCH=none BUG=b:118844551 TEST=No build errors for npcx7 series. Change-Id: I61719fad74bfd85006b6c90dd46b69cb103dcfa9 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1410792 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* it83xx: disable eSPI pad before EC sleepDino Li2019-01-161-1/+21
| | | | | | | | | | | | | | | On Dx version, EC is not able to enter sleep mode properly if eSPI CS# pin is low. This change disables eSPI pad before system hibernate, so EC is able to enter sleep mode properly. BUG=b:121105042 BRANCH=none TEST=On Ampton, EC power consumption drops in system hibernate. Change-Id: Ic6dce407f95a5cf93837be9aef92c5bbbd9cba30 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/1404642 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx: reset espi module during init on DX versionDino Li2019-01-162-0/+11
| | | | | | | | | | | | | | | | | | | Symptom: On Ampton, boot to kernel with coreboot image R73-11543.0.0 (eSPI is operating at Quad I/O mode). Reboot EC with console command "reboot", eSPI will get stuck after power sequence is done. Because I/O mode field will not go back to default setting (single I/O mode) after a software reset. BUG=b:122820812 BRANCH=octopus TEST=Running "reboot" on the EC console and then boot to kernel. Change-Id: I65252aa191294458467f3ba55b2071659f3b5ae8 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/1408752 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* it83xx: disable eSPI pad before changing PLLDino Li2019-01-112-9/+10
| | | | | | | | | | | | | | | | | | | | | This change inhibits eSPI CS# pin's function by disabling pad instead of turning VCC off. Because eSPI module will also reset if we turn VCC off, but we just want to inhibits CS# function. (eSPI module will be reset after sysjump if PLL setting of RO/RW images are different.) BUG=b:70537592 BRANCH=none TEST=On Ampton, EC clock frequency is correct after changing PLL sequence. Change-Id: I263132aa6e94542b03afc840ede8527ea98e2927 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1404641 Commit-Ready: Justin TerAvest <teravest@chromium.org> Tested-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/stm32/clock: Enable STOP mode when the host sets wake alarmPhilip Chen2019-01-113-41/+120
| | | | | | | | | | | | | | | | | BUG=chromium:769503 BRANCH=scarlet TEST=make buildall -j TEST=On scarlet: 1) 'powerd_dbus_suspend --wakeup_timeout=10' on AP console. 2) When AP is in S3, confirm ec enters STOP mode by 'idlestat'. 3) Confirm AP still wakes up at the right time. Change-Id: I0ce60cc6c33cb475b3311de83c35fe73ff92641b Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/706537 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cr50: Deferred RDD check in deasserting EC_RST_L.Namyoon Woo2019-01-091-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | RDD connection can be detected after the debug cables comparator values are stable, which takes RDD_MAX_WAIT_TIME_COUNTER. This CL changes to check RDD connection in a deferred way only when it is a power-on reset and the power button is held. This CL increases Flash memory usage by 40 bytes. BRANCH=cr50 BUG=b:37351386 TEST=manually on bob, coral and scarlet. 1. (EC) cutoff 2. unplug all cables. 3. hold the power button. 4. plug USB-C cable of Servo V4 (or SuzyQ cable) in. 5. check EC console. Should be off. To verify, run the cr50 console command, 'ecrst' and check if 'EC_RST_L' is asserted. 6. release the power button. EC should run. Change-Id: I4c7b0653bf49fbe57c8ad8395c72e006fa3a0ff0 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1398921 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* chip: stm32: clock-stm32f4: Implement rtc_set() for RTCstabilize-11554.BMoritz Fischer2019-01-091-2/+30
| | | | | | | | | | | | | Implement rtc_set() function for STM32F4 chip variant BUG=none BRANCH=none TEST=Using eval-board, use rtc set 0, observe increments Change-Id: I63abe0c388b7a0ba9ed881b393ffdbcc69e6d75a Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: https://chromium-review.googlesource.com/1401017 Reviewed-by: Philip Chen <philipchen@chromium.org>
* ish/uart: fix wrong register address access in uart_tx_start()Hu, Hebo2019-01-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | void uart_tx_start(void) { ... if ( REG8(IER(id) & IER_TDRQ) ) return; ... } the expression 'REG8(IER(id) & IER_TDRQ)' is wrong, '(IER(id) & IER_TDRQ)' is not a register address but a '0' value, '0' address is a invalid address in ISH. the correct expression of read IER register and check TDRQ bit should be: 'REG8(IER(id)) & IER_TDRQ'. BUG=b:122052562 BRANCH=none TEST=tested on arcada Change-Id: I811ce68ff17e197df83a8d44bffaa58799cbb3b6 Signed-off-by: Hu, Hebo <hebo.hu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1390942 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
* pd: Enable USB PD SOP' and SOP'' CommunicationSam Hurst2019-01-071-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, the PD stack ignores messages received from SOP' and SOP'' and this prevents the stack from communicating with VCONN Power Devices and Cable Plugs in general. I propose encoding the message address (SOP*) in the message header. The message header is encoded as a 16-bit value but the TCPC drivers use a 32-bit type for the header. The SOP* address will be stored in bits 31 to 28 of the message header and the PD stack can check those bits to determine the address of the message. BUG=b:122109575 BRANCH=none TEST=manual Change-Id: I2b34c16cae186202c9cf0bc5f940e05151e88cbf Signed-off-by: Sam Hurst <shurst@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1390951 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/stm32/clock: Cleanly clear pending RTC alarm IRQPhilip Chen2019-01-051-0/+3
| | | | | | | | | | | | | | | | | | | We want to reset RTC alarm and clear pending IRQ when EC wakes up from deep sleep mode. Unfortunately, RTC alarm IRQ is still latched and pending in NVIC unless we explicitly clear the flag in ICPR register. BUG=chromium:769503 BRANCH=scarlet TEST=confirm RTC alarm irq is not fired after EC exits deep sleep mode Change-Id: If6b9815337fbd24a0337116ef9c5fa1521671a93 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1390947 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* stdlib cleanup.Allen Webb2019-01-031-2/+3
| | | | | | | | | | | | | | | | This cleanups some header includes to avoid conflicts between the ec headers and the standard c headers. BRANCH=None BUG=None TEST=make -j buildall && ./build_packages --board=veyron_minnie \ chromeos-ec && FEATURES=test emerge-veyron_minnie chromeos-ec Change-Id: Icf9022d688fd9c749f7a5f8673755188741b40e1 Signed-off-by: Allen Webb <allenwebb@google.com> Reviewed-on: https://chromium-review.googlesource.com/1378906 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp/ipi: Support host command.Yilun Lin2018-12-291-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | mt_scp is the first chip which uses IPI to do host command communication. This CL implements the host command over IPI. TEST=Run ec.RW.bin on kukui by "echo start > /sys/class/remoteproc/remoteproc0/state" and see that there are HC logs from SCP uart [0.000385 hostcmd init 0x0000000000002000] [0.049958 HC 0x0b] [0.050061 HC 0x400b] [0.050108 HC 0x400b err 1] [0.050204 HC 0x08] [0.050240 HC 0x08 err 3] [0.050370 HC 0x8d] [0.050406 HC 0x8d err 1] [0.050821 HC 0x0d] BUG=b:117917141, b:120953723 BRANCH=None Change-Id: I2c2b701d92504a74cc2ee90ab05912e99378acde Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1379410 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Support inter-process interrupt/communication (IPI).Yilun Lin2018-12-297-4/+368
| | | | | | | | | | | | | | | | | | This CL enables the IPI/IPC functions in mt_scp on MTK SOC. TEST=Run ec.RW.bin on kukui, and see EC version string in AP console: remoteproc remoteproc0: powering up scp remoteproc remoteproc0: Booting fw image scp.img, size 29800 mtk-scp 10500000.scp: scp is ready. kukui_scp_v2.0.519+164255084 BRANCH=None BUG=b:117917141, b:120172001, b:120953723 Change-Id: I2a43aee13141535bf71f839cf9e6cc0460b65844 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1351924 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* ISH: HID: implement HID subsystemHyungwoo Yang2018-12-283-0/+531
| | | | | | | | | | | | | | | | | | Introduce HID subsystem. HID subsystem provides interface for a HID device to communicate with host. Using this API, a HID device can use hid-core in host. BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279432 Change-Id: I0547a07e1c1cb5d34ba11b245ca539cf53b7d30d Reviewed-on: https://chromium-review.googlesource.com/1279433 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ISH: HECI: implement HECI layerHyungwoo Yang2018-12-286-0/+1418
| | | | | | | | | | | | | | | | | | | Introduce Host Embedeed Controller Interface for ISH. HECI is bi-directional fully asynchronous communication interface between host and ISH. It enables a host software to communicate with a ISH software(a HECI client). BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. CQ-DEPEND=CL:1279363 Change-Id: I5fdc3018e9575c5fd0c804a883293f6c9f8aa2e7 Reviewed-on: https://chromium-review.googlesource.com/1279432 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* ISH: IPC: implement generic IPC layerHyungwoo Yang2018-12-274-0/+1002
| | | | | | | | | | | | | | | | Introduce new IPC API supporting MNG and HECI protocols. Currently it supports communication with host(x64) BUG=b:79676054 BRANCH=none TEST=Tested on Atlas board. Change-Id: Iea6d1f96c89228b425861d045618d58f9d146f08 Reviewed-on: https://chromium-review.googlesource.com/1279363 Commit-Ready: Hyungwoo Yang <hyungwoo.yang@intel.com> Tested-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* mt_scp: Support SCP reset stepping stone function.Yilun Lin2018-12-234-1/+28
| | | | | | | | | | | | | | | | | | | | SCP assumes vector table at CONFIG_RAM_BASE. However, on cortex-m resetting, it would load 0x0 to SP(r13) and load 0x04 to PC(r15). Stepping stones copy these two very special values from CONFIG_RAM_BASE, CONFIG_RAM_BASE + 0x04 to 0x0, 0x4 resepctively. TEST=make BOARD=kukui_scp -j, and see the value from 0x0, 0x4 in kukui_scp/RW/ec.RW.flat are the same as 0x800, 0x804 respectively. TEST=Puts ec.RW.bin on kukui and see that SCP boots. BUG=b:120825336 BRANCH=None Change-Id: I71670d5d4b5ba3aaad17c264a2a3bc3076703a9c Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1373950 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp/uart: Do not use usleep in tx_flush/write_charNicolas Boichat2018-12-231-3/+2
| | | | | | | | | | | | | | | These functions may be called in interrupt/exception context, especially when panic_printf is used. We need to busy-loop. BRANCH=none BUG=b:119929419 TEST=crash divzero works Change-Id: Ie97243afcc433226e78ea1b1225227c6ffbf2a04 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1373288 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp/hrtimer: Fix race condition in timer_read_raw_systemNicolas Boichat2018-12-231-2/+11
| | | | | | | | | | | | | | | | | | | When the 32-bit bit timer @26Mhz wraps around, there is a short amount of time when the 32-bit timer value (@1Mhz) is incorrect. Fix this by manually adjusting sys_high if an interrupt is pending. BRANCH=none BUG=b:120173036 BUG=b:120763595 TEST=Boot kukui_scp, leave it running for 200 seconds taskinfo "time in exceptions" look reasonable Change-Id: I053972d018e3e5e9c46cb73a0edb16b0354d5c43 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1372871 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* npcx: lpc: don't set SHCFG[7:5] in the driver's initializationCHLin2018-12-201-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | In older Nuvoton EC chips (prior NPCX5), the Semaphore register is mapped to offset 0 of the Shared RAM Window by default. We usually disable it in the driver by setting SHCFG[7:6] both to 1 if we want to disable the Semaphore mechanism. However, in NPCX5 and later chips, this behavior is deprecated (the Semaphore register is not mapped to offset 0 of the Shared RAM Window by default). These bits (including bit 5) were removed. The driver should keep these bits at their default state. Otherwise, the Semaphore mechanism may not work as expected. BRANCH=none BUG=b:73018524 TEST=pass make buildall. TEST=build and flash reef/grunt/yorp image, stress test the host command and host event, no symptom occurs. Change-Id: I63031f3957d0485f18fb8c4f1b13ad56c2dc5804 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1383675 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* kukui: Add initial kukui_scp board for SCP developmentRong Chang2018-12-201-2/+2
| | | | | | | | | | | | | | | | | | | Kukui is the first project with Chromium OS EC based SCP. This is an base board to develop SCP functionalities. BRANCH=none BUG=b:114326670 TEST=manual make BOARD=kukui_scp -j Change-Id: I65897d5439e88cebdc6543e5a8e07cd5657303e7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208772 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* scp: Add mt_scp chipRong Chang2018-12-2010-0/+1618
| | | | | | | | | | | | | | | | | | | | | | | SCP is a Cortex-M4 based sensor hub in Mediatek SoC. This change adds the chip folder and system level drivers. BRANCH=none BUG=b:114326670 TEST=manual make BOARD=kukui_scp -j copy ec.bin to /lib/firmware/scp.img echo 'stop' > /sys/class/remoteproc/remoteproc0/state echo 'start' > /sys/class/remoteproc/remoteproc0/state check EC uart console Change-Id: I6629149f352184108fa520e80b59fd2ce94c76f7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208770 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* it83xx/intc:add type-c plug in interruptRuibin Chang2018-12-183-0/+32
| | | | | | | | | | | | | | | When tcpc detect type-c plug in (cc lines voltage change), it will interrupt fw to wake pd task, so task can react immediately. BRANCH=None BUG=None TEST=GRL USBPD test Change-Id: I194b2fcad1d0c62dde2d3296753abd47af8feea6 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1333207 Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/ish: replace CONFIG_ISH_xx flags with CHIP_FAMILY and CHIP_VARIANTShine Liu2018-12-184-19/+17
| | | | | | | | | | | | | | | | | Replace all CONFIG_ISH_xx flags in chip/ish/* files with CHIP_FAMILY and CHIP_VARIANT. Which provides more structural defines between ISH generations. BRANCH=none BUG=b:120295222 b:112385410 TEST=Test host FW loading for main ISH FW. Change-Id: Ica92eee11034447c9f0828aa986fb1736d20cf27 Signed-off-by: Shine Liu <shine.liu@intel.com> Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1367010 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Keyboard: Consolidate keyboard factory testsDaisuke Nojiri2018-12-173-198/+7
| | | | | | | | | | | | | | | | | This patch consolidates keyboard factory tests, which are currently duplicated under the chip directories. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=buildall Change-Id: I1ab8bc96808e1c284d991d3c2f1f82a37329676e Reviewed-on: https://chromium-review.googlesource.com/1378654 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* keyboard: restore KBD_KSO2 after keyboard factory scan testingDevin Lu2018-12-173-3/+12
| | | | | | | | | | | | | | | | | This patch fix the keyboard malfucntion with KBD_KSO2 line after executed "ectool kbfactorytest". BUG=none BRANCH=octopus TEST=make sure keyboard works after executed "ectool kbfactorytest" on meep. Change-Id: I33c22e59a01884ff6c961161e189583a6c3673a3 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/1373389 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/spi: rename spi.c to spi_master.ctim2018-12-132-1/+1
| | | | | | | | | | | | | | | | | In it83xx chip, the file of spi.c is renamed to spi_master.c, and the related config is renamed too. BUG=none BRANCH=none TEST=none Change-Id: Ia696e62afa2ff06da68a3e4af685615b1dbcc8e9 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1372870 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: VENDOR_CC_IMMEDIATE_RESET may have a delay argument.Namyoon Woo2018-12-131-6/+39
| | | | | | | | | | | | | | | | | VENDOR_CC_IMMEDIATE_RESET has either uint16_t argument or none. The argument is a time delay in millisecond unit. If it has no argument, then Cr50 resets H1 immediately without any delay. BUG=b:120485010 BRANCH=cr50 TEST=none Change-Id: I33aaacbb0a0532aa84f39a8cd51d0d54fa2d281a Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1361998 Commit-Ready: Joel Kitching <kitching@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ISH3.0: Scaling timer from 12MHz to 1MHzSadashiva Rao Pv2018-12-122-4/+54
| | | | | | | | | | | | | | | | | | | | | | | -Added support to scale 12MHz to 1MHz -Fixes the timestamp issue -Changes under CONFIG_ISH_30 ISH 3.0 has 12MHz Main counter ISH 4.0 has 32KHz Main counter BUG=none BRANCH=master TEST=On Soraka board modified for ISH, ensure clock tick happens correctly. Ensure ISH probe and sensor info is seen in kernel logs Change-Id: Ib5d8a48bf99d1398a0424596399abd7df431e07a Signed-off-by: Naresh Solakni <naresh.solanki@intel.com> Signed-off-by: Sadashiva Rao Pv <sadashiva.rao.pv@intel.com> Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/686434 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* chip/ish: change host command ready from 8 to 3Shine Liu2018-12-121-1/+1
| | | | | | | | | | | | | | | | To accomondate upcoming arcada_ish board, changing MNG_HC_FW_READY from 8 to 3 BRANCH=none BUG=b:120295222 TEST=Test host FW loading for main ISH FW. Change-Id: Ibee24cb01c6078177ba9ef1ad30c360a3157a84e Signed-off-by: Shine Liu <shine.liu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1367012 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx: force filling cache if the last two 4KB blocks of 512KB flash are ↵Dino Li2018-12-102-3/+37
| | | | | | | | | | | | | | | | | | | modified After immu reset, we will fill the immu cache with 8KB data that are outside address 0x7e000 ~ 0x7ffff. When CPU tries to fetch contents from address 0x7e000 ~ 0x7ffff, immu will re-fetch the missing contents inside 0x7e000 ~ 0x7ffff. BUG=b:111808417, b:119799561 BRANCH=none TEST=use console "flasherase" and "flashwrite" commands to erase/write last two 4KB blocks(0x7e000 ~ 0x7ffff), no error message occurred. Change-Id: Ia97c814f20d602c591c39040b964b122edd50205 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1365372 Reviewed-by: Diana Z <dzigterman@chromium.org>
* cr50: Fix return value for VENDOR_CC_SN_SET_HASH.Louis Collard2018-12-061-2/+2
| | | | | | | | | | | | | | | | | I made a careless mistake when incorporating comments during review of CL:1237696 and broke the return value for this vendor command. The command still sets SN bits correctly, but in most cases (success and failure), returns VENDOR_RC_NOT_ALLOWED. BUG=b:111195266 TEST=tested locally on soraka BRANCH=none Change-Id: I6d3bc1c9df7737f7469c6f432da2e65c79f324a6 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1364490 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* wov: Add API method to retrieve the channel gain parametersScott Collyer2018-12-062-0/+22
| | | | | | | | | | | | | | | | | | | | | This CL adds a new function wov_get_gain() so the codec driver can query the current channel gain values. BRANCH=none BUG=b:116766596 TEST=On cheza verifed recording works using the following kernel commands and the loading the audio file into audacity. amixer -c 0 cset iface=MIXER,name='MultiMedia1 Mixer SEC_MI2S_TX' on amixer -c0 cset numid=27 30,30 arecord -D hw:0,0 -f dat /tmp/rec.wav -d 5 Change-Id: I5aab58a651d95727cf5c49149898f78ca25c78cf Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1356184 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* cr50: provide DCRYPTO_ladder_is_enabled() for test and fuzz buildsVadim Bendebury2018-12-061-10/+14
| | | | | | | | | | | | | | | This function is called from common/nvmem.c, it should be available when compiling for tests, the stub could be filled up later when new tests are added. BRANCH=cr50, cr50-mp BUG=b:119221935 TEST=make buildall -j still succeeds. Change-Id: I082292818c7f2b10336c9a7c49e0a9195e25a12b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1363816 Reviewed-by: Allen Webb <allenwebb@google.com>
* test/usb_pd_fuzz: Fuzzing of USB PD dataNicolas Boichat2018-12-051-1/+1
| | | | | | | | | | | | | | | Setup CC lines, then send up to 8 PD messages, in an attempt to cause errors while parsing PDO and other messages. BRANCH=none BUG=chromium:854975 TEST=make -j buildfuzztests && \ ./build/host/usb_pd_fuzz/usb_pd_fuzz.exe > /dev/null Change-Id: Ibb575ea8d464945390d1663dd6fff279bd9d77ea Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1116626 Reviewed-by: Jonathan Metzman <metzman@chromium.org>
* cr50: revoke key ladder on disabling TPMNamyoon Woo2018-12-052-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Disabling TPM will do revoke H1 key laddder. Querying TPM_MODE or enabling TPM_MODE will fail if H1 Key Ladder is already revoked. BUG=b:118504817 BRANCH=cr50 TEST=Manually tested with TPM disabling and Resume or Warm Reboot. (1) Resume $ trunks_send --raw 80 01 00 00 00 0c 00 00 01 45 00 01 80010000000A00000000 $ gsctool -a -m disable TPM Mode: disabled (2) $ echo mem > /sys/power/state (press key on chromebook either after three seconds or in a second.) (2) Warm Reboot $ gsctool -a -m disable (press refresh + power button or run kernel command 'reboot') Check Chrome os boot ok. No TPM command failures were observed (in CR50 console). (3) Windows Warm Reboot or Resume are checked. Change-Id: I32fffc432a9a6068ea324a97225974c581cb9359 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1312197 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* wov: Modify wov_set_gain to update gain params in wov_confScott Collyer2018-12-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | The function wov_set_gain would only pass along the desired channel gain values to the apm, but did not update channel gain parameters of wov_conf. This CL modifies this function to also update those parameters so they can be saved an retrieved by the audio codec. BRANCH=none BUG=b:116766596 TEST=On cheza verifed recording works using the following kernel commands and the loading the audio file into audacity. amixer -c 0 cset iface=MIXER,name='MultiMedia1 Mixer SEC_MI2S_TX' on amixer -c0 cset numid=27 30,30 arecord -D hw:0,0 -f dat /tmp/rec.wav -d 5 Change-Id: I2d0e1e386769bb25754a684b391362c4ea02b39b Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1356183 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* wov: Split i2s_set_config into 2 functionsScott Collyer2018-12-042-11/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | This API was intended to be used to set both the I2S format and BCLK rate. However, the audio codec API has separate methods to set each of these parameters. This CL splits wov_i2s_set_config() into 2 functions: wov_i2s_set_fmt() - called by codec_i2s_set_fmt host command wov_i2s_set_bclk() - called by codec_i2s_set_bclk host command BRANCH=none BUG=b:116766596 TEST=On cheza verifed recording works using the following kernel commands and the loading the audio file into audacity. amixer -c 0 cset iface=MIXER,name='MultiMedia1 Mixer SEC_MI2S_TX' on amixer -c0 cset numid=27 30,30 arecord -D hw:0,0 -f dat /tmp/rec.wav -d 5 Change-Id: Id840ecf1b4c00762091d71b6cc10b00acc774eb2 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1356182 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
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