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* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-2912-20/+22
| | | | | | | | | | | | | | | | We will move to an API compatible with Zephyr's API. See the bug for complete rationale and plan. BUG=b:169151160 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: Id611f663446abf00b24298a669f2ae47fef7f632 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2427507 Tested-by: Dawid Niedźwiecki <dn@semihalf.com> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/mt8192_scp: support ULPOSCTzung-Bi Shih2020-09-294-0/+478
| | | | | | | | | | | | | | | Supports ULPOSC and selects ULPOSC2 (360MHz). BRANCH=none BUG=b:146213943 BUG=b:156222893 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Change-Id: Ib9f043bb5575a6e18fc64479c7b241e11e012b5c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2198823 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* npcx: make required changes in some modules for npcx9CHLin2020-09-2510-23/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Functions are supported in npcx7 but npcx5 are guarded by: "#if defined(CHIP_FAMILY_NPCX7)." In npcx9, most of these functions are inherited. Change the guard to: "#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7" 2. Configure APB4DIV in clock.c 3. In npcx5/7, the host interface type (HIF_TYP_SEL in the DEVCNT register) is updated by booter after VCC1 Power-Up reset according to VHIF voltage. In npcx9, the booter will not do this anymore. Set the HIF_TYP_SEL filed at initialization in lpc.c anyway to cover to all chip family. 4. Configure power down registers appropriately. 5 add symbolic links: i2c-npcx9.c -> i2c_npcx5.c system-npcx9.c -> system-npcx7.c BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST=with related CLs, build and flash image on the npcx7/9 EVB and yorp, no symptom occurs. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I17a71b7b90435d4a3ff75aac18bf2640b5b15515 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402843 Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* npcx: add GPIO support for npcx9 and refactor GPIO driverCHLin2020-09-258-185/+899
| | | | | | | | | | | | | | | | | | | | | 1. Add GPIO driver support for npcx9. 2. move the GPIO interrupt handler (MIWU) from gpio.h to gpio-npcx5.h, gpio-npcx7.h, and gpio-npcx9.h separately. Note: gpio-npcx7.h is a link to gpio-npcx5.h because almost all of the source codes are the same. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST=with related CLs, build and flash image on the npcx5/7/9 EVB and yorp; verify GPIO functionality. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I665507f804ca3772f81f0ff8bd917a633bda2d11 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402842 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx: fix ADC repetitive mode and single mode switchWealian Liao2020-09-252-13/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL fix ADC repetitive/single mode switch and repetitive mode channel enable toggle issue. 1. ADC repetitive mode doesn't work after invoking adc_read_channel(). After invoking adc_read_channel(), the ADC module sets to single channel operation mode. ADC doesn't set back to repetitive mode. This CL sets ADC back to the repetitive mode in adc_read_channel() if anyone uses repetitive mode. Moreover, Add a adc_read_data() function for ADC data read directly. 2. When repetitive channel disable, npcx_set_adc_repetitive() sets ADC to one-shot mode. It makes ADC stop repetitively scan. This CL adds ADC stop before ADC setting in npcx_set_adc_repetitive() and moves the ADC mode setting to all channel disable. 3. THR_STS bit in THRCTS register is R/W1C. It will be clear by read-modify-write other bits. 4. ADC driver shared the same IRQ. Add event enable check for different ADC events. BRANCH=none BUG=b:167319238 TEST=pass "make buildall" TEST= 1. enable ADC repetitive mode 2. read ADC data by console command "ADC" 3. check whether the ADC repetitive mode works correctly 4. toggle ADC channel enable for repetitive mode 5. check whether another channel works correctly Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Ie9183163de49235f551218af93ddd75ea87d7af2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2409718 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* driver/it8xxx2: change Rd_DB to Rd_5.1k in EC hibernateRuibin Chang2020-09-251-2/+2
| | | | | | | | | | | | | | | | | | | We change Rd_DB to Rd_5.1k in EC hibernate, so the cc voltage level won't false trigger chip H1 when there is nothing attached on c port. BUG=b:167937680 BRANCH=none TEST=on board asurada and it81202_evb, in EC hibernate mode: 1.can wakeup by AC plug in, then pd state to SNK_READY. 2.Rd_5.1k power consumption is more 1.5uA than Rd_DB Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: If670e65bfed864ca9b1ca97ee66957a5e11accaa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2413190 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Bloonchipper: Reduce usart transport's response size to 0x100Bhanu Prakash Maiya2020-09-251-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Bloonchipper firmware uses usart_host_command.c to communicate with Zork's AP. On AMD SoC we found there is a 256 byte UART FIFO limitation with Designware's UART IP. Typically DMA should have solved this issue but looks like Picasso and Dali, UART DMA is not working at expected. This is causing timeout issues with EC responses > 256 bytes. This patch will limit the response size to 256 bytes which ensures that AP RX packets always stay within FIFO limits. Currently UART based host command transport is only used by FPMCU Dragonclaw STM32 design. BRANCH=none BUG=b:160208269 TEST=1. Run bloonchipper binary on Zork FPMCU devices. 2. Check PCO/DALI do not throw UART DMA overrun interrupt. Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@chromium.org> Change-Id: I0b99d25cf7d2dd163d05c35585064ad5e61a91ee Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428203 Commit-Queue: Bhanu Prakash Maiya <bhanumaiya@googlers.com> Tested-by: Bhanu Prakash Maiya <bhanumaiya@googlers.com> Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@googlers.com> Auto-Submit: Bhanu Prakash Maiya <bhanumaiya@googlers.com>
* it83xx/adc: adjust ADC read timeout to 1ms.Dino Li2020-09-243-7/+16
| | | | | | | | | | | | | | | | | | | | | Voltage comparator has about 73us conversion time, and ADC read channel has about 122 us conversion time. ADC engine will convert each channel at a time (comparators and ADC read channel) and current timeout setting is 248us, so we might have a chance to trigger timeout if converting two comparators while EC starts ADC read channel. This change increased timeout to 1ms. BUG=b:164256608 BRANCH=none TEST=Verified that running 'ectool temps all' without error on drawcia x200. Change-Id: I803d3065a75adaee673a9724ec4fc2fd73da0c48 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2423663 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* it83xx: read_clear_int_mask() read and clear interrupt bit.Dino Li2020-09-245-17/+11
| | | | | | | | | | | | | | | | | | This change pulled the operation of interrupt disable into read_clear_int_mask(). Because riscv core supports instruction csrrc to atomic read and clear bit in CSR register. With this change, we won't need to separate operations of reading and clearing interrupt bit on riscv core. BUG=none BRANCH=none TEST=read_clear_int_mask() is able to disable interrupt and return saved interrupt bit on both nds32 and riscv cores. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I871aab747b950b7948cdeb7911fcf8c09d55df5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2419739 Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: add features, memory configuration and ID for npcx9CHLin2020-09-236-22/+163
| | | | | | | | | | | | | | | | | | To support npcx9, this CL defines the configurations of RAM/flash and features for npcx9m3f and npcx9m6f. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST=with related CLs, build and flash image on the npcx9 EVB. Make sure EC can boot up and chip/revision ID are correct. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Ie3b343368d13d7f20e3b8970048704c1d94793d2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402841 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx7: set code RAM size to actual code RAM sizePeter Marheine2020-09-231-4/+13
| | | | | | | | | | | | | | | | | | Munging the program flash size to account for the ROM header by default also affects the assumed size of code RAM, which causes problems with the MPU because it makes the code RAM region a weird size. Since we're not using all of the code RAM space but it remains a full 256k in size, explicitly set the code RAM size for the chips where we pretend program memory is smaller than it actually is. BUG=b:168732993 TEST=verified dalboz configures code RAM with size 256k BRANCH=zork Signed-off-by: Peter Marheine <pmarheine@chromium.org> Change-Id: I0ab0954bc8a433d0d7c0c85945b012d45cc225ea Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2417788 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* npcx: change registers and hwtimer to support npcx9CHLin2020-09-229-670/+1550
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL makes the following changes to support npcx9. 1. Split the CHIP_FAMILY specific register setting form register.h to register-npcx5.h and register-npcx7.h. 2. Add npcx9's specific register setting in registers-npcx9.h 3. In npcx9, all 16-bit timers are removed from ITIM module. Change the hwtimer driver to use 32-bit timer for npcx9. The table shows the supported and current use of ITIM modules in the system: NPCX5/7 NPCX9 Change-Id: I1d00cbb8d36bff37563cfeaf78e338286e779b00 -------------------|---------------------|--------------------| Supported ITIMs | ITIM16_1-ITIM16_6 | ITIM32_1-ITIM32_6 | | ITIM32 | | -------------------|---------------------|--------------------| System tick timer | ITIM32 | ITIM32_6 | -------------------|---------------------|--------------------| Event timer | ITIM16_1 | ITIM32_1 | -------------------|---------------------|--------------------| Watchdog timer | ITIM16_5 | ITIM32_5 | BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST=boot up EC on the npcx7/npcx9 EVB. Check HOOT_SECOND function is working; EC watchdog resets after console command "waitms 4000" TEST=build and flash image for yorp, no symptom occurred. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Ibf0fa5fa44590de6bb3e1bff677f40aafd70b556 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402840 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* chip/it83xx/gpio: correct bit settingRuibin Chang2020-09-211-1/+1
| | | | | | | | | | | | | | | | | The cc2 bit field of CCCSR was repeated setting twice, so I correct one of setting to cc1. BUG=none BRANCH=none TEST=on board it8xxx2_evb, check CCCSR register value by console Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I51b914a2dacefb2c5ed3b6c2be221d95f5724ce3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2417778 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* stm32g4: Update dma channels for USARTScott Collyer2020-09-081-6/+6
| | | | | | | | | | | | | | | | This CL adjusts the DMA channel assignment for the USART that's used for EC console. BUG=b:148493929 BRANCH=None TEST=verfied ec console works on quiche Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I87aecdbc16667adc87e15f0158b71cfa39c706c6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213941 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx: i2c: Don't set ACK when using FIFO modeCHLin2020-09-081-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | In the single-byte mode, the I2C driver sets ACK bit in the SMBnCTL1 register to NACK the last byte when receiving data. In the FIFO mode, it sets the LAST bit in the SMBnTXF_CTL register in most of the protocol except "receive byte" and "read byte" protocols. (In these two protocols, both LAST and ACK bit are set.) In the normal case, there is no problem to set them together. However, it was observed in b:163076059 that the ACK bit is not cleared after a transaction when the I2C bus encounters an error. This CL changes the I2C driver to set the ACK bit only when it runs on the single-byte mode. BRANCH=none BUG=b:163076059 TEST=pass "make buildall" TEST=test test "read byte" and "receive byte" protocol on EVB about 500 thousands of transactions. test=build and flash image on yorp, check yorp can boot up to OS and there is no I2C error msg in the EC console. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Ife31d6e35caa9ccbb108571a887c4fab4d802406 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2393404 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* chip/mt8192_scp: remove chip_disable_irqTzung-Bi Shih2020-09-031-12/+8
| | | | | | | | | | | | | Disabling INTC IRQ in runtime is unstable in MT8192 SCP. BRANCH=none BUG=b:163682416 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I2817cd14be2f7d9188c188405b79acb2a2d5504d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2377046 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/i2c: enable 400kHz timing registers for port A/B/CDino Li2020-09-021-42/+78
| | | | | | | | | | | | | | With this change, port A/B/C will use timing registers to config clock frequency of 400kHz. BUG=b:163384683 BRANCH=none TEST=tlow meet timing when port speed configuration is 400kHz Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id4fafafa021966acc33711dd454c109b3bf93766 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2359623 Reviewed-by: Diana Z <dzigterman@chromium.org>
* stm32g4: Specify correct ARM core and CPU flagsScott Collyer2020-08-311-1/+2
| | | | | | | | | | | | | | | | The only change required for build.mk is to specify the correct ARM core and machine instruction set. BUG=b:148493929 BRANCH=None TEST=verfied image builds successfully. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I267dfbe54de153c8687f5048fdcccf65ac15678f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195551 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32g4: Add flash support for stm32g4 chip familyScott Collyer2020-08-314-83/+91
| | | | | | | | | | | | | | | | | | | This CL adds support for flashing stm32g4. The L4 family has the same flash module and so that was used as basis for G4 driver. This CL renames the l4 flash driver to capture this commonality. In addition, the flash register definitions in G4 registers file was updated appropriately. Previously, this section matched F4 requirements. BUG=b:148493929 BRANCH=None TEST=verfied usb-ep fw update completes successfully Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I6cc818c6329524924534b0566bd9d24145c86c72 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195547 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org>
* stm32l4: Refactor to use page instead of bank notationScott Collyer2020-08-312-31/+77
| | | | | | | | | | | | | | | | | | The L4 and G4 family share the same flash peripheral block. Therefore, the G4 can share the L4 driver. This CL adds macros which more closely track the TRM description of the flash module, especially w.r.t pages. There is no functional change for the L4 driver. BUG=b:148493929 BRANCH=None TEST=make -j BOARD=stm32l476g-eval is successful Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ie2c16ef2b8fa0e35f5945fb124765039f8ea22c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2376388 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Fix build issue with i2c driverScott Collyer2020-08-292-2/+1
| | | | | | | | | | | | | | | This CL fixes 2 minor issues which with the i2c driver file. BUG=b:148493929 BRANCH=None TEST=verfied honeybuns builds correctly. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Ide6aafd4e4296891579fa138ec0d3e54a4ed9c6d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2376828 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* it83xx/system: Don't disable DBGR in system resetDino Li2020-08-272-9/+21
| | | | | | | | | | | | | | | | | | | | | | | Our current implementation will disable DBGR (debug mode) in system reset, but this will break flashing sequence. So we make a change to ensure flashing won't be broken under the above situation. Note: DBGR is only applied to flashing sequence, a HW reset after flashing will disable DBGR and allow normal system reset. We also enable wait flashing sequence in this CL, so EC can check if there’s a DBGR flag during initialization and proceed afterwards. BUG=b:118584434, b:165515400 BRANCH=none TEST=- The soft reset still works after flashing. - EC can be flashed even if it is in continuous reboot loop. Change-Id: I9cea2c4fef74de7afcffb203e02f79cb18a4c5bf Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1243878 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* chip/mt8192_scp: do not handle pending IPI interruptsTzung-Bi Shih2020-08-261-7/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to handle pending IPI interrupts. Reasons: - Interrupts are level trigger in MT8192 SCP. As long as the source interrupts persist, RV33 handles them eventually. - task_trigger_irq() fires an additional GIPC_IN0 IRQ. The former one will clear the interrupt source by writing GIPC_IN_CLR. When the latter one is handling, RV33 crashed due to it cannot find the corresponding interrupt source. BRANCH=none BUG=b:163682416 TEST=1. cat - <<EOF >test.sh echo stop >/sys/class/remoteproc/remoteproc0/state while :; do dmesg -C echo start >/sys/class/remoteproc/remoteproc0/state sleep 1 if dmesg | grep -q 'rpmsg send timeout'; then break fi echo stop >/sys/class/remoteproc/remoteproc0/state done echo stop >/sys/class/remoteproc/remoteproc0/state EOF 2. sh test.sh Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I2cc89a258a4ce218389799bbe1101ffc1375af8a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2373846 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* chip/mt8192_scp: do not switch INTC_IRQ_EN in runtimeTzung-Bi Shih2020-08-261-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MT8192 SCP's interrupt handling is a long path. +----------+ +----------+ +----------+ | INTC | ---> | GVIC | ---> | RV33 | +----------+ +----------+ +----------+ ^ ^ ^ ^ INTC_IRQ_EN VIC_EN MIMASK mie When turning off INTC_IRQ_EN, it is possible GVIC has already latched the interrupt. As a result, RV33 receives the spurious interrupt. MT8192 SCP has no effective way to clear the unwanted interrupt. Thus, do not switch INTC_IRQ_EN in runtime. Disable all interrupts (via mie) instead. BRANCH=none BUG=b:163682416 TEST=1. cat - <<EOF >test.sh echo stop >/sys/class/remoteproc/remoteproc0/state while :; do dmesg -C echo start >/sys/class/remoteproc/remoteproc0/state sleep 1 if dmesg | grep -q 'rpmsg send timeout'; then break fi echo stop >/sys/class/remoteproc/remoteproc0/state done echo stop >/sys/class/remoteproc/remoteproc0/state EOF 2. sh test.sh Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I494330f8d00744c305be7beb19ca6b7084512a72 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2373845 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* chip/mt8192_scp: add address location of MIEMASK_G0Tzung-Bi Shih2020-08-261-0/+1
| | | | | | | | | | | BRANCH=none BUG=b:163682416 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I38e717a4a88d80a6c22ffd74b38904fa2e38fa73 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2352955 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* it83xx: fix incorrect reset cause when boot from z-stateTing Shen2020-08-252-3/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the following features to support z-state for Asurada. 1) Call chip_save_reset_flags() before entering board_hibernate_late() to make sure the hibernate flag saved before ec powered off. 2) Handle the second ec reset correctly if CONFIG_BOARD_RESET_AFTER_POWER_ON enabled. BUG=b:163963220 TEST=Check the reset cause under following cases: 1) boot from z-state -> reset-pin power-on hibernate initial-pwr 2) boot from cutoff -> reset-pin power-on initial-pwr 3) `ecrst pulse` in cr50 console -> reset-pin power-on initial-pwr BRANCH=none Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I176075ea2b3f6b2abbfe22e47f3019ee23af57a0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2371751 Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* usbc: remove PD_EVENT_SM in favor of task_wakeJett Rink2020-08-211-1/+1
| | | | | | | | | | | | | | | | We have used both methods of waking up the PD tasks to process the next state: PD_EVENT_SM and TASK_EVENT_WAKE. They effectively do the same thing and it is more straightforward to only have one way to wake the task up with the sole purpose of re-evaluating the current state. BRANCH=none BUG=none TEST=No regressions on GRL testing. Signed-off-by: Jett Rink <jettrink@chromium.org> Change-Id: I0fa79b82223e6b97eede4130480156949d79f365 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2363466 Reviewed-by: Edward Hill <ecgh@chromium.org>
* it83xx/spi: change configuration to IS_ENABLED() styletim2020-08-191-69/+67
| | | | | | | | | | | BUG=none BRANCH=none TEST=No error on the command of get EC protocol info. Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I08d87bd20e60520c891f1b99d78ff91c1e89b2cb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2359613 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx7: introduce new chip variant npcx7m7fcCHLin2020-08-194-10/+23
| | | | | | | | | | | | | | | | | | | | | | | Add the following changes: 1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to define what (RAM, flash, features...) are supported in npcx7m7fc. 2. add the chip id and chip revision id of npcx7m7fc BRANCH=none BUG=b:163910671 TEST=pass "make buildall" TEST=with related CLs, change CHIP_VARIANT to npcx7m7fc in board/npcx7_evb/build.mk; flash image and run on the internal testing board of npcx7m7fc; make sure the EC can boot up; check the chip ID and chip revision ID are correct by console command "version". Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: Ibef17148eeba71bbbb63145064a5fa398c0118dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355156 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* Replace __attribute__((noreturn)) with noreturnTom Hughes2020-08-1711-18/+34
| | | | | | | | | | | | | | | _Noreturn was added in C11 and the convenience macro "noreturn" is specified by stdnoreturn.h: https://en.cppreference.com/w/c/language/_Noreturn. BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I30361bb5290cea1c776a7356f7e3a68edf1f8e39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324816 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* Clean up: set embedded flash clock 48MHz as defaultRuibin Chang2020-08-172-0/+2
| | | | | | | | | | | | | | | | For chip it8xxx2 series and it8320dx, we set embedded flash clock 48MHz as default. BUG=none BRANCH=none TEST=build all Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I100d70fbf80430ae98fa14c557886c4a37d8b93a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355164 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* task: Change mutex_lock() assertEdward Hill2020-08-152-11/+3
| | | | | | | | | | | | | | | | | | | Instead of asserting that task_start() has not been called, just return without doing any locking. This avoids the need to fix every caller of mutex_lock() to check task_start_called(). BUG=b:164461158 BRANCH=none TEST=Esc+F3+Power enters recovery, does not assert. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ic157d7e7041185a67f257f0f5710fd02e45cd77f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2357496 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* it83xx/spi: enable rx valid length interruptDino Li2020-08-143-0/+50
| | | | | | | | | | | | | | | | | | | | | Enable IT83XX_SPI_RX_VALID_INT which can obtain data length field of host requested. When received data to reach, Rx valid interrupt will be fired then start to parse. Instead of waiting for Rx 256 bytes reach interrupt method, this is effectively saving time to complete once transaction. BUG=b:160662061; b:161509047 BRANCH=none TEST=Boot to kernel with it81202 on asurada. No error on the command of get EC protocol info with 1MHz clock frequency. Change-Id: Ib56e3034d3ee39fa64818b95747eb7e9e5821294 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076826 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org>
* it83xx/adc: Enable automatic hardware calibrationDino Li2020-08-142-0/+3
| | | | | | | | | | | | | | We missed it when ADC accuracy initialization, let's fix it. BUG=b:164011390 BRANCH=none TEST=ADC accuracy is in +/- 4LSB. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id40adbdc6823fbf3db506681ce4bff6a2f32b843 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355166 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Parker Lin <parkerlin@google.com>
* COIL: change usage of sanityDaisuke Nojiri2020-08-141-1/+1
| | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "sanity" with inclusive alternatives. BUG=b:163885307 BRANCH=None TEST=make -j buildall TEST=grep -ir sanity Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I487a50999d506a0337f1d3fbe173f193e5e4098a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2353516 Reviewed-by: Sam Hurst <shurst@google.com>
* npcx: add support for rom resident sectionsKeith Short2020-08-132-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC images are copied in full from flash to RAM. When the code RAM size is smaller than 1/2 the flash size, the EC image size is limited to the code RAM size, leaving unused flash space. Create a new linker section .init_rom used to store data objects that are single use in the previously unused flash area. Data objects can be used at runtime by copying into RAM using the flash_read() function. This change is tied to the NPCX flash layout, with asserts to ensure builds fail if the CONFIG_CHIP_INIT_ROM_REGION is not supported by the chip. CLs that enable CONFIG_CHIP_INIT_ROM_REGION should not be merged until the predecessor CL:2325764 is available in CPFE images. BUG=b:160330682 BRANCH=none TEST=make buildall TEST=With debug code, use the _init_rom macro and validate the data can be read using flash_read(). TEST=Using hex editor, verify .init_rom section located at 192K boundary and unused bytes are filled with 0xFF. TEST=compare_build.sh passes when run against waddledoo (npcx, cortex-m) Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ia0785798fd1938ad6a1c254a070b219027ee82a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311268 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org>
* stm32g4: Add I2C supportScott Collyer2020-08-132-11/+472
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the i2c driver for stm32g4 chip family. The i2c block for stm32g4 is very similar to that of stm32l4 chip family. The g4 driver is mostly copied from the L4 version of the i2c driver. However, the driver only currently supports master mode. BUG=b:148493929 BRANCH=None TEST=run i2scan on EC console > i2cscan Scanning 0 usbc................. 0x18. 0x19. 0x1a. 0x1b. 0x1c. 0x1d. 0x1e. 0x1f. 0x20. 0x21. 0x22. 0x23. 0x24. 0x25. 0x26. 0x27........................... 0x42.............................. 0x60....................... Scanning 1 usb_mst. 0x08. 0x09. 0x0a. 0x0b. 0x0c. 0x0d. 0x0e. 0x0f. 0x10. 0x11. 0x12. 0x13. 0x14. 0x15. 0x16. 0x17... 0x1a........................... 0x35............ 0x41......... 0x4a. 0x4b...................... 0x61...................... Scanning 2 eeprom......................................... 0x30................................ 0x50....................................... Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: Id8b7472e579bae17360a0122fe2b12a333139cfa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2161580 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* stm32g4: Fix max clock freq and flash wait stateScott Collyer2020-08-131-5/+5
| | | | | | | | | | | | | | | | | | | | | The clock frequency macro added in previous CL was missing the '0'. This CL fixes that error and makes a minor change to how the flash wait state value is configured. Previously, setting of the wait state field was disabling instruction/data cache until it was restored in the next instruction. This results in swd debugger not remaining attached. BUG=b:148493929 BRANCH=None TEST=verified console is working and debugger remains attached after setting wait state to the correct value. Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I65e3a22e36de0bbf14926e5687a995b7e5717e7f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340695 Commit-Queue: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* chip/mt8192_scp: enlarge the stack size of idle taskTzung-Bi Shih2020-08-121-1/+1
| | | | | | | | | | | | | | | | | | | Enlarges the stack size of idle task from 256 to 640. BRANCH=none BUG=b:163459890 TEST=$ r() { echo stop >/sys/class/remoteproc/remoteproc0/state echo start >/sys/class/remoteproc/remoteproc0/state } $ r $ r Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I6d887262f39ff32bdb1b86aba59759917a0a95d1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2351640 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/mt8192_scp: add missing guard for TASK_HOSTCMDTzung-Bi Shih2020-08-121-0/+2
| | | | | | | | | | | | | BRANCH=none BUG=b:160382789 BUG=b:163459890 TEST=1. remove hostcmd task from ec.tasklist 2. make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ia92abeccd5fba8862563a200cbdcf4ce461f4106 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2351639 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-122-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. Add check for task_start_called() for NPCX flash_lock, I2C port_mutex, pwr_5v_ctl_mtx, STM32 bkpdata_write_mutex. This was submitted CL:2309057, reverted CL:2323704, submitted CL:2335738, reverted CL:2341706. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I0aadf29d073f0d3d798432099bd024a058332412 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2343450 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Revert "task: Fix mutex_lock() assert (reland)"caveh jalali2020-08-071-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8d46141f4d45c65712a9ca7509b7b60128fa4d89. Reason for revert: getting EC boot loop on volteer: (note that you have to flash EC-RO to get this) 20-08-07 00:22:33.520 --- UART initialized after reboot --- 20-08-07 00:22:33.531 [Image: RO, volteer_1.1.9999-4284ce1 @caveh] 20-08-07 00:22:33.531 [Reset cause: reset-pin] 20-08-07 00:22:33.531 [0.005149 KB boot key mask 0] 20-08-07 00:22:33.543 [0.005438 init buttons] 20-08-07 00:22:33.543 [0.005669 VB Main] 20-08-07 00:22:33.543 [0.005872 VB Ping Cr50] 20-08-07 00:22:33.543 [0.007148 hash start 0x00040000 0x0002f61c] 20-08-07 00:22:33.833 [0.300169 hash done e4ddc3d0ffd015db085389d94faa38d3922e42290b6887baa8de3067ce846c13] 20-08-07 00:22:33.833 [0.300289 VB Verifying hash] 20-08-07 00:22:33.833 ��������������������������������EC\0 \0 �������S��O�8Ӓ.B) h����0g΄l[0.317577 VB Received 0xec00] 20-08-07 00:22:33.850 [0.317899 Jumping to image RW] 20-08-07 00:22:33.850 20-08-07 00:22:33.850 ASSERTION FAILURE '!in_interrupt_context() && task_start_called()' in mutex_lock() at core/cortex-m/task.c:868 20-08-07 00:22:33.861 20-08-07 00:22:33.861 === HANDLER EXCEPTION: 00 ====== xPSR: 0000000a === 20-08-07 00:22:33.861 r0 :00000364 r1 :100b6815 r2 :100b72ab r3 :100956bd 20-08-07 00:22:33.873 r4 :dead6663 r5 :00000364 r6 :200c1c20 r7 :00000001 20-08-07 00:22:33.873 r8 :00001388 r9 :100b4108 r10:100b4158 r11:00000013 20-08-07 00:22:33.884 r12:10095811 sp :200c0320 lr :200c1c20 pc :200c14f8 20-08-07 00:22:33.884 20-08-07 00:22:33.884 cfsr = 0, shcsr = 70000, hfsr = 0, dfsr = 0 20-08-07 00:22:33.884 20-08-07 00:22:33.884 =========== Process Stack Contents =========== 20-08-07 00:22:33.889 00000000: 100cfc00 00002a3d 00002751 00002731 20-08-07 00:22:33.901 00000010: 00002741 00002711 000027e1 00002791 20-08-07 00:22:33.901 00000020: 000027a1 000027b1 00002771 000027c1 20-08-07 00:22:33.901 00000030: 00002721 00002781 00002761 000027d1 20-08-07 00:22:33.906 20-08-07 00:22:33.906 Rebooting... 20-08-07 00:22:33.996 20-08-07 00:22:33.996 20-08-07 00:22:33.996 --- UART initialized after reboot --- Original change's description: > task: Fix mutex_lock() assert (reland) > > mutex_lock() must not be used in interrupt context. Add an assert > to catch this. > > Also assert task_start_called() since task ID is not valid > before this. > > Also remove an old assert since comparing id with TASK_ID_INVALID > doesn't make sense. > > This was first submitted as CL:2309057, then reverted by CL:2323704 > because it broke jump to RW (b/162302011). Fix this by adding check > for task_start_called() to chip/npcx/flash.c and common/i2c_master.c. > > BUG=b:160975910 > BRANCH=none > TEST=boot AP, jump to RW > > Signed-off-by: Edward Hill <ecgh@chromium.org> > Change-Id: I070a265a95d2128643b536814e608509d81adbe3 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738 > Reviewed-by: Raul E Rangel <rrangel@chromium.org> > Reviewed-by: Denis Brockus <dbrockus@chromium.org> Bug: b:160975910 Change-Id: I9e37b1eac7344cddbd756fb45b130d7e0aee661b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2341706 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-061-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. This was first submitted as CL:2309057, then reverted by CL:2323704 because it broke jump to RW (b/162302011). Fix this by adding check for task_start_called() to chip/npcx/flash.c and common/i2c_master.c. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I070a265a95d2128643b536814e608509d81adbe3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* chip/npcx/lpc: Read HIKMST before HIKMDIRaul E Rangel2020-08-061-1/+9
| | | | | | | | | | | | | | | | | Reading HIKMDI causes the IBF flag to deassert and allows the host to write a new byte into the input buffer. So if we don't capture the status before reading HIKMDI we will race with the host and get an invalid value for HIKMST.A20. BUG=b:162539945, b:157617092, b:159282882 BRANCH=none TEST=Boot ezkinil and make sure keyboard still functions. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia8dcd18e3de31b4fa8c1742c7604d5c39e80dc51 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2341090 Commit-Queue: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* chip: support dynamic hibernate_wake_pins configTing Shen2020-08-064-0/+20
| | | | | | | | | | | | | | | | Add CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC to let board config their wake pins at runtime. BUG=b:162814191 TEST=make BRANCH=master Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Iae2072ec7239a0daa84222c23733b90153e732f1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340730 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* ec: change usage of dummySam Hurst2020-08-0547-116/+116
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* it83xx: Add support for interrupt and 1.8v selection of GPJ7Dino Li2020-08-043-2/+7
| | | | | | | | | | | | BUG=b:162805450 BRANCH=none TEST=not yet Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ie1525b8a0f67a4700649163b536d09bef9a9671a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335518 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* chip/mt8192_scp: don't unset the THRI flag unless we are in the UART ISRTzung-Bi Shih2020-08-021-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Interrupt mechanism of MT8192 SCP has 3 tiers: INTC, global VIC, local VIC (in RV33). +------+ +-------------+ +----------------+ | | | | | | UART TX -----| |--GROUP 0 --| | | | UART RX -----| INTC |--GROUP 1 --| Global VIC | | Local VIC | Timer 0 -----| |--GROUP 2 --| | | | Timer n -----| | . | (MIEMS, |-----| (INTC_IRQ_OUT, | . | | . | MICAUSE, | | INTC_IRQ_...) | . | | . | MIXXXX...) | | | GIPC 0 -----| |--GROUP 14--| | | | . +------+ +-------------+ +----------------+ GVIC latches from INTC at a time and notifies LVIC if any group is asserted. For example, suppose UART TX corresponds to group 12 and GIPC 0 corresponds to group 7: (1) GIPC 0 and UART TX are asserted. (2) GVIC notifies LVIC about the interrupt. (3) RV33 finds group 7 and group 12 (from INTC_IRQ_OUT) are asserted. Note that it is a fatal error if RV33 cannot find the corresponding groups in (3). GVIC caches the group 7 and group 12 until RV33 writes to bit 7 and bit 12 of MIEMS. Even though the interrupt source is de-asserted, the GVIC cache won't get updated. The most suggested way to handle interrupt in RV33: batch handle them. However, EC OS doesn't handle multiple interrupts at a time. EC OS handles 1 interrupt, acknowledges by writing 1 bit in MIEMS, and sees if further interrupts from GVIC. UART TX interrupt can be easily cleared by calling cflush() in anywhere. To avoid the interrupt source of UART TX being cleared in other ISR, don't unset the THRI flag unless we are in the UART ISR. BRANCH=none BUG=b:157541273 TEST=call cflush() in any ISR Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I2fab7308edce386ea65d0d45e39805d8cc7f4857 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2331984 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/it83xx, it8xxx2: implement detect cc disconnection interrupt for SRC roleRuibin Chang2020-07-313-22/+26
| | | | | | | | | | | | | | | | | | | | Implement detect cc disconnection interrupt for source. When TCPC detect SNK/audio/debug device plug out (cc lines open), TCPC can interrupt pd task to update cc state. BUG=b:160548079 BRANCH=none TEST=test on board reef_it8320, it81202_pdevb with TCPMv1, TCPMv2. Connect to dongle, adapter and DRP, check 1.Plug in/out interrupt fire correctly. 2.Power role swap can state to SRC_READY and SNK_READY. 3.When partner disconnect, we discharge Vconn within tVconnOFF(35ms). Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Change-Id: I58bc8a5a9289df4ea4e8b3efec000d3a9ab1cb5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2294626 Reviewed-by: Jett Rink <jettrink@chromium.org>
* stm32g4: Set uart frequency and enable clocks for stm32g4Scott Collyer2020-07-311-3/+3
| | | | | | | | | | | | | | | | This CL adds changes to enable clocks and configure the uart speed for stm32g4 chip family. BUG=b:148493929 BRANCH=None TEST=verfied that the GPIO, clocks, and EC console over LPUART Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I5600ed64867192fe77fd85fc3dbc0a63f912d738 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2195550 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
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