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* mec1322: hibernation supportstabilize-5339.BVic (Chun-Ju) Yang2014-01-282-4/+160
| | | | | | | | | | | | | | | This adds hibernation support. The chip can be waken by either GPIO or a timer. The maximum delay allowed is ~2 hours. BUG=chrome-os-partner:24107 TEST=hibernate and wake by GPIO TEST=hibernate and wake by timer BRANCH=None Change-Id: I1e064638a5008894a002a06a738bf6104f18636d Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181202 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Use EMI module for port 80Vic (Chun-Ju) Yang2014-01-171-6/+13
| | | | | | | | | | | | | | | EMI module is the only LPC module suitable for port 80 implementation, and thus let's move it to 0x80. Consequently the EMI mapped memory is moved to 0x82-0x87. BUG=chrome-os-partner:24107 TEST=Write to port 80 and see the data printed to console BRANCH=None Change-Id: I7d749650d6d109af2941a1db6e6c4a32e7482f61 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182796 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: disable host write to mapped memoryVic (Chun-Ju) Yang2014-01-171-1/+1
| | | | | | | | | | | | | | EMI module has the ability to set different read and write ranges. Let's disable write on mapped memory. BUG=chrome-os-partner:24107 TEST=Write to mapped memory has no effect BRANCH=None Change-Id: I88654bde9208376103d3c084ee54991d886ea4cc Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182795 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* lm4: move I2C transfer state machine to interrupt handlerRandall Spangler2014-01-161-184/+183
| | | | | | | | | | | | | | | | | | | | | | This significantly decreases the task swapping overhead when doing many transfers. Also fix a bug where on error, i2c_xfer() would issue a stop condition, but not actually wait for it to complete before returning; this could interfere with the next transfer in a back-to-back scenario. BUG=chrome-os-partner:25015 BRANCH=lm4 (more specifically, rambi and derivatives) TEST=battery command should show the same info as before i2cscan should show devices at bus 0 0x12, 0x16, bus 5 0x98 no charger errors on boot Change-Id: I2195f0f9800b03a54fa33170dbae6705382578c7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182503 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
* ite: Watchdog module addedAlec Berg2014-01-152-0/+101
| | | | | | | | | | | | | | | | | Watchdog module added. Off by default because of following limitations: - When programming, the WD fires, and programming fails. For now, you have to program twice. BRANCH=none BUG=chrome-os-partner:23575 TEST=Manually wrote in a while(1); and made sure watchdog warning triggers first, prints IPC register, and then soon after the watchdog timer resets the chip. Signed-off-by: Alec Berg <alecaberg@chromium.org> Change-Id: Ia83f58f3ae108f755d2f139ada22a22e2fbdc2fa Reviewed-on: https://chromium-review.googlesource.com/177397 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ite: Added system reset and reset causesAlec Berg2014-01-142-1/+70
| | | | | | | | | | | | | | | Added system reset and reset causes for ITE chip. The only reset causes available on this chip are watchdog reset or power on reset. BRANCH=none BUG=none TEST=Used reboot console command with various args and verified reset cause was recorded correctly on next boot. Change-Id: Ie65f1e8f2b98c1e614b5c1d8bcbe9b3000ed9590 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179539 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Refine reset cause detectionVic (Chun-Ju) Yang2014-01-112-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | The VBAT POR indication is unreliable for detecting a power-on reset, and thus we often see "unknown" reset cause when we should see "power-on". A better indication is to check for VCC1 POR, which manifests by clearing watchdog count. The catch is that we still cannot tell power-on reset from reset-pin reset. Also, to distinguish soft/hard reset from actual watchdog reset, we need to explicitly save soft/hard reset flag before triggering watchdog reset. BUG=chrome-os-partner:24107 TEST=Power cycle EVB and see 'power-on' reset cause. TEST='reboot' and see 'soft' reset cause. TEST='reboot hard' and see 'hard' reset cause. TEST='waitms 2000' and see 'watchdog' reset cause. BRANCH=None Change-Id: I0075f5bf5cdb032d206c4a53c586b75b69093235 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182120 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Use internal SCI pin controlVic (Chun-Ju) Yang2014-01-092-3/+22
| | | | | | | | | | | | | | | Instead of requiring a GPIO definition, default to using the internal SCI pin control. BUG=chrome-os-partner:24550 TEST=Trigger SCI and verify with logic analyzer BRANCH=None Change-Id: I13ac3b8f1031d3c56ea0b8f6a6ed0c1aa4e77bb1 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182010 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Convert vboot hash calculation from task to deferred functionRandall Spangler2014-01-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vboot hash calculation takes ~350 ms during EC boot. Since the hash task is higher priority than the hook task, this starves all the hooks during boot. We could, in theory, fix that simply by swapping the priority of the hook and hash tasks. But then watchdog detection (in the hook task) wouldn't detect hangs in the hash task. A better fix (implemented here) is to convert the hashing operation to a series of deferred function calls. This gets rid of the hash task entirely, and allows all pending hooks and other deferred function calls to take place between each chunk of hashing. On STM32-based boards, we need to bump up the hook task stack size, since hashing is called from several layers deep in the hook task instead of at the top of its own task, but this is still a net win of several hundred bytes of SRAM. BUG=chrome-os-partner:24892 BRANCH=rambi TEST=Boot EC; look for "hash start" and "hash done" debug output. 'taskinfo' shows at least 32 bytes of unused stack for HOOKS task. 'hash ro' runs properly from EC console. Change-Id: I9e580dc10fc0bc8e44896d84451218ef67578bbe Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181954
* Remove old TODO comment in emulator UART moduleVic (Chun-Ju) Yang2014-01-091-4/+1
| | | | | | | | | | | | | | | | Now that we handle all UART input from interrupt context, we shouldn't need to guard input buffer with mutex lock. Removing the stale TODO comment and adding an assertion to ensure this argument is correct. BUG=chrome-os-partner:23804 TEST=make buildall BRANCH=None Change-Id: If61eed4329a782b80fe8b16667bddaae8464620d Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181722 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ite: WORKAROUND reduce data SRAM to 8kBVincent Palatin2014-01-081-1/+1
| | | | | | | | | | | | | | | | | | | On the IT8380, we should be able to map 16kB of SRAM to use as data memory (aka DLM), but sometimes the 2 top 4k pages seem to be mapped differently (ie not to SRAM, they do not retain writes ...). As we have no documentation on that topic, for now use 8kB of DLM for now. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23575 TEST=build and run IT8380 dev board. Change-Id: I4ed452f27e9c457e7ac717b82580781ca506b0d8 Reviewed-on: https://chromium-review.googlesource.com/179322 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* emulator: Fix a bug that jump tag is overwrittenVic (Chun-Ju) Yang2014-01-081-5/+0
| | | | | | | | | | | | | | | | | The mock system_usable_ram_end() always returns the same address. However, this causes the second jump tag to overwrite the first one. Also, now that the jump data is properly placed, we can actually remove the mock implementation. BUG=chrome-os-partner:19235 TEST=Add two jump tag and check the first one is not overwritten. BRANCH=None Change-Id: If868895a7c028dd25399adb69e9708de45c84f10 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181745 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ite: Add initial support for ITE IT8380 chipVincent Palatin2014-01-0810-0/+1684
| | | | | | | | | | | | | | | | | | | | | | | | | Initial support for the ITE IT8380 chip with the following peripherals : - 8250-like UART module. - HW timer (with a 128-us tick period). - GPIO with pins initialization and edge interrupt support. other functions are stubbed. - Clock : basic fixed frequency setup only. It also add the dev board configuration as a test vehicle. Signed-off-by: Alec Berg <alecaberg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23575 TEST=make BOARD=it8380dev on IT8380 dev board, use the EC serial console, use gettime from console. Change-Id: Id4bf37d1beb21d1a4bee404c9a0bc500025fe787 Reviewed-on: https://chromium-review.googlesource.com/175481 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* Add squawks boardRandall Spangler2014-01-081-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement LED color policy (crosbug.com/p/23957) Update battery vendor information (crosbug.com/p/24684) BUG=chrome-os-partner:24885 BRANCH=rambi TEST=manual system on, lidclose -> power LED off system on, lidopen -> power LED on system suspended -> power LED blinks green every 2 sec system suspended, lid closed -> power LED off system off -> power LED off plug AC in, battfake 95 -> charging LED green plug AC in, battfake 94 -> charging LED orange unplug AC, battfake 10 -> charging LED off unplug AC, battfake 9 -> charging LED blinks orange battcutoff -> after a few sec, system powered down plug back in AC -> system comes back on charger -> I_in < 1700 Change-Id: I89161e2c024d85197b8612a40a61dd50c106549e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181755
* Remove duplicate KBD_IRQ_L signalsRandall Spangler2014-01-081-12/+0
| | | | | | | | | | | | | The SERIRQ signal will now be high-Z on the EC, which removes a leakage path. This requires the BIOS to use PM3 for its keyboard IRQ. BUG=chrome-os-partner:24424 BRANCH=rambi TEST=boot system; keyboard still works Change-Id: I0acf425125ced11a9ef6da58ee49979b83c92d5c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181718
* Process emulator UART events in interrupt contextVic (Chun-Ju) Yang2014-01-061-11/+16
| | | | | | | | | | | | | | | | | Currently emulator UART input/output are processed in various context, including UART thread, individual tasks, and tests. By moving the processing to interrupt context, the way it works resemble real chips more. Also, this provides a cleaner cut between emulated UART device and UART processing code. BUG=chrome-os-partner:23804 TEST=make buildall BRANCH=None Change-Id: I58127e66f4058a68d37be9029e9ddbbd798381c6 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181590 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add interrupt support for emulatorVic Yang2014-01-061-1/+1
| | | | | | | | | | | | | | | | | | This provides us a way to inject interrupts during a test. If a test has interrupt_generator() defined, it will run in a separate thread. The generator can then trigger interrupts when it decides to. The current running task is suspended while emulator is executing ISR. Also fixes a bug that tasks run without scheduler notifying them during emulator start-up. BUG=chrome-os-partner:19235 TEST=Repeatedly run all tests. BRANCH=None Change-Id: I0f921c47c0f848a9626da6272d9040e2b7c5ac86 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/55671
* mec1322: Update pack scriptVic (Chun-Ju) Yang2013-12-271-39/+77
| | | | | | | | | | | | | | | | | This includes: - Reference to the boot ROM document - Update flags usage from the document - Command line argument support BUG=chrome-os-partner:24107, chrome-os-partner:24188 TEST=Pack and boot BRANCH=None Change-Id: I6f79ca94fbc10448e3a1c884a2d52fdf4abf266d Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180180 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add signing keyVic (Chun-Ju) Yang2013-12-272-0/+56
| | | | | | | | | | | | | | | | | | Adding two signing keys: - A dev key used to sign header. We have confirmation from Microchip that we can check in this key. - A key to sign payload. This can actually be an arbitrary key as long as the header and the payload are in sync. Adding a key here just for convenience. BUG=chrome-os-partner:24107 TEST=None BRANCH=None Change-Id: I5d7418a926047887c01cd0a334a041b18082f66e Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180835 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: ADC driverVic (Chun-Ju) Yang2013-12-204-0/+151
| | | | | | | | | | | | | ADC driver for MEC1322 with ADC interrupt support. BUG=chrome-os-partner:24107 TEST=Read single channel TEST=Read all channels BRANCH=None Change-Id: I89d196c7fd78e736575e2c368b65cfb1ec651004 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180832
* Move ADC console command to commonVic (Chun-Ju) Yang2013-12-203-51/+12
| | | | | | | | | | | | | | | | | | | We have three duplicated ADC read console command, and we are about to have the fourth. Let's consolidate them to a single implementation in common/. Note that we have to add a simple implementation of adc_read_all_channels() for LM4. BUG=chrome-os-partner:18343 TEST=Build all boards TEST=Read single channel TEST=Read all channels BRANCH=None Change-Id: I079c0b33ab6b81a188f309cf99875eb02e9d78a4 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180831
* cleanup: Remove checkpatch warningsRandall Spangler2013-12-1911-36/+34
| | | | | | | | | | | | | | | | This make minor syntactic changes and renames some camel-cased symbols to keep checkpatch from complaining. The goal is to reduce the temptation to use 'repo upload --no-verify'. This is a big furball of find/replace, but no functional changes. BUG=chromium:322144 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180495
* mec1322: handle dummy GPIO gracefullystabilize-springlte-5116.46.Bstabilize-5116.88.Bstabilize-5116.53.Bstabilize-5116.115.Bstabilize-5116.113.Brelease-R33-5116.BVic (Chun-Ju) Yang2013-12-171-11/+31
| | | | | | | | | | | | | | | | When a GPIO signal is defined by GPIO_SIGNAL_NOT_IMPLEMENTED, it should still be able to call various GPIO methods on that GPIO signal. Since __builtin_clz dies when the value passed in is zero, we need to check this before calling __builtin_clz. BUG=chrome-os-partner:24107 TEST='sysjump RW' and the system doesn't crash BRANCH=None Change-Id: I5025a2f218d549316fe096c07bd3c7207fe9dbc2 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180183 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: i8042 interfaceVic (Chun-Ju) Yang2013-12-172-0/+62
| | | | | | | | | | | | | This implements i8042 keyboard interface at LPC 0x60/0x64. BUG=chrome-os-partner:21407 TEST=Enable keyboard and keystroke from host ACPI commands. Short KSO pins and KSI pins, and read different key codes from host. BRANCH=None Change-Id: Ie4e5e236bdeefd7e44974f92fcbafab5e4af2b30 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179940
* rambi: Add duplicate GPIO outputs for proto 2.0 boardRandall Spangler2013-12-161-0/+12
| | | | | | | | | | | | | | | | | | | Proto 2.0 makes these changes: KBD_IRQ# moves from PM4 to PM3. EC_PWROK moves from PH2 to PJ1. Since PM3 and PJ1 are unused on proto 1.5, it's harmless to duplicate the current functionality on those outputs. We can remove the old outputs when we deprecate the 1.5 boards. BUG=chrome-os-partner:24424 BRANCH=none TEST=boot rambi Change-Id: Iff77651ef575a8405878fe75f025a0507b02b771 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180081 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Rename mixed-case config constantsRandall Spangler2013-12-169-33/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | This renames constants used in compiler conditionals to uppercase. BOARD_foo CHIP_foo CHIP_FAMILY_foo CHIP_VARIANT_foo CORE_foo Mixed-case constants are still defined by the makefile, but are now no longer used. I will make one more pass in a week or so to catch any that are part of someone else's CL, since otherwise this change might silently merge correctly but result in incorrect compilation. Then I will remove defining the mixed-case constants. BUG=chromium:322144 BRANCH=none TEST=Build all boards. Also, "git grep 'BOARD_[a-z]'" should return no results (similarly for CHIP, CORE, etc.) Change-Id: I6418412e9f7ec604a35c2d426d12475dd83e7076 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179206 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mec1322: ACPI and host event supportVic (Chun-Ju) Yang2013-12-141-6/+157
| | | | | | | | | | | | | | | | | This wires 0x62/0x66 to ACPI module and also implements the host event functions. BUG=chrome-os-partner:24107 TEST=ACPI memory test and compliment memory test. TEST=Set SCI mask and host event to trigger SCI. Check SCI pin pulse low. TEST=Query host event from ACPI. BRANCH=None Change-Id: Ib1f557e995a861c92a603491229ad361e17d2129 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179942 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Implement DPTF thermal thresholdsBill Richardson2013-12-131-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Any of the EC's temp sensors can have up to two independent thresholds attached to them. When the temperature crosses the threshold (rising or falling), a EC_HOST_EVENT_THERMAL_THRESHOLD event is sent to the AP. It's up to the AP to read the sensor values and figure out why the event was sent. The thresholds are set and enabled with ACPI writes to three registers in the EC interface space: EC_ACPI_MEM_TEMP_ID, EC_ACPI_MEM_TEMP_THRESHOLD, and EC_ACPI_MEM_TEMP_COMMIT. Refer to the comments in ec_commands.h for details on their use. ACPI does not provide any means to read the threshold settings (the AP will just have to remember), but there is an EC console command "dptftemp", that can be used to examine the current settings. BUG=chrome-os-partner:23970 BRANCH=none TEST=manual On the EC console, check the current threshold settings and temperatures: > dptftemp sensor thresh0 thresh1 0 --- --- PECI 1 --- --- ECInternal 2 --- --- I2C-Charger-Die 3 --- --- I2C-Charger-Object 4 --- --- I2C-CPU-Die 5 --- --- I2C-CPU-Object 6 --- --- I2C-Left C-Die 7 --- --- I2C-Left C-Object 8 --- --- I2C-Right C-Die 9 --- --- I2C-Right C-Object 10 --- --- I2C-Right D-Die 11 --- --- I2C-Right D-Object 12 --- --- I2C-Left D-Die 13 --- --- I2C-Left D-Object > > temps PECI : 318 K = 45 C ECInternal : 306 K = 33 C I2C-Charger-Die : 309 K = 36 C I2C-Charger-Object : Not calibrated I2C-CPU-Die : 309 K = 36 C I2C-CPU-Object : Not calibrated I2C-Left C-Die : 306 K = 33 C I2C-Left C-Object : Not calibrated I2C-Right C-Die : 307 K = 34 C I2C-Right C-Object : Not calibrated I2C-Right D-Die : 307 K = 34 C I2C-Right D-Object : Not calibrated I2C-Left D-Die : 306 K = 33 C I2C-Left D-Object : Not calibrated > In this case, the PECI temp is 318 K, so let's set a threshold at 322 K. On the AP: [ "$#" -eq "2" ] || return; iotools io_write8 0x66 0x81 iotools io_write8 0x62 $1 iotools io_write8 0x62 $2 } Back on the EC console, we see that the threshold has been set: [768.176648 DPTF sensor 0, threshold 49 C, index 1, enabled] > dptftemp sensor thresh0 thresh1 0 --- 322 PECI 1 --- --- ECInternal 2 --- --- I2C-Charger-Die ... Now do something on the AP to increase the temperature (webgl aquarium, etc). When the temp goes above 322 K, the EC console reports it and sends a host event, and the "dptftemp" command indicates the over-temp condition: [815.367442 DPTF over threshold [0][1] [815.367878 event set 0x00000100] [815.368069 sci 0x00000100] [815.368619 event clear 0x00000100] > dptftemp sensor thresh0 thresh1 0 --- 322* PECI 1 --- --- ECInternal 2 --- --- I2C-Charger-Die ... Log out and wait for the temp to drop. You'll see that trigger a host event as well: [854.375713 DPTF under threshold [0][1] [854.376147 event set 0x00000100] [[854.376396 event clear 0x00000100] > dptftemp sensor thresh0 thresh1 0 --- 322 PECI 1 --- --- ECInternal 2 --- --- I2C-Charger-Die ... Change-Id: I6bb34c615f37477ccf37163caaa94737baed8dae Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179962 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: keyboard scan supportVic (Chun-Ju) Yang2013-12-134-0/+81
| | | | | | | | | | | | | | | | | | | | | This adds keyboard scan module driver. Keyboard scan task is not enabled yet as the LPC layer is not finished and thus i8042 protocol cannot be enabled. Since KSO00-KSO03 are used as JTAG, we use KSO04-KSO16 so as to preserve JTAG functionality. Unfortunately we don't have enough KSO pins, so trace debug port must be disabled, as done in this CL. BUG=chrome-os-partner:24107 TEST=Set 'ksstate on'. Short KSI pins and KSO pins, and see corresponding key shown as pressed. TEST=Check keypress is detected when console shows 'KB wait'. BRANCH=None Change-Id: I366a27453ef95030d251e525313eb4627eb4340f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179319 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Change PECI_TJMAX to a board config optionChromeOS Developer2013-12-131-13/+4
| | | | | | | | | | | | | BUG=chrome-os-partner:24455 BRANCH=none TEST=Manual: Verify that CONIFG_PECI_TJMAX set per-board matches the value queried over the PECI bus with the restricted "peciprobe" command. Change-Id: I8e99a23a66f26d6101e01cc751d0a8ca79686321 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179682 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Move ACPI stuff out of chip/lm4 and into commonBill Richardson2013-12-122-105/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The port 62/66 ACPI commands were implemented in chip/lm4/lpc.c. They should be handled in common instead of being tied to a particular EC. BUG=chrome-os-partner:23774 BRANCH=none TEST=manual read EC_ACPI_MEM_VERSION # iotools io_write8 0x66 0x80; iotools io_write8 0x62 0; iotools io_read8 0x62 0x01 write & read EC_ACPI_MEM_TEST # iotools io_write8 0x66 0x81; iotools io_write8 0x62 1; iotools io_write8 0x62 0xa5 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 1; iotools io_read8 0x62 0xa5 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 2; iotools io_read8 0x62 0x5a # iotools io_write8 0x66 0x81; iotools io_write8 0x62 1; iotools io_write8 0x62 0xbb # iotools io_write8 0x66 0x80; iotools io_write8 0x62 1; iotools io_read8 0x62 0xbb # iotools io_write8 0x66 0x80; iotools io_write8 0x62 2; iotools io_read8 0x62 0x44 read & write EC_ACPI_MEM_KEYBOARD_BACKLIGHT # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 100 (keyboard lights up) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x64 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 50 (keyboard dimmer) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x32 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 0 (keyboard goes dark) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x00 read & write EC_ACPI_MEM_FAN_DUTY # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 100 (fan on full) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x64 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 50 (fan on half speed) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x32 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 0 (fan off) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x00 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 0xff (fan back to EC control) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0xff test EC_CMD_ACPI_QUERY_EVENT # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x00 On EC console: > hostevent set 0x0f000000 # ectool eventget Current host events: 0x0f000000 # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x19 # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1a # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1b # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1c # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x00 # ectool eventget Current host events: 0x00000000 Change-Id: I011a5a2051171ec1d37e55ce03e1ce74b93a7e14 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179692
* lm4: Fix potential false over-temperature on entry to S0Alec Berg2013-12-091-1/+9
| | | | | | | | | | | | | | | | | | | This fixes a rare problem in which the EC could shutdown due to a false over-temperature when entering S0 on Haswell architectures. The fix involves requiring two valid reads of the temperature sensor (out of the last 4 readings) in order to report it. BUG=chrome-os-partner:24204 BRANCH=none TEST=See bug report for a patch that recreates the bug at a significantly higher rate then it would occur on its own. Using that patch, I implemented this fix, and made sure that there were no false over-temperatures reported. Change-Id: I0454eca1b96fd2fa1833b080026ed8f1caeeddc4 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177963 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: I2C driverVic (Chun-Ju) Yang2013-12-064-1/+378
| | | | | | | | | | | | | | | | | | This adds the driver for MEC1322 I2C controller. BUG=chrome-os-partner:24107 TEST=Hook up TSU6721 to eval board. Do the following tests: - 'i2cscan' and see TSU6721. - Read device ID register and get correct value. - Add 3 tasks randomly doing I2C read and writes. Check there is no error. BRANCH=None Change-Id: I465f73fe8177a8df6b56c57e594cd733caea37d4 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178591 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* extract common core codeVincent Palatin2013-12-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | Move the non-core dependent code out of core/$(CORE) directory to common/ directory. Put all panic printing code in common/panic_output.c Put timer management code in common/timer.c Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=./util/make_all.sh use "crash divzero" and "panicinfo" on Link. Change-Id: Ia4e1ebc74cd53da55fe24f69e96f39f512b9336d Reviewed-on: https://chromium-review.googlesource.com/178871 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Fan control driverVic (Chun-Ju) Yang2013-12-043-0/+178
| | | | | | | | | | | | | | | | | | | | This adds the driver for PWM duty cycle based and RPM based fan control. BUG=chrome-os-partner:24107 TEST='fanset 5000' and fan spins up. 'fanset 8000' and fan spins faster. 'fanset 0' and fan stops. 'fanduty 30' and fan spins up. 'fanduty 50' and fan spins faster. 'fanduty 30' and fan slows down. 'fanset 6000' and fan goes to ~6000 RPM. Unplug fan power and see 'fan 0 stalled'. Plug power back and doesn't see stall warning anymore. BRANCH=None Change-Id: Ice3e5c03686cde57894e888e34ae2070c33b4e4d Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178402
* mec1322: LPC host command supportVic (Chun-Ju) Yang2013-12-044-1/+178
| | | | | | | | | | | | | | | | | | | With this, basic host command functionality is working. We don't have the correct description of LPC memory BAR register yet, so we have to use EMI (embedded memory interface) module for 0x800-0x9ff region. This requires a slightly different protocol, which is in the next CL. BUG=chrome-os-partner:24107 TEST=Wire EVB to Stumpy. 'ectool hello' and 'ectool version' working. BRANCH=None Change-Id: I873b4a455cf692e479321a5c6e18c8f33df60e66 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178250 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Add support for CONFIG_WATCHDOG_HELPVic (Chun-Ju) Yang2013-12-021-5/+81
| | | | | | | | | | | | | | | | | | If CONFIG_WATCHDOG_HELP is defined, a 16-bit timer is used as an auxiliary timer to interrupt us 50ms before the watchdog expires. When the auxiliary timer expires, the stack trace is printed. Watchdog then expires 50ms after and reboots the system. BUG=chrome-os-partner:24107 TEST=Define CONFIG_WATCHDOG_HELP, and see stack trace on 'waitms 2000'. TEST=Undefine CONFIG_WATCHDOG_HELP, and check watchdog still works without printing stack trace. BRANCH=None Change-Id: I2555d3f86a15c83bb03a00c6807f77d9dddaf333 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178284 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add PWM driverVic (Chun-Ju) Yang2013-12-024-0/+94
| | | | | | | | | | | | | | | | This adds a PWM driver, which now generates 30KHz PWM output. Note that this is different from fan control module driver. BUG=chrome-os-partner:24107 TEST=Set GPIO136 to PWM1. Attach logic analyzer to monitor its output. - Set to active high and 30%, see 30% duty PWM at ~29.1KHz. - Set to active low and 20%, see 80% duty PWM at ~29.1KHz. BRANCH=None Change-Id: I5f1001d5a4701e19fa87c4cabfd4ae5ae7ccb30c Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178391 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Check/save reset causeVic (Chun-Ju) Yang2013-12-021-0/+38
| | | | | | | | | | | | | | | | So far we can only reliably sense a watchdog reset, but this saving/checking reset cause will at least make 'ap-off' flag work. BUG=chrome-os-partner:24107 TEST='waitms 2000' and see reset cause = 'watchdog' TEST='reboot ap-off' and see reset cause includes 'ap-off' TEST='reboot preserve' and see previous reset cause is preserved. BRANCH=None Change-Id: Id47a72d615489c9d9cd0b8761cfa699f08c724df Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178277 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add support for VBAT backed RAMVic (Chun-Ju) Yang2013-12-022-0/+17
| | | | | | | | | | | | | | This will be used for saving data across reboots. BUG=chrome-os-partner:24107 TEST=Enable scratchpad command and check value is preserved across watchdog reboot. BRANCH=None Change-Id: Ifd68541a3f842c466b6ff49bcc654c92df48aac6 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178276 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: remove the ugly DUMMY() macro in system.cVic (Chun-Ju) Yang2013-12-021-5/+15
| | | | | | | | | | | | | | DUMMY() is ugly and DUMMY_int() makes repo complain. Replace them with explicit functions. BUG=chrome-os-partner:24107 TEST=Build mec1322_evb BRANCH=None Change-Id: I155b769c12cafaf432c7f53fd46806feada3cfca Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178275 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Deassert iRESET_OUT on initVic (Chun-Ju) Yang2013-11-271-0/+3
| | | | | | | | | | | | | | | | iRESET_OUT must be deasserted before the host can boot, and it's also the gating source of the internal nSIO_RESET signal. There is a delay between deasserting iRESET_OUT and nSIO_RESET inactivated, so let's deassert iRESET_OUT as early as possible. BUG=chrome-os-partner:24107 TEST=Boot EVB and check iRESET_OUT value BRANCH=None Change-Id: I6647da00567e2651c2b49e1e767adee2d5276493 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178171 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add more register address and IRQ numbersVic (Chun-Ju) Yang2013-11-271-0/+95
| | | | | | | | | | | | | No functional changes. Just adding more chip-specific constants. BUG=chrome-os-partner:24107 TEST=Build mec1322_evb BRANCH=None Change-Id: I649ad2656da941c28a2a738007ced955cd25ea75 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178170 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add GPIO interrupt supportVic (Chun-Ju) Yang2013-11-261-3/+116
| | | | | | | | | | | | | | | | | | With this, we can now define and trigger interrupt on GPIO status. BUG=chrome-os-partner:24107 TEST=Test GPIO036 with following cases: - Pulled up and rising edge trigger. Pull down externally and then release. - Pulled up and falling edge trigger. Pull down externally. - Pulled up and both edge trigger. Pull down and then release. - Pulled up and low level trigger. Pull down externally. BRANCH=None Change-Id: Id9bfd2ba9dd8a75bcf2c5691ffe2aa6518076925 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177560 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add script for packing EC binary into SPI flashVic (Chun-Ju) Yang2013-11-261-0/+159
| | | | | | | | | | | | | | | | This script is needed for packing EC binary into SPI flash for MEC1322. This includes adding tag and header at appropriate location and signing the image. Signing key, for obvious reason, is not included here until we are sure what key we want to check in. BUG=chrome-os-partner:24107 TEST=Build and boot on eval board BRANCH=None Change-Id: I92db7d2ba2c76c14a9c6611a04dbd6a2c3eb8d83 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177324 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add watchdog supportVic (Chun-Ju) Yang2013-11-262-0/+33
| | | | | | | | | | | | | | | This implements the basic watchdog support. For now, the watchdog doesn't warn us before it expires. This functionality will be added later using a basic timer. BUG=chrome-os-partner:24107 TEST='waitms 700' and the EC stays alive. TEST='waitms 1200' and the EC reboots. BRANCH=None Change-Id: I1cc48978ed09577ae88cc2f7a6087867e5854973 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177736
* gpio: Make GPIO_INT_BOTH explicitly RISING|FALLINGRandall Spangler2013-11-234-9/+9
| | | | | | | | | | | | | | | | | | | | | | | For historical reasons on LM4, we defined GPIO_INT_F_BOTH separately from GPIO_INT_F_RISING and GPIO_INT_F_FALLING. This means that the code has weird checks like BOTH || (RISING && FALLING), which have propagated in error-prone ways across the other chips. Instead, explcitly define BOTH to be RISING|FALLING. Ideally, we would have called it GPIO_INT_EDGE to match GPIO_INT_LEVEL, but changing that now would be a big find-replace. Which might still be a good idea, but that is best done in its own CL. BUG=chrome-os-partner:24204 BRANCH=none TEST=build and boot pit, spring, and link; that covers STM32F, STM32L, and LM4. Change-Id: I23ba05a3f41bb14b09af61dc52a178f710f5c1bb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177643 Reviewed-by: Jeremy Thorpe <jeremyt@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org>
* Remove bolt, daisy, kirby, puppy, slippy boardsRandall Spangler2013-11-211-22/+2
| | | | | | | | | | | | | | | | | | These boards are unloved and unsupported. They'll never grow up to be laptops, and hardware is increasingly hard to come by. Comparable functionality is available in the other, more-loved boards. Removing these boards speeds up util/make_all.sh by 40%. (If you're not running that before every upload, you should be...) BUG=chrome-os-partner:24062 BRANCH=none TEST=build all remaining platforms and pass unit tests Change-Id: I4d8a49e4d52d7393471f1b1cbef059c8db4a4f77 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177373
* Add DPTF interface for fan dutyBill Richardson2013-11-211-1/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds include/dptf.h to define the DPTF interface functions. As the first DPTF feature, it also adds a register to the EC's ACPI interface block. Register 0x04 is used to get and set the fan's target duty cycle, as a percentage value. Writing a 0 to this register will set the target duty cycle to 0, writing a 100 (0x64) will set it to 100%. Writing any other value will return the fan control to the EC, rather than driving it manually from the host. Likewise, reading from this register returns the current fan target duty cycle, as a percentage. If the EC is controlling the fan automatically, the returned value will be 0xFF. BUG=chrome-os-partner:23972 BRANCH=none TEST=manual You can monitor the fan state from the EC console with the "faninfo" command. From the host side, test this interface from a root shell. Read fan duty: iotools io_write8 0x66 0x80 iotools io_write8 0x62 4 iotools io_read8 0x62 Set fan duty to 100%: iotools io_write8 0x66 0x81 iotools io_write8 0x62 4 iotools io_write8 0x62 100 Set fan duty to 50%: iotools io_write8 0x66 0x81 iotools io_write8 0x62 4 iotools io_write8 0x62 50 Set fan duty to 0%: iotools io_write8 0x66 0x81 iotools io_write8 0x62 4 iotools io_write8 0x62 0 Set fan control back to automatic: iotools io_write8 0x66 0x81 iotools io_write8 0x62 4 iotools io_write8 0x62 -1 Change-Id: I91ec463095cfd17adf452f0967da3944b254d558 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177423 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: add option for using gpio as kebyoard interruptAaron Durbin2013-11-211-2/+18
| | | | | | | | | | | | | | | | | | | | On certain boards it's no feasible to use the SERIRQ method for generating the kebyboard interrupt. To that end provide CONFIG_KEYBOARD_IRQ_GPIO option which specifies the negative edge-triggered gpio for the keyaboard interrupt. BUG=chrome-os-partner:23965 BRANCH=None TEST=Built and booted rambi using this option. Keyboard works in kernel with interrupts for i8042 device. Change-Id: I64f7e9530841c184d2a33821126ec446c96bb0f0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177188 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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