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* it8380dev: add peci control modulestabilize-7204.BDino Li2015-06-247-3/+489
| | | | | | | | | | | | | | | | | | | Add peci control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command "pecitemp" get CPU temperature normally. 2. console command "peci" manual test peci commands. (GetDIB, GetTemp, RdPkgConfig, and WrPkgConfig) Change-Id: I48b63a391adf04f159adca401acb369a6acc3799 Reviewed-on: https://chromium-review.googlesource.com/265171 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* mec1322: Correctly get reset causeDivya Jyothi2015-06-242-2/+25
| | | | | | | | | | | | | | | | | | Since the reset cause was not recorded correctly recovery mode(Esc+Refresh+Power) was not working. With this change power-on reset state and VCC1_RST# only state are distinguinshed. BUG=chrome-os-partner:41479 BRANCH=none TEST=Esc+Refresh+Power boots to recovery screen Refresh+Power reboots the system Change-Id: I63eff488c970302e7afe8a677a57ad27d4d9918e Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://chromium-review.googlesource.com/280782 Reviewed-by: Shawn N <shawnn@chromium.org>
* it8380dev: add sspi control moduleDino Li2015-06-234-1/+168
| | | | | | | | | | | | | | | | | | | | | | | | Add sspi control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EVB + Winbond W25Q80 SPI ROM To define CONFIG_SPI_FLASH, CONFIG_SPI_FLASH_SIZE, and CONFIG_SPI_FLASH_W25X40 console "spi_flashinfo" can get SPI information > spi_flashinfo Manufacturer ID: ef Device ID: 40 14 Unique ID: c8 60 84 a1 1f 6a 7f 2f Capacity: 1024 MB Change-Id: I6c4d4d977536484d47a2207ed80dd0ea08a7c8fd Reviewed-on: https://chromium-review.googlesource.com/267403 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* cleanup: fix all the header guardsBill Richardson2015-06-1827-80/+80
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash_ec: remove unused USB and unprotect optionsMyles Watson2015-06-181-15/+0
| | | | | | | | | | | | | | There is no need for the usb flag, remove it. There is no need for the unprotect flag, remove it. BRANCH=none BUG=chrome-os-partner:22990 TEST=run flash_ec before and after Change-Id: I201bad7f5be63a90bb8168e21baef2c6fa8d85b4 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273904 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* discovery-stm32f072: Blink the LEDsBill Richardson2015-06-182-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This just makes the LEDs blink continually, because I have a development board sitting on my desk and I like to see it doing something. You can still force the GPIOs on and off using the tool in extra/usb_gpio/. BUG=none BRANCH=none TEST=make buildall Try it: sudo make BOARD=discovery-stm32f072 flash The LEDs blink. Force them on and off with: cd extra/usb_gpio make ./usb_gpio write -1 0 ./usb_gpio write 0 -1 ./usb_gpio write 2 0 ./usb_gpio write 4 2 To resume blinking, use ./usb_gpio write 0 0 Change-Id: Iadbe7436c02de5b6eae81885d95bad154ca3692c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/274131 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* mec1322: Disable Flash Write-protect code.Shamile Khan2015-06-171-9/+63
| | | | | | | | | | | | | BUG=chrome-os-partner:38103 TEST=flashrom -p ec -w ec.bin updates EC successfully. Does not cause a reboot and does not corrupt flash. BRANCH=none Signed-off-by: Shamile Khan <shamile.khan@intel.com> Change-Id: Id45074b991dc6d6d7ed68f72c57a81d9ec1a0713 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/278002 Reviewed-by: Shawn N <shawnn@chromium.org>
* it8380dev: add pmc control moduleDino Li2015-06-177-13/+580
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pmc(LPC ACPI) control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. 62h/66h port. 1-a. out 66h 80h, out 62h 00h, in 62h 02h 1-b. out 66h 81h, out 62h 01h, out 62h 55h 1-c. out 66h 80h, out 62h 01h, in 62h 55h 1-d. out 66h 80h, out 62h 02h, in 62h aah 2. H2RAM LPC I/O cycle 900h ~ 9FFh = DLM 0x8D900 ~ 0x8D9FF and host read only. 3. 80h port, console command port80. 4. host command. 4-a. host request (LPC I/O 800h ~ 807h) 03 FD 00 00, 00 00 00 00 out 204h DAh, in 200h 00h host response (LPC I/O 800h ~ 80Bh) 03 F7 00 00, 04 00 00 00, 02 00 00 00 4-b. host request 03 EE 01 00, 00 00 04 00, 01 02 03 04 out 204h DAh, in 200h 00h host response 03 E5 00 00, 04 00 00 00, 05 05 05 05 Change-Id: I5c3bac66306dfba380548a74a64536ea606ddd3e Reviewed-on: https://chromium-review.googlesource.com/269271 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* common: Add i2c 32bit read/writeGwendal Grignou2015-06-171-0/+30
| | | | | | | | | | | | | Add functions and associated test to read/write a 32 bit register BRANCH=smaug TEST=Test on smaug with bm160 driver BUG=chromium:39900 Change-Id: Ieff24b65f1eb8610874fe13c4a8fadf583a218cb Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277535 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Added support for sysjump.stabilize-7173.BDivya Jyothi2015-06-147-44/+160
| | | | | | | | | | | | | | | | | | | | | | | | changes added to support flashrom are: sysjump support to be able to copy the RO/RW image and jump to it without causing AP to reboot while its alreday ON. LPC init should be reinitialized on sysjump corrected gpio_set_flags_by_mask to make sure we update the register only for GPIO_LOW condition and not all else conditions. BUG=chrome-os-partner:38103 TEST=commands : flashrom -p ec -w ec.bin flashrom -p ec -r ec.bin BRANCH=none Change-Id: I23892f0378d756052030e73034c3acdd41477e34 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272000 Reviewed-by: Shawn N <shawnn@chromium.org>
* tcpc: disable TX timer as early as possible after DMA doneAlec Berg2015-06-131-3/+3
| | | | | | | | | | | | | | | | Move disabling the TX timer up to as soon as possible after DMA transmit is complete to avoid potentially clocking another bit, which could corrupt the end of the transaction. BUG=none BRANCH=smaug TEST=load on glados and use a scope to verify the end of transmit is clean. Change-Id: If52ba2475eeb9752da0acc8efc957c1f472bc711 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277298 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tcpc: change pd_tx_done() to only wait for DMA done eventAlec Berg2015-06-131-5/+1
| | | | | | | | | | | | | | | | | | Change pd_tx_done() to wait specifically for the DMA complete event using task_wait_event_mask(). This fixes a potential bug where if we get another event, for example a TCPM event, while waiting for transmit to complete we restore the pending event after we are done. BUG=none BRANCH=smaug TEST=run on glados and make a bunch of contracts with zinger. Change-Id: Ie28d97eba3edcc7a98fe842e8b7eb6b9d7707047 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/277297 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* spi/mec1322: Ensure that SPI Flash write chunks do not crossShamile Khan2015-06-121-2/+0
| | | | | | | | | | | | | | | | | | | | | | Page Boundary. If SPI Flash write is at an offset within the page and the length is greater than remainder of the page, the Flash page gets corrupted as addressing wraps to the beginning of page and previously written data gets overwritten. This change splits SPI Flash writes in such cases into two operations in different pages. BUG=None BRANCH=None TEST=During Software Sync, Depthcharge sends Flash write chunks that cross page boundary. With this change, the RW parition does not get corrupted. This can be confirmed by executing a successful "sysjump RW" after a Software Sync. Change-Id: I46349eea0d8e927353de7cb55a61e9960291adb6 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/275760 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: fix flash_physical_get_writable_flags()Andrey Petrov2015-06-111-1/+5
| | | | | | | | | | | | Add spi_enable() before SPI transaction. This fixes a problem where protect host cmd ended up messing up SPI controller state. Change-Id: Ief61f279cbd0a90e55ce87d0c350072dc8616c31 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/276338 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* Stream: Remove in_stream/out_stream interfaceAnton Staaf2015-06-112-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The in_stream and out_stream interfaces were a first attempt at providing an abstraction for multiple stream like devices (usart, USB, I2C/LPC host interfaces...). But, by baking the queue into the device it proved to be hard to use and required additional resources (task or deferred hook) to handle passing data from one stream to another. Since then the queue policy and producer/consumer interfaces have replaced the stream interfaces. This CL removes the old stream interfaces and updates the only users (deleting the test echo code from the discovery-stm32f072 board and updating the mcdp28x0 driver to use the queue interfaces). Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ic0d2abf81eafc4fb2e61172540151f2d0ba45caf Reviewed-on: https://chromium-review.googlesource.com/276163 Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* mec1322: Fixed I2C handling on Repeat Start.Kevin K Wong2015-06-101-2/+1
| | | | | | | | | | | | | According to the datasheet, PIN should not be set in the CTRL register. BUG=none TEST=Verify with I2C analyzer that no error is observed. BRANCH=none Change-Id: Ifed58b413151b40ed951cb71b1164432fea28eca Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/276672 Reviewed-by: Shawn N <shawnn@chromium.org>
* Remove obsolete board-specific codeRandall Spangler2015-06-103-71/+4
| | | | | | | | | | | | | | | | | Now that we've removed boards from ToT, also delete board-specific code used only by the removed boards. There are still more things to remove (unused charging chips, LED drivers, COMx support). More CLs coming. BUG=chromium:493866 BRANCH=none TEST=make buildall -j Change-Id: Ie6bdeaf96e61cadd77e3f6336c73b9b54ff4eabb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/276524 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Do not restrict SPI flash reads to Word Boundary.Shamile Khan2015-06-071-5/+1
| | | | | | | | | | | | | | BUG=chrome-os-partner:41145 BRANCH=None TEST=flashrom can update EC's RW partition. Change-Id: I29c450c8cffbc8a47228836ce1959f316026e743 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/275633 Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Commit-Queue: Icarus W Sparry <icarus.w.sparry@intel.com> Tested-by: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* i2c: Retry i2c operation if fails on nack'd(EC_ERROR_BUSY).li feng2015-06-041-6/+17
| | | | | | | | | | | | | | | Retry count is defined by CONFIG_I2C_NACK_RETRY_COUNT. BUG=chrome-os-partner:37494 TEST=Tested on Cyan, observed retry happens on nack'd i2c. BRANCH=None Signed-off-by: li feng <li1.feng@intel.com> Change-Id: I73ed15a52335de6c5a5b647660bfe431a8238716 Reviewed-on: https://chromium-review.googlesource.com/274689 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* Cr50: Add usb_blob handler frameworkBill Richardson2015-06-042-0/+220
| | | | | | | | | | | | | | | | | | | | | This adds a new task and endpoints to handle large opaque (to the USB) chunks of data. The expected use case is that the USB endpoint accepts bytes from the host and passes them blindly to the blob-handling task. At some point, the blob-handling task may wish to send bytes back to the host. What those bytes are and what they mean is determined at higher levels of abstraction. BUG=chrome-os-partner:40969 BRANCH=none TEST=make buildall This CL doesn't enable the blob-handler; it just makes it available. The next CL will enable and test it. Change-Id: I6eba8e8010466e71efe9c5e06848b9f403df835f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/275131 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: fix read-only I2C transfers on STM32F0/F3Vincent Palatin2015-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | Ensure that we put a proper start bit if the transfer only contains a read but has the start flag set. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=chrome-os-partner:40919 TEST=On Smaug (P6), at the Linux prompt, do "cat /sys/class/power_supply/bq27742-0/current_now" and see a proper value rather than an error. Change-Id: I10cc9907476b3cfb006f2c1540688139366c9195 Reviewed-on: https://chromium-review.googlesource.com/275079 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Puthikorn Voravootivat <puthik@chromium.org>
* Increase charger/console/hook stack sizes.Chiranjeevi Rapolu2015-06-041-0/+4
| | | | | | | | | | | | | | | | | | | | Charger task is overflowing and causing crash. Increased charger task stack size by 128 bytes. Also increased console/hook by 128 bytes as these are also close to its limit. BRANCH=None BUG=chrome-os-partner:40766 TEST=1.Program EC image. 2. Run various tests to verify charger stack doesn't overflow. Change-Id: I6e350584508fa3a47769982b1e0cf3e3aea9ded6 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/274204 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* mec1322: Implement i2c_set_timeoutShawn Nematbakhsh2015-06-032-8/+23
| | | | | | | | | | | | | Allow timeout to be set at runtime by controller. BUG=chrome-os-partner:40780 TEST=Manual on Glados. Verify PD I2C communication is functional. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I582e47c7bebfed7a639789c90064d86ffe1a5401 Reviewed-on: https://chromium-review.googlesource.com/274967 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* oak: Add PD communication to oakAlec Berg2015-05-301-0/+2
| | | | | | | | | | | | | | | | | | Add TCPM on EC side and TCPC on PD side to allow PD communication. Enable PD communication on port 0. BUG=none BRANCH=none TEST=load on oak. plug in hoho on port 0, and make sure we successfully negotiate a PD contract. (note: you have to manually enable 5V VBUS right now) Change-Id: I0ce7c016545bc56c5e10f66b49b73722187f12dc Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/271829 Reviewed-by: Rong Chang <rongchang@chromium.org> Reviewed-by: Sheng-liang Song <ssl@chromium.org> Commit-Queue: Sheng-liang Song <ssl@chromium.org>
* Cr50: Use USB structs instead of byte arrays for readabilityBill Richardson2015-05-292-25/+32
| | | | | | | | | | | | | | | | | The USB spec mandates that all structs are little-endian over the wire. Since we're a little-endian architecture (and the code we're changing is intentionally chip-specific), we can just cast the hardware buffer into the correct struct. This makes the code easier to read and understand. BUG=none BRANCH=none TEST=make buildall Change-Id: Ib2d3b04f4db1a531cb3f5ada1a2e6ee82e8a23aa Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/274130 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: USB hardware uses 8-bit buffers, not 16-bitBill Richardson2015-05-295-107/+44
| | | | | | | | | | | | | | | Our USB buffers are just arrays of uint8_t in program RAM, so let's treat them that way. The DMA descriptors are in normal RAM, too. BUG=chrome-os-partner:40693 BRANCH=none TEST=make buildall Change-Id: Ibafe1a557a328bbf8cf37ce113675fcd35bad376 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273918 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: i2c: Fix open transaction i2x_xferShawn Nematbakhsh2015-05-291-11/+23
| | | | | | | | | | | | | | | | | - Don't re-send our slave address if we're not generating a start condition. - Handle repeated start vs new transaction properly in the Rx case. BUG=chrome-os-partner:40677 BRANCH=none TEST=Manual on glados. Verify 'battery' dumps correct info, and i2cscan succeeds. Also verify that tcpc communication with PD transmits the expected data. Change-Id: I30315d2d82857d6031fda6d4e6a787a52ec01382 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273956 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Remove device-specific stuff from include/usb.hBill Richardson2015-05-282-0/+170
| | | | | | | | | | | | | | | | This moves the STM32-specific code out of the common header file and into the chip directory where it belongs. Note that this doesn't actually change the code for non-STM32 SoCs; that will happen in a separate CL for clarity. BUG=chrome-os-partner:40693 BRANCH=none TEST=make buildall Change-Id: Ifdf0086e86a1088fb011b9ac4d6c70ab8da47aec Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273577 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Added KBD SERIRQ supportKevin K Wong2015-05-281-7/+8
| | | | | | | | | | | | | | BUG=chrome-os-partner:24107 TEST=Keyboard keys are printed correctly on Kunimitsu. BRANCH=none Change-Id: Ia4ed6c1166fa20dc8623ea8d7147b6f587cbf993 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272504 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* oak_pd: add initial support for oak PDAlec Berg2015-05-273-0/+68
| | | | | | | | | | | | | | | Add initial support for Oak PD MCU on rev1 boards. This does not include USB PD communication. BUG=none BRANCH=none TEST=build and load on oak and get console. test we resond to host commands from EC using "pdcmd 0 0" on EC console. Change-Id: I92045cf0fd682279ada6c286f5399f0e258a6305 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/271828
* i2c: Make i2c_xfer a wrapper function to chip_i2c_xferShawn Nematbakhsh2015-05-277-23/+23
| | | | | | | | | | | | | | | | i2c_xfer was previously implemented at the chip-level, but now we want to add some global retry logic. Rename the chip-level i2c_xfer functions to chip_i2c_xfer and add a new global wrapper function i2c_xfer. BUG=chrome-os-partner:39613 TEST=Run "battery" from EC console on Cyan, verify that values + strings are correctly printed. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If37c85cc3cf94fd53feb6931553e10c30ad6cad6 Reviewed-on: https://chromium-review.googlesource.com/272939 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* oak: add initial support for oak board rev1Rong Chang2015-05-272-0/+23
| | | | | | | | | | | | | | | Add initial support for Oak rev1 board. This is just the EC and includes battery charging but does not include USB PD. BUG=none BRANCH=none TEST=load on oak board and get console Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Alec Berg <alecaberg@chromium.org> Change-Id: I626f3921025fbc39ba22b04eeb6dd1084cd70777 Reviewed-on: https://chromium-review.googlesource.com/261678
* mec1322: Simplify GPIO listsSteven Jian2015-05-279-3/+27
| | | | | | | | | | | | | | | Our existing GPIO macros use port# / gpio#, but the concept of different GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros for chips which do not have distinct GPIO ports. BUG=None BRANCH=None TEST=make buildall -j Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b Signed-off-by: Steven Jian <steven.jian@intel.com> Reviewed-on: https://chromium-review.googlesource.com/262841 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* pd: stm32f0: modify i2c driver to support TCPCIAlec Berg2015-05-272-1/+51
| | | | | | | | | | | | | | Modify the stm32f0 i2c driver to support the new TCPC interface. BUG=none BRANCH=none TEST=test on oak Change-Id: Ibcb205e67d59d99a97dce090bd84bbb714ad5032 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270173 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: move non-phy layer config out of usb_pd_config.hAlec Berg2015-05-272-7/+7
| | | | | | | | | | | | | | | | | | | | | Move parts of usb_pd_config.h that are not part of the phy layer out of usb_pd_config.h and into board.h. This cleans up the division between the TCPC and TCPM as only the TCPC needs to use usb_pd_config.h. Also cleans up the use of the CC detection voltage thresholds by creating standard macros to use based on Rp strength for the board. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I946cceb38bea8233095b8a4b287102bb8a3a296d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270337 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* i2c: Move i2c_read_string to common codeShawn Nematbakhsh2015-05-265-140/+1
| | | | | | | | | | | | | | | | | Since stm32 and mec1322 now support open-ended i2c_xfer, we can move the lm4 i2c_read_string implementation to common code and delete all chip-specific versions. BUG=chrome-os-partner:39613 TEST=Run "battery" from EC console on Cyan and Oak, verify that battery info + strings are correctly printed. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I06369df64bb2eb747d163664b4c96eeacb4b1faa Reviewed-on: https://chromium-review.googlesource.com/272938 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: i2c: Support open-ended i2c transfersShawn Nematbakhsh2015-05-261-55/+59
| | | | | | | | | | | | | | | Modify i2c_xfer to support transfers where start and stop conditions are not issued together. BUG=chrome-os-partner:39613 TEST=Manual with subsequent commit. Verify that 'battery' shows proper values + strings. BRANCH=None Change-Id: If98c9493902326203880645828061c45c9cfd8be Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/272995 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Producer/Consumer: Refactor to use Queue policiesAnton Staaf2015-05-264-39/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously the Producer and Consumer interfaces tracked the Consumer and Producer respectively at the other end of the queue that they interacted with. This was done to avoid modifying the queue implementation, but resulted in a rougher interface that required additional initialization steps and prevented alternative configurations; many producers and one consumer for example. This commit uses the new queue policies to track this information. The new direct policy behaves as the old producer and consumers did. Now the producers and consumers are just named references to the queue that they work on and a convenient location for a notification callback when the queue is updated in a way that is relevent to the producer or consumer. All users of Producer and Consumer have been updated including the stream adaptors which are in use by the echo test code and the mcdp28x0 driver. Use of the stream adaptors has also been simplified. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Manual testing of Ryu (P5) and discovery board echo task Change-Id: I704be6378a31b4e20f5063295eff9943e4900409 Reviewed-on: https://chromium-review.googlesource.com/271792 Reviewed-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* Queue: Add policies to queuesAnton Staaf2015-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | Policies give a convenient place to hook into the queue operations and notify something that there is new space free in the queue or new units added. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I94b2aa94b8e8d07911191bc19a39fa827623b117 Reviewed-on: https://chromium-review.googlesource.com/271791 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org>
* mec1322: Fixed incorrect value passed to I2C unwedge function.Kevin K Wong2015-05-231-2/+2
| | | | | | | | | | | BUG=chrome-os-partner:40175 TEST=Check i2c_unwedge is called with a valid port number by using debug print. BRANCH=none Change-Id: Ibc8e441116441b526c872a9cb33cb252650bca5a Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272769 Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32f0: i2c: fix master i2c sending partial transfersAlec Berg2015-05-222-7/+28
| | | | | | | | | | | | | | | | | | | | | | | | | Fix master i2c when sending partial transfers using I2C_XFER_START and I2C_XFER_STOP. BUG=none BRANCH=none TEST=Tested i2c transfers on oak. tested transfers with I2C_XFER_SINGLE (I2C_XFER_START | I2C_XFER_STOP) and tested partial transfers with just one flag. For partial transfers I tested two different types: - i2c_xfer START only transmitting, then another i2c_xfer with more trasnmitting followed by a STOP. verified with logic analyzer that there is not restart in the middle. - i2c_xfer START with transmitting and receiving, then another i2c_xfer with more receiving followed by a STOP. verified with logic analyzer that there is one restart in between transmitting and receving and no restart in between the two calls to i2c_xfer. Change-Id: Ie4146d1cf7d39f7dc56fd02e65add6bf02772e67 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/272690 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* pd: add config options for including TCPM and TCPC separatelyAlec Berg2015-05-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Add config options for various parts of USB PD stack: CONFIG_USB_POWER_DELIVERY: The use of this option has changed slightly. It now represents whether or not to include the USB PD protocol and policy layers of the software stack. CONFIG_USB_PD_TCPC: Compile in type-C port controller module which performs the phy layer of the PD stack. CONFIG_USB_PD_TCPM_STUB and CONFIG_USB_PD_TCPM_TCPCI: If CONFIG_USB_POWER_DELIVERY is defined, then one TCPM needs to be defined to declare which port management module to use to drive the TCPC. BUG=none BRANCH=none TEST=make -j buildall Change-Id: I41aa65a478e36925745cd37a6707f242c0dfbf91 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270171 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f0: i2c: Add i2c_xfer repeated start supportRong Chang2015-05-202-20/+51
| | | | | | | | | | | | | | | | | | | | | | stm32f051 I2C slave does not clear transmit interrupt status (TXIS) on receiving NACK. That fails to support I2C master repeated-start read. This change moves slave transmit from host command thread's TXIS loop to interrupt event loop. And enables NACK interrupt to handle master restart. On the I2C master side, this CL adds i2c_xfer flags. With this CL, stm32f0 EC can talk to stm32f051 PD through host commands. BRANCH=None BUG=None TEST=make BOARD=<board with stm32f0 EC and PD> Verify EC console command "pdcmd 1 0 0x10 0x20 0x30 0x40" Change-Id: I771b4fb3de3732f18da90ea5e27a79afb09689b0 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/267041 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
* Add option to enable GCC LTOVincent Palatin2015-05-195-5/+5
| | | | | | | | | | | | | | | | | | | | | | Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the flash footprint of the firmware. Add additional protection to some functions/data to avoid removal by the linker when their usage is not obvious. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall (with and without LTO enable on all boards) Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059 Reviewed-on: https://chromium-review.googlesource.com/271291 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Correct SPI image offsetsShawn Nematbakhsh2015-05-161-55/+68
| | | | | | | | | | | | | | Correct image offsets to reflect our actual layout. BUG=chrome-os-partner:39741 TEST=Manual on Cyan. Verify EC image boots and FMAP RO_FRID and RW_FWID point to our actual IDs. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If0c4e44f45cac1cdc0a99cf0ae4c17e0ead95486 Reviewed-on: https://chromium-review.googlesource.com/270353 Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
* cleanup: Use appropriate image geometry CONFIGsShawn Nematbakhsh2015-05-1523-304/+32
| | | | | | | | | | | | | | | | - Use CONFIG_*_MEM when dealing with images in program memory. - Use CONFIG_*_STORAGE when dealing with images on storage. - Use CONFIG_WP when dealing with the entire WP RO region. BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches actual layout of image. Verify flashrom succeeds flashing + verifying EC image using host command interface. BRANCH=None Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270269
* Fix type mismatch on extern declarationsVincent Palatin2015-05-151-1/+1
| | | | | | | | | | | | | | | | | | | Update a few extern declarations to match the original variable type. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall Compile with LTO enabled and no longer see errors for those declarations. Change-Id: I5b0f0f7f498ec414a861cb1ce50a486036c853bd Reviewed-on: https://chromium-review.googlesource.com/271279 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Rename image geometry CONFIGsShawn Nematbakhsh2015-05-1221-127/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | Rename image geometry configs with a uniform naming scheme to make their purposes more clear. CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Set date / version strings to constants then `make buildall -j`. Verify that each ec.bin image is identical pre- and post-change. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd Reviewed-on: https://chromium-review.googlesource.com/270189 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* cr50: add SPI Slave driverVadim Bendebury2015-05-072-0/+487
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CR50 device will have to have two different drivers, for SPI slave and master modes. This patch adds the slave driver which is called SPS. CR50 SPS controller uses 2KB buffer split evenly between receive and transmit directions as two FIFOs. RX write and TX read pointers are maintained by hardware, RX read and TX write pointers are maintained by software. The FIFO area allows only 32 bit writes from the CPU core, which complicates the function placing TX data into the FIFO. There is no limit to read access size. Another complication is that the hardware pointers in the FIFO in fact have 11 bits (instead of 10 required to address 1K), so the software needs to use 10 bits when accessing the FIFO, but 11 bits when writing the pointers into the registers. Driver API provides three functions: - transmit a packet of a certain size, runs on the task context and can exit before the entire packet is transmitted., - register a receive callback. The callback is running in interrupt context. Registering the callback (re)initializes the interface. - unregister receive callback. A CLI command is added to help testing this driver. When invoked, it installs the callback function to handle receive data. The data is expected to be of the following format: <size/256> <size%256> [<size> bytes of payload] where size should not exceed 1098 bytes. Received frames are saved in a buffer and once received are transmitted back to the host. BRANCH=none BUG=none TEST=used the enhanced 'spiraw' utility which sends frames of random size in 10..1010 bytes, and then clocks the line to receive the same amount of bytes back, syncs up in the returning stream of bytes and compares received and transmitted data. # run 'sps 100' on the target $ src/examples/spiraw.py -l 100 -f 2000000 FT232H Future Technology Devices International, Ltd initialized at 2000000 hertz $ which is an indication of the successful loop back of 100 frames. The cli command on the target exits and reports the stats: > sps 100 Processed 100 frames rx count 108532, tx count 51366, tx_empty count 100, max rx batch 11 Change-Id: I62956753eb09086b5fca7504f2241605c0afe613 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/269794 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mec1322:Flasherase, flashread, flashwrite offsets adjusted.Divya Jyothi2015-05-052-2/+7
| | | | | | | | | | | | | | | | | | | | | Flash read,erase and write should access SPI flash and not read SRAM MAPPED location. flashrom -p and Software sync use the same flash functions to perform flashread,flashearse and flashwrite.So these functions should be reading RW image starting address offset.Address offset sent by host should not depend on the actual SPI flash as the EC code handles the right offset to program the ec.bin(via flashrom -p) and RW image only via software sync. BUG=chrome-os-partner:38103 BRANCH=None TEST=flashrom -p options tested to read and update ec.bin Change-Id: I3fb16accf3e05eaa3469a8a589962164574d5fb2 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/269231 Reviewed-by: Shawn N <shawnn@chromium.org>
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