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* mec1322: Properly initialize the ALTERNATE GPIO level flagsKevin K Wong2015-09-101-4/+5
| | | | | | | | | | | | | | | | | | | Initialise the ALTERNATE GPIO level flags along with rest of the flags to prevent GPIO toggling during I2C initialization. BUG=chrome-os-partner:44821 BRANCH=none TEST=Manually tested on Kunimitsu FAB3. I2C SDA & SCL lines do not toggle during I2C initialization. Soon after the I2C init is done, read/write to PMIC is success. Change-Id: I70f728017b00f407a0422fd4aa4dbfd8590d74de Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/298242 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: clocks: Don't squash reserved bits in sleep / wakeShawn Nematbakhsh2015-09-103-12/+24
| | | | | | | | | | | | | | | | | | Keep the state of reserved bits in SLP_EN registers when sleeping and waking from sleep. BUG=chrome-os-partner:45003 TEST=Manual on glados. Go to S3 and measure EC power. Go to deep sleep and wake. Re-measure power and verify that it is not ~60% higher than originally measured. BRANCH=Strago Change-Id: I6b6b0efcd146fe1a68b41b9b33b25740090dc08f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/298655 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: bug fix for hibernation timerKyoung Kim2015-09-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | When system timer stops while in heavysleep idle task, hibernation timer maintains system time and system timer's recovery is done with reading from hibernation timer. If hibernation timer setting/reading is incorrect, system timer recovery is incorrect and evenytually this will result in quicker/more frequent task scheduling and eventually faster sleep LED blinking at S3 and higher S3 power consumption. BRANCH=firmware-strago-7287.B BUG=chrome-os-partner:37576 TEST=1. measure S3 LED blinking time(probing GPIO pin with scope 2. For debug purpose, let system timer keeps running and compare internval from system timer reading (t1 - t0) and one from hibernation timer. Change-Id: Iace3d29c9e20c0ea863c25eacb69d50858e204b7 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/297753 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 86e7e64e3b5d27a80e1fac296776c0e2fb57912d) Reviewed-on: https://chromium-review.googlesource.com/297796 Commit-Ready: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* update case closed debugging partial mode policyVincent Palatin2015-09-084-7/+22
| | | | | | | | | | | | | | | | | | | | | | | When a debug accessory is connected to the type-C port while the write protection is enabled, put the case closed debugging in "partial" mode rather than "full". Update the "partial" mode to provide read-only access to the AP and EC consoles. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=smaug BUG=chrome-os-partner:44700 TEST=check the EC console input/output over USB is still working with SuzyQ on a write-protected system, verify that the console input is disabled. Change-Id: I5baa03d6e738d06437c45469f46b286e76a755a4 Reviewed-on: https://chromium-review.googlesource.com/297141 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Cleanup: Remove COMPILE_FOR_RAM option from linker scriptsBill Richardson2015-09-083-9/+0
| | | | | | | | | | | | | | | This option was added way back in January 2012 for early EC bringup, and never used since. We can probably remove it. BUG=none BRANCH=none TEST=make buildall Change-Id: Idc8c3099388f2e28d620848a0e78b555b02fba9c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297334 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* I2C: Remove unused arbitration supportAnton Staaf2015-09-082-2/+0
| | | | | | | | | | | | | | | | | The i2c_claim and i2c_release routines are no longer in use, removing this code removes one odd usecase of the panic printing routines. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I76c1d90738e1e39b4b3226c31085513a20bbd769 Reviewed-on: https://chromium-review.googlesource.com/296732 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: Fixed the bugs for flash and i2c drivers.Mulin Chao2015-09-062-58/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the length of flash-write function used by host command is not aligned to 256 bytes, we need to split it into several sequences to make sure it won't exceed page buffer size of flash. Add i2c stop condition checking to avoid unnecessary i2c unwedge operations. We found some battery will held scl for a while and master cann't issue stop condition immediately. Modified drivers: 1. flash.c: Add support for sequence programing. 2. i2c.c: Add i2c stop condition checking mechanism. 3. i2c.c: Fixed bug of i2c_is_raw_mode. (wrong bit offset) BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I4f35a617466ba37bcc4e3aa5324c8950f824a4c2 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/295662 Commit-Ready: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Update some TODO comments.Bill Richardson2015-09-031-4/+0
| | | | | | | | | | | | | BUG=chrome-os-partner:44803 BRANCH=none TEST=make buildall Comment change only. Change-Id: I68c2fba64b7f613e3936f4e7ddf6b48430c7b858 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297021 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Remove FPU support by defaultShawn Nematbakhsh2015-09-021-1/+0
| | | | | | | | | | | | | | | | | | Floating point is used in very few places in the code, none of which are needed by mec1322 boards (yet). If needed, individual boards can define CONFIG_FPU. BUG=None TEST=Verify glados continues to boot AP successfully and image is shrunk by 64 bytes. BRANCH=Strago Change-Id: I6ea46c15bedbc498e7baa96098b002d711ac20fb Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297029 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Clarify use of flash layout CONFIGsShawn Nematbakhsh2015-09-024-95/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | Based on feedback from programmers, it's not clear when config_std_internal_flash should be used, and when non-standard chip-specific layouts need to be defined. Add clarity here with the following changes: - Explain in-depth the one config that config_std_internal_flash should be used for. - Move non-standard chip-level flash layout CONFIGs to their own new chip-level file, config_flash_layout. All chips should either include config_std_internal_flash.h OR define their own layout in their own config_flash_layout. Functionally, this change is a NOP. BUG=chrome-os-partner:23796 TEST=`make buildall -j` BRANCH=None Change-Id: I6037b68db9048d90fa2a2da4c9c9e09d1143fa68 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/296527 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* system: provide optional chip_save_reset_flags()Aaron Durbin2015-08-261-1/+6
| | | | | | | | | | | | | | | | | | | Certain boards may need to handle fixing up the RESET_FLAG_s because of the boards' designs. Provide an optional per-chip implementation to save the reset flags. Note that this function is not protected by a CONFIG_ option as it can just be implemented by the chip if a board requires it. Lastly, implement chip_save_reset_flags() for mec1322 for future use. BUG=chrome-os-partner:44527 BRANCH=None TEST=Built and booted on glados. Change-Id: I604fe4e6a069f31727bab52288595a349e3dbe72 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295115 Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: fix console in lfwAaron Durbin2015-08-271-1/+5
| | | | | | | | | | | | | | | | | | | | | | | The console support in lfw was not very in for printing messages. The version was smashed against the name of the program and the image type was at the same column as end of version: littlefwglados_1.1.9999-f3a5046 lfw-RO load Fix this by adding a space after the program name and outputting a carriage return if a new line is encountered. With these changes the new console looks like: littlefw glados_1.1.9999-f3a5046 lfw-RO load BUG=chrome-os-partner:44527 BRANCH=None TEST=Built for glados. 'reboot' shows legible console output. Change-Id: I7b80b2c7db453c09a401a740155de98e78f3cf84 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295112 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: i2c: Unwedge controller on transaction timeoutShawn Nematbakhsh2015-08-261-1/+9
| | | | | | | | | | | | | | | | | | | | | If clk or dat aren't pulled up for an extended period, the i2c controller may get into a wedged state that requires a controller reset to recover from. There are no outward signs of the controller being in such a state, other than transaction timeouts. Therefore, on a transaction timeout, reset the controller. BUG=chrome-os-partner:43270 TEST=Manual on glados: - Run `gpioset PP3300_USB_PD_EN 0` on PD console and wait several seconds - Run `gpioset PP3300_USB_PD_EN 1` on PD console - Run `i2cscan` and verify all ports / devices ack - Repeat above several times BRANCH=None Change-Id: I2ae42762ee6c961224ff50309a448475b67854b5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295404 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* cr50: add plumbing for signing CR50 RO imagesVadim Bendebury2015-08-251-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The signer utility needs to be built and the flat image needs to be signed. The signer utility is written in C++, supporting this required adding a new make command to Makefile.rules and a build file for the utility. The signing now needs to be a part of generating the .flat file. To achieve this an alternative set of rules is defined in Makfile.rules for targets where RO image needs to be signed. Rules for converting elf to hex have been consolidated as there is no need to omit the --set-section-flags when it does not apply. BRANCH=none BUG=chrome-os-partner:43025 TEST=as follows: - ran 'rm build/cr50; make BOARD=cr50' - observed that both build/cr50/ec.bin and build/cr50/RO/ec.RO.flat have the required signature header in the first 1024 bytes. - verified that the cr50 board can be booted over SPI using the image in build/cr50/RO/ec.RO.flat Change-Id: Iacc22561de67fadfaf8e049bf9578cbd08cfad86 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295291 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: Move to RevB:20150820 FPGAVadim Bendebury2015-08-251-3147/+3149
| | | | | | | | | | | | | | | | | This changes the register description to match the newer FPGA version. The new version supports firmware integrity verification as well as bootstrapping over SPI slave interface. BRANCH=none BUG=chrome-os-partner:43791 TEST=with the rest of the patches (providing ability to sign firmware and load it over SPI) the code gets signed properly and loaded and started on the target Change-Id: Ibebe5f6c510fbfb2c7c6ff40ab58ea643f051b1b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295211 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: allocate RO header for signatureVadim Bendebury2015-08-251-0/+1
| | | | | | | | | | | | | | | Leave 1024 bytes at the cr50 RO section for the signature required by maskrom bootloader. BRANCH=none BUG=chrome-os-partner:43025 TEST=with this and other changes the latest cr50 image gets signed and booted properly. Change-Id: I64efe242b958bbb4e320cb3bb16c653d210dd662 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295201 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* USART: Add DMA based receiverAnton Staaf2015-08-249-1/+230
| | | | | | | | | | | | | | | | | | | | | | | | This DMA receiver uses a separate small circular buffer to DMA into. This allows the DMA transaction to be made circular, and thus it does not require the interrupt latency to be low enough to setup the next transfer before the next character comes in. Additional diagnostics output have been added to the usart_info console command to facilitate tuning of the FIFO size. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Verify DMA works by cross connecting two discovery boards Change-Id: Idcdf95a47fadf21ec2154f0c9128cd3586e568ec Reviewed-on: https://chromium-review.googlesource.com/292870 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* USART: Add usart_info commandAnton Staaf2015-08-249-6/+87
| | | | | | | | | | | | | | | | | | | This optional console command is enabled with CONFIG_USART_INFO_COMMAND. It will display and clear dropped character and overrun counts for all configured USARTs. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Icf6061aaab2cda71e9d317455c897828b9daf844 Reviewed-on: https://chromium-review.googlesource.com/292770 Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* stm32: spi: clear the spi sleep mask when AP in S3.Ben Lok2015-08-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | The SLEEP_MASK_SPI will not be cleared, if SPI received a bad data. It is possible to block EC to enter deep sleep if AP send a bad packet to EC before AP goto S3/S5. In order to ensure that deep sleep can be enabled, clear SLEEP_MASK_SPI in chipset suspend hook to avoid this situation. BUG=chrome-os-partner:44170 BRANCH=None TEST=manually 1. use AP console command to let AP enter S5: > shutdown -h now 2. check the sleepmask in EC console. > sleepmask sleep mask: 00000000 Change-Id: Ib5f5c421c123d9a3c2cc6fead07c8fa515e452f1 Signed-off-by: Ben Lok <ben.lok@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/294432 Reviewed-by: Rong Chang <rongchang@chromium.org>
* nds32: use INT_MASK instead of GIEDino Li2015-08-202-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | When there is an interrupt event, N8 CPU will save PSW register to IPSW register and clear GIE then jump to interrupt service routine. N8 will restore PSW from IPSW after "iret" instruction (the above are purely hardware mechanism). Nested interrupt will occur if we set GIE again in interrupt context. symptom: power button pressed while LID open -> exception or unknown reset. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Manually pressed power button x200. 2. Console "eflash" erase and write eflash OK. Change-Id: Ic04a23d473ebc6417dffea814a27583cb8d63a1f Reviewed-on: https://chromium-review.googlesource.com/289437 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* nuc:Mulin Chao2015-08-196-138/+224
| | | | | | | | | | | | | | | | | | | | | Modified i2c driver into controllers and ports to support I2C0 port 0/1 at the same time. Modified drivers: 1. i2c.c: Support i2c controller mechanism and fixed bug for i2c_raw functions used by i2c_wedge and i2c_unwedge. 2. gpio.c: Fixed bug for gpio_alt_sel since wrong type of func. 3. lpc.c: Fixed bug for port80. Since disabling SUPPORT_P80_SEG, we should replace GLUE_SDP0/1 with DP80BUF. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I9919269e4f5e795d9ceb8a4cd2c39abbd7bb6b1a Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/294015 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Fix spshc console commandBill Richardson2015-08-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPS RX FIFO handler prototype changed from passing cs_enabled to cs_disabled, but the callback function for the spshc command didn't. Now it does. The spshc command switches the protocol on the SPI Slave bus to expect EC Host Commands. BUG=none BRANCH=none TEST=manual At the EC console: spstpm off spshc On the build machine, with an FTDI cable connected to the SPS input: cd extra/ftdi_hostcmd make ./test_cmds Change-Id: I69294a977b83854c5f6348904330bf74416cc6ec Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293619 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: tpm2: pull in the tpm2 library sourcesVadim Bendebury2015-08-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch syncs up TPM2 sources into the build area when building cr50 image. This relies on a specific directory layout so that the ec makefile has access to the tpm2 source tree. The sources are copied using rsync, the tpm2 library is a dependency for the RO/RW elf images, and is declared to be a phony make target, which guarantees that the tpm2 make is always run when cr50 image is built. Include files in board/cr50/tpm2 are necessary to be able to build tpm2 code using the bare metal toolchain used for building ec code. memory.h is in fact empty, it is easier to add it here than to wrap it in conditional compilation at the source. Make variables CROSS_COMPILE and CFLAGS are exported for the benefit of the tpm2 makefile. ROOTDIR indicates where tpm2 library should look for .h files not available from the toolchain. CQ-DEPEND=CL:292946 BRANCH=none BUG=chrome-os-partner:43025 TEST=make buildall -j succeeds; when linked with the latest tpm2 source, the combined image starts the tmp task and reacts to the host sending the startup command (failing due to unplugged stubs). Change-Id: Ia3fd260588558c2bacd724df9583052fa4660ca3 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/292975 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: introduce tpm task skeletonVadim Bendebury2015-08-141-1/+1
| | | | | | | | | | | | | | | | | | | TPM command processing should not be happening on the interrupt context. This patch adds a skeleton of the task which handles TPM functions. It initializes the TPM and then enters endless loop waiting for an event trigger from interrupt, which happens when a valid FIFO message is received. BRANCH=none BUG=chrome-os-partner:43025 TEST=none yet Change-Id: I63dce2762cc07370a05bf00bdf144c5d9eb6019b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289332 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: sps: allow receive registration function set FIFO thresholdVadim Bendebury2015-08-134-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The default receive FIFO threshold of 8 (meaning that 9 bytes need to be received before receive IRQ fires) is good for high volume transfers, when the amount of transferred data greatly exceeds the threshold. But in case of TPM transactions, which start with a 4 byte header and then stall while the device processes it, the default threshold guarantees delays on every transaction, as the receiver does not start processing the header until 5 idle bytes are transferred to bring the total number to nine. The suggested solution is to allow to specify the receive FIFO interrupt request threshold at run time, by adding this value to the receive function registration API. BRANCH=none BUG=chrome-os-partner:43025 TEST=verified that spstest still works fine. Change-Id: I92517205a7d0d47893b702efa188eb524fb18a49 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289331 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* it8380dev: add console command "rwreg"Dino Li2015-08-131-0/+82
| | | | | | | | | | | | | | | | The console command "rwreg" for accessing EC/PNPCFG registers. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console "rwreg" Change-Id: I6345b3f40c8992f06959f50625e11e5b89c6eae8 Reviewed-on: https://chromium-review.googlesource.com/293120 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* npcx_evb_arm: Fix buildShawn Nematbakhsh2015-08-121-0/+2
| | | | | | | | | | | | | | npcx GPIO code calls out to an LPC function, which isn't defined on platforms without LPC support. BUG=chromium:520207 TEST=`make buildall -j` BRANCH=None Change-Id: I80c0d08fea4a2621df9646926959fc48af52a15a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/293013 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* nuc:Using LRESET interrupt to re-initialize LPC settings after warm bootMulin Chao2015-08-123-13/+58
| | | | | | | | | | | | | | | | | | | | | | Fixed bug during polling port 0x204 by BIOS. We should set processing flag before reading command byte in ISR to prevent EC_LPC_STATUS_FROM_HOST and EC_LPC_STATUS_PROCESSING bits are both low. Modified drivers: 1. gpio.c: Add LRESET ISR. 2. lpc.c: Fixed bug during polling port 0x204 by BIOS. 3. flash_ec: Reset ec before flashing ec BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I8e557f2e2be41a7a9d40c03c775313b12668f283 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/291210 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org>
* Allow for private board configurationsBill Richardson2015-08-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The public sources look for board configurations in directories named board/$BOARD/ Sometimes it's necessary to keep sensitive projects out of the public view for a bit. This CL allows board configurations to also appear in directories named private*/board/$BOARD/ BUG=none BRANCH=none TEST=manual First, ebuilds and "make buildall" seem to work just as before. Second, I copied 24 of the existing boards (those without board-specific #ifdefs in the code) into a private*/board/ directory, renamed them to something unique, and ran "make buildall" again. Both public and private boards compiled and passed their tests. Change-Id: I977c23cb8e73e40677c8f329abca8bbc51fd53df Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/292428 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* glados: Turn off LEDs in hibernateShawn Nematbakhsh2015-08-111-8/+0
| | | | | | | | | | | | | | | Use new board-level hibernate GPIO state function to turn off LEDs in hibernate. BUG=chrome-os-partner:43807 TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console, verify that LED remains off. Press power button, verify that board wakes. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id695df9b5e75514f8f807a894b63f71676b66f92 Reviewed-on: https://chromium-review.googlesource.com/292317 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mec1322: Allow GPIO hibernate state to be specified at board-levelShawn Nematbakhsh2015-08-112-37/+43
| | | | | | | | | | | | | | | | Add a new board-level function board_get_gpio_hibernate_state which can optionally be defined to set the desired state of a GPIO during hibernate. BUG=chrome-os-partner:43807 TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console, verify that LED remains off. Press power button, verify that board wakes. BRANCH=None Change-Id: Ica11554e231e88773c3e139fea4622377ebe1e42 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/292471 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* it8380dev: fix hooks task won't wake up if timer overflowDino Li2015-08-112-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | symptom: Unexpected watchdog reset console message if watchdog is enabled. The IPC value of pre-watchdog warning is in idle task. duplicate: set time_us = 0xff000000 when timer init, watchdog will reset after about 18 seconds. also fix: reload the watchdog counter while flash write. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. enable watchdog. 2. no unexpected watchdog reset. 3. ectool "flashwrite 0x20000 ec.RW.bin" no watchdog reset. Change-Id: Ife10c2ead9c76462a865e694543e862b387d3b49 Reviewed-on: https://chromium-review.googlesource.com/292071 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* cr50: remove unused register definitionsVadim Bendebury2015-08-112-18372/+0
| | | | | | | | | | | | | Let's just keep one hardware version at a time. BRANCH=none BUG=chrome-os-partner:43791 TEST=make buildall -j Change-Id: I2e8c40e28638d461fa4ff14ad97ca5da55b33dd2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/291856 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: code modifications to support FPGA B1Vadim Bendebury2015-08-117-4780/+10264
| | | | | | | | | | | | | | | | | | | | | | | | The new FPGA version adds a lot of few features, while temporarily cutting off some existing capabilities like clocking configuration (hardwared clocks used instead), pinmux assignment for SPS interface (hardwared connections used), etc. This patch removes some now unused code, modifies some configuration items and adds TODO_FGPA comment blocks highlighting code which needs to be reviews next time FPGA version changes). The new register definitions file is derived from hardware description. BRANCH=none BUG=chrome-os-partner:43791 TEST=with these changes in place the B1 board boots to the console prompt. Change-Id: I78ec6b2831a44cbfd40ee726a5d3c2cc11bf2cfa Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/291855 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: add polling uart implementationVadim Bendebury2015-08-112-1/+90
| | | | | | | | | | | | | | | | | | | This code kicks in when the target is compiled with CONFIG_POLLING_UART defined. This ensures that each message sent to the console is drained completely before the code proceeds, which helps debugging early bringup issues. BRANCH=none BUG=chrome-os-partner:43791 TEST=with this code enabled was able to debug cr50 bringup on the new core version. Change-Id: Iab42370d64d17ecc5210bd4db1f2c5f19b40bce8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/291853 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* USART: Split RX driver between L and F familiesAnton Staaf2015-08-108-14/+91
| | | | | | | | | | | | | | | | | | | | The USART peripheral in the L and F families is different enough to need different receive drivers. In particular, the L family USART perihperal has no way of disabling the overflow error bit. So for that family we check and clear the bit, and keep a count of overflows. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Iea26c242d5177afd552a3bd4d6ab1a9c7a65f90e Reviewed-on: https://chromium-review.googlesource.com/288978 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* stm32: Deprecate SPI protocol version 2.Aseda Aboagye2015-08-081-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Now that v3 support is in the cros_ec kernel driver and depthcharge, deprecate support for the old v2 protocol. At some point in the future, support for the v2 protocol will dropped entirely. Boards that require support for the V2 protocol should enable the following config option. #define CONFIG_SPI_PROTOCOL_V2 BUG=chrome-os-partner:20533 BRANCH=None TEST=make -j buildall tests TEST=Flash jerry, AP & EC boot successful. TEST=`ectool protoinfo` shows only version 3 supported on jerry. TEST=Flashrom still works on jerry. Change-Id: I72d3aee00879314b936cc0b1002c9883550b1f1a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/291411 Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mec1322: add EC_FLASH_PROTECT_ALL_NOW support for external flashAndrey Petrov2015-08-061-27/+84
| | | | | | | | | | | | | | | | | | When flash_set_protect() is called pretend to activate "ALL" protection, and report it active if asked. This persists through sysjump and cleared on reboot/reset. BUG=chrome-os-partner:43323 TEST=Cyan. "flashinfo" should show "all_now", after "flashwp now" called, but only if WP is active and RO protection is activated earlier BRANCH=strago-7287.B Change-Id: I042e5311d79b7ef8e5bc3917662df1edab0e65cb Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/290813 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* it8380dev: speed up flash verifyingDino Li2015-08-061-2/+3
| | | | | | | | | | | | | | | | | | | | No need to use EC in-direct fast read for verifying, just a pointer. symptom: ectool erase 128KB RW image will show "Timeout waiting for EC response", but the erase is success. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=ectool erase RW image will show the correct message. Change-Id: Ie07d087ec004edc730bd084dd2e9b541f84adc2b Reviewed-on: https://chromium-review.googlesource.com/290525 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: fix KB init state abnormalDino Li2015-08-061-1/+0
| | | | | | | | | | | | | | | | | | | | Let keyboard_raw_task_start() function enable key scan interrupt. symptom: When any key is pressed while powering on the system. Console message "KB init state" will show no key pressed. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console message "KB init state" normal Change-Id: I49fcbc4c6c40d0c7e551631466a4ef4c2215a892 Reviewed-on: https://chromium-review.googlesource.com/290508 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* lm4: Add debug output for overlapping HCs.Aseda Aboagye2015-08-051-1/+4
| | | | | | | | | | | | | | | | | | | | | | Currently, when a host command is received which would overlap with an ongoing host command, we ignore it silently. This commit simply logs a line to the EC console stating that we are ignoring the overlapping host command. BRANCH=None BUG=chrome-os-partner:23806 TEST=make -j buildall tests TEST=Build, flash, and boot samus. Using ectool, read 64K from flash while also querying the current EC switch positions. Observe the log message being printed to the EC console. Change-Id: Ic0d249ccec2efb9600bcf8567392add1ee6295d9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/290545 Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* it8380dev: change PNPCFG base address to 4E/4FDino Li2015-08-041-2/+2
| | | | | | | | | | | | | | | | | Always reserved 2E/2F for super I/O. This can avoid conflict with super I/O base address. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=make buildall -j Change-Id: I67a37355e320e289fb1f58c7356a1592f7645d21 Reviewed-on: https://chromium-review.googlesource.com/290087 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: fix keyboard no break codeDino Li2015-08-041-0/+10
| | | | | | | | | | | | | | | | | Wake up task to send the remaining scan codes after OBE(host read data) or IBF(host send command/data). Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EC complete sending scan codes. Change-Id: Ie71140bbdfe5fcaccd5d16fd35b426004c218ba8 Reviewed-on: https://chromium-review.googlesource.com/290088 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: modify sspi moduleDino Li2015-08-041-22/+33
| | | | | | | | | | | | | | | | | We need to modify SSPI module to fix compile fail due to SPI flash common code changed. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console "spi_flashinfo" OK Change-Id: I83bb645eff1e5874d849056df518eea92340c39e Reviewed-on: https://chromium-review.googlesource.com/290089 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* npcx: Fix termination of chip revisionRandall Spangler2015-08-041-1/+2
| | | | | | | | | | | | | | | | system_get_chip_revision() would return a string which lacked the terminating null. Increase the string length and enforce termination. BUG=chromium:511405 BRANCH=none TEST=version; should show chip revision without garbage chars at end Change-Id: Icb9e36c5bfdf7de7400e5316934ccf28b4b57898 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/290392 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com>
* tasks: Remove most task_start_called() calls.Aseda Aboagye2015-08-012-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Now that HOOK_INIT hooks are called from a task switching context, most calls to task_start_called() should no longer be needed. This commit removes them. BRANCH=None BUG=chrome-os-partner:27226 TEST=make -j buildall tests TEST=Flash EC image onto samus and verify EC boot, AP boot, keyboard, lid, and tap-for-battery all functional. TEST=Flash EC image onto samus_pd and verify charging still works. TEST=Flash EC image onto ryu(P3) and verify that EC boot. TEST=Added ASSERT(task_start_called()) to the places where I removed task_start_called(). Booted samus, samus_pd, cyan, and ryu with AC inserted and verified that no ASSERT's were hit upon boot. Change-Id: Ic12c61862e85ca3a0a295beedbb4eeee6d5e515b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/285635 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
* mec1322: Fix dedicated SPI port accessShawn Nematbakhsh2015-08-011-1/+7
| | | | | | | | | | | | | Correct spi_rx_option table, and use correct port for kunimitsu. BUG=chrome-os-partner:42304 TEST=Burn + boot glados BRANCH=None Change-Id: Ic52ecb48102a74d3c17ab06b6da24ee40659ef86 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289868 Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* stm32: spi: Add lock around spi_transactionGwendal Grignou2015-08-011-0/+6
| | | | | | | | | | | | | | Like the implementation for mec1322, add a lock around spi_transaction. It prevents 2 tasks from accessing a given bus at the same time. BRANCH=smaug TEST=Check the BMI160 FIFO corruption disappeared in SPI mode. BUG=None Change-Id: I9e8a9e39ca96ea56692e3125930ab05ae6ef143f Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289856 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: make i2c transactions faster by not sleeping taskAlec Berg2015-08-011-36/+29
| | | | | | | | | | | | | | | | | | Modify i2c driver on mec1322 to change from sleeping and waking on i2c interrupt, to just doing a blocking wait for i2c transfer to complete. This greatly improves the i2c transaction time on fast busses. BUG=chrome-os-partner:43416 BRANCH=none TEST=test on glados. test can talk to battery and PD MCU. Use logic analyzer to see delay between bytes during an i2c transfer. The delay goes from ~70us to ~4us. Change-Id: Iee2a903d27b2e50e54d64bd6d5ed4920293fe575 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/289667 Reviewed-by: Shawn N <shawnn@chromium.org>
* stm32: Enable 3rd SPI interfaceGwendal Grignou2015-07-303-3/+20
| | | | | | | | | | | | | | | | Remove assumption of only one SPI master going to the SPI flash. SPI3 can be used as second SPI master. Define a new module type, SPI_FLASH, that can be turned on/off when flash is not in used without impacting other SPI masters. BRANCH=smaug BUG=chrome-os-partner:42304 TEST=Test on Ryu board. Change-Id: Ie72471cea6f0a357ffee055a610d032580a794e7 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288514
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