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* cr50: Add console and TPM vendor commands to get/set board IDstabilize-9592.82.Bstabilize-9592.67.Bstabilize-9592.55.Brelease-R60-9592.BPhilip Chen2017-06-302-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds vendor and console commands to read and write the board ID space in the INFO1 block. Current image's board ID settings are saved in the image header by the latest codesigner. Board ID write attempts are rejected if the board ID space is already initialized, or if the currently running image will not be allowed to run with the new board ID space settings. Error codes are returned to the caller as a single byte value. Successful read command returns 12 bytes of the board ID space contents. The console command always allows to read the board ID value, and allows to write it if the image was built with debug enabled. BUG=b:35586335 BRANCH=cr50 TEST=as follows: - verified that board ID can be read by any image and set by debug images. - with the upcoming patches verified the ability to set and read board ID values using vendor commands. Change-Id: I35a3e2db92175a29de8011172b80091065b27414 Signed-off-by: Philip Chen <philipchen@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/522234 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit ee545922389739b39cc0ac7e0f0d1dd8c2c67607) Reviewed-on: https://chromium-review.googlesource.com/557504
* tcpm: it83xx: reload cc parameter setting during initializationDino Li2017-05-251-0/+1
| | | | | | | | | | | | | | | | The trimmed value of CC parameter setting registers (port0: ff3760h ~ ff3763h, port1: ff3860h ~ ff3863h) will be reset to default after a soft reset (system_reset()). BRANCH=none BUG=none TEST=Console command 'reboot' and checking if the value of cc parameter setting registers are correct (trimmed). Change-Id: Ibf9c72e8aeef36701d72bcb64529735295295cdf Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/513744 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mn50: socket controlsNick Sanders2017-05-251-0/+3
| | | | | | | | | | | | | | | | Add console and usb_spi commands to enable or disable IOs to the socket, so that it will not be powered if a chip is inserted, and control reset and boot_cfg. BUG=b:36910757 BRANCH=None TEST=Check no voltage when socket is disabled. Full spiflash compatibility. Change-Id: Ie4ce0613a868030833abfdccd827acce2753dc6f Reviewed-on: https://chromium-review.googlesource.com/509072 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* stm32f4: i2c: process stop condition after slave receiver executedWei-Ning Huang2017-05-231-22/+22
| | | | | | | | | | | | | | | | We need to process the stop condition after slaver receiver is executed, or else we will lost the last byte of the transmission. BRANCH=none BUG=b:38510075 TEST=`make BOARD=rose -j`, AP suspend/resume should complete within 3 secs Change-Id: I6390a908b6c05b875b8bb2c0a124292785110b20 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/512463 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* rose: spi: add SPI master halfduplex modeRong Chang2017-05-221-27/+60
| | | | | | | | | | | | | | | | This change adds 3-wire mode support in STM32 SPI master driver. BUG=chromium:688979 TEST=manual enable CONFIG_SPI_HALFDUPLEX read id from SPI heatmap sensor BRANCH=none Change-Id: I09139dcbfe39a427721451db6842ea712abf2e33 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444630 Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: system: Fixed bug that ec received unexpected rtc interruptMulin Chao2017-05-191-3/+6
| | | | | | | | | | | | | | | | | | | | | In old system driver, ec clears "Predefined Time Occurred" (PTO) flag before setting a new alarm (PT field in WTC). If PT field is the same as the first 25 TTC bits at this moment, we might receive unexpected rtc interrupt again. This CL sets new alarm first then clears PTO flag to make sure rtc interrupt is issued from new alarm. BRANCH=none BUG=b:38310685 TEST=Duplicated the same symptom by the script in issue 38310685 on gru. No symptoms occurred with the same script for 3 hours by applying this CL. Change-Id: Ia6410d6aa4ef8e2acb7bfadf9192d619045bfa58 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/508572 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: avoid infinite looping w/ out of range inputsMarius Schilder2017-05-181-970/+981
| | | | | | | | | | | | | | | | | Make the dcrypto ecdsa verify code check that r,s are in range, and not depend on the caller C code to have done so. For instance, s equal to 0 would result in infinite loop during computation of its modular inverse. BRANCH=none BUG=b:35587381 TEST=TCG tests pass Change-Id: I13f7811be030aed9feaa11c45dc68d4bfd08fb76 Reviewed-on: https://chromium-review.googlesource.com/508819 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* it83xx: ec2i: move 'ec2i_setting' to header file of chipDino Li2017-05-181-0/+44
| | | | | | | | | | | | | | | This enum can be included in common. BUG=none BRANCH=none TEST=build boards: it83xx_evb and reef_it8320 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id7014b7de170cb3324c45d43fbf04ebe48a69f5e Reviewed-on: https://chromium-review.googlesource.com/505864 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* hammer: Make keyboard work at firmware screenNicolas Boichat2017-05-184-25/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First, libpayload expects the keyboard interface index to be 0. Then, hid_iface_request needs to reply to USB_HID_DT_HID request with the content of struct usb_hid_descriptor. With current code, the variable name is generated (and therefore hard to guess), so we create a new set of macros so that we can use a specific variable name. Also, add support for HID Get_Protocol and Set_Protocol, as they are compulsory for devices supporting boot protocol, even though those are mostly no-op for now. Finally, add a note regarding USB HID keyboard boot protocol, to make sure that we do not accidentally change the report format. BRANCH=none BUG=b:36538963 TEST=Keyboard works in FW screen, both trackpad and keyboard still work when AP has booted. TEST=hammer/staff can still be updated (both RO from RW, and RW from RO) Change-Id: Ibea4888385909c9ce3b430464e5805c039d4b9ed Reviewed-on: https://chromium-review.googlesource.com/505796 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* config: allow increasing i2c host packet buffer size with configWei-Ning Huang2017-05-182-2/+4
| | | | | | | | | | | | | | | | | | Some chip supports two owned slave address. The second slave address is used for other purpose such as board specific i2c commands. This option can be set if user of the second slave address requires larger host packet er size. BRANCH=none BUG=b:37187312 TEST=`make BOARD=rose -j` Change-Id: I8d0b04bf4dded55e3957c7b25d849663299593e5 Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/472288 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* stm32f4: Add stm32f4 I2C slave driverRong Chang2017-05-182-1/+261
| | | | | | | | | | | | | | | | | | This patch clones I2C slave and hostcmd driver from stm32f0. This patch contains contribution from Wei-Ning Huang <wnhuang@chromium.org> for fixing i2c slave transmitter (CL:471726). BUG=chromium:688979 TEST=build and load on dev board, run i2cget/set on host and check return value. BRANCH=none Change-Id: I3d159d5bdd4bda6c229cf6d275ab4982836628dc Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/461037 Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
* reef_it8320: initial reef_it8320 boardDino Li2017-05-181-1/+2
| | | | | | | | | | | | | | This change is based on reef's board code and modified for it8320. BUG=none BRANCH=none TEST=Run the entire faft_ec suite and passed. Change-Id: I8977d7431eb0a97ceb4ee1dfd11a2c4433687db0 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/487792 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* usb_hid_touchpad: Add config options to set dimensionsNicolas Boichat2017-05-181-73/+29
| | | | | | | | | | | | | | | | | | | | | | In principle, trackpad dimensions (logical and physical), can be probed from the trackpad at runtime, but this would slow down setup time, as we need to wait for the trackpad to be initialized to read those. Also, we do not have a framework to generate HID report at runtime, and a new base with new trackpad would probably require a new overlay anyway. Also, set appropriate (temporary) values for both hammer and staff. BRANCH=none BUG=b:38277869 TEST=Connect hammer/staff to host, correct logical dimensions are shown in evtest, and resolution is always 32. Change-Id: I39b84274d71ca2f4e285f3324c0841331aae9bc1 Reviewed-on: https://chromium-review.googlesource.com/505856 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: remove code that was used to work around sys_rst issuesMary Ruthven2017-05-161-6/+0
| | | | | | | | | | | | | | | | | | | | | | | Cr50 holds the EC in reset when it wants to flash the EC or AP. This will trigger a pulse on the tpm reset signal. In early Cr50 versions when the tpm was reset we would reboot cr50, so we added some code to prevent cr50 from resetting itself when the update was going on. sys_rst_asserted would check if there was an update going on and ignore the signal if update in progress was true. At the end of the update the deferred function was used to reset Cr50 after the update was complete. None of this is needed anymore. We can just release the EC from reset at the end of the update. This change removes usb_spi_update_in_progress and the deferred update_finished. BUG=b:35571516 BRANCH=none TEST=flash the bob ec and ap using ccd. Change-Id: I79416dba178c06bbc7289ad96968ee4e61947c4c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/506571 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: drop obsolete/addressed TODOsVadim Bendebury2017-05-164-13/+0
| | | | | | | | | | | | | | There many TODOs sprinkled in the code, some of them have been addressed or do not apply any mode. This patch removes them. BRANCH=cr50 BUG=none TEST=built and ran cr50 on reef Change-Id: Ica6edb204e5cc0cc9dc7f0d43fd39e7ddaf56809 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/506496 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: remove duplicate SHA #definesnagendra modadugu2017-05-161-6/+2
| | | | | | | | | | | | | | | | Include the appropriate SHA header files and remove duplicate #defines. BRANCH=none BUG=none TEST=compilation succeeds Change-Id: I15b77c3f40a07af8ea397f41d671386f303287eb Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/505200 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* CR50: configure AES rand stallsnagendra modadugu2017-05-152-0/+13
| | | | | | | | | | | | | | | | | | | | | | This change configures the AES engine to a) enable rand stalls at 25% during regular operation through AES API's, and b) disable rand stalls when doing fixed-key bulk-encryption (e.g. NVRAM ciphering). TCG tests continue to complete in ~20 minutes (i.e. no noticable slowdown). BRANCH=none BUG=b:38315169 TEST=TCG tests pass Change-Id: I2d26d232491a27bffbbe0b5aedfebaf04e0ad509 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/502717 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* CR50: replace dcrypto_memset with always_memsetnagendra modadugu2017-05-156-23/+23
| | | | | | | | | | | | | | | | | | | | | | | always_memset() implements a version of memset that survives compiler optimization. This change replaces instances of the (placeholder) call dcrypto_memset() with always_memset(). Also add a couple of missing memsets and fix related TODOs by replacing memset() with always_memset(). BRANCH=none BUG=none TEST=TCG tests pass Change-Id: I742393852ed5be9f74048eea7244af7be027dd0e Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/501368 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* npcx: flash: Add write-protect support for internal flash of npcx7 ecstabilize-9554.BMulin Chao2017-05-122-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | In order to support write-protect mechanism for the internal flash of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by controlling the WP_L pin of internal flash. During ec initialization or any utilities related to access status registers, we'll protect them if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we only can unlock write protection of internal flash by rebooting ec. This CL also includes: 1. Add protect_range array of npcx7's internal flash (W25Q80) for write-protect mechanism. 2. Add bypass of bit 7 of DEVCNT. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. (Besides gru) Build poppy board and upload FW to platform. No issues found. Passed flash write-protect checking on npcx796f evb. Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/501727 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CR50: enable dcrypto random stallsnagendra modadugu2017-05-121-3/+6
| | | | | | | | | | | | | | | | | | Clean up a lingering TODO; enable random stalls (NOPs) at ~6% for crypto operations. BRANCH=none BUG=none TEST=TCG tests pass Change-Id: I46b2755d9f501eb4ec98c3184d1e14fbf118c718 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/501349 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Paul Scheidt <pscheidt@google.com>
* g: allow to select the default USB PHY at startup.Vincent Palatin2017-05-121-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | When (USB-)resuming from deep-sleep, ensure that we avoid switching back and forth the selected USB PHY at boot, in order to avoid having a short disconnection at resume. To achieve this, allow the board configuration to select the PHY it is really using with the CONFIG_USB_SELECT_PHY_DEFAULT configuration variable, still keep the default USB_SEL_PHY1 as before. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:38160821 TEST=manual: build 'proto2' firmware with CONFIG_LOW_POWER_IDLE defined, with the chip connected to the host on PHY A, make the host issue a USB Suspend then resume and see no disconnection. Change-Id: I7abd5e338e5c688c2dd486293f520049cdfd273b Reviewed-on: https://chromium-review.googlesource.com/501947 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* stm32: add clock configuration for stm32f412 to run at 96 MHzWei-Ning Huang2017-05-122-5/+23
| | | | | | | | | | | | | | Add clock definition for stmf412. New stm32f4 chip variant will have to define their own clock definitions. BUG=b:37187312 TEST=`make BOARD=rose- j` Change-Id: Ie053298d2f1255d7bc152f6018a674281bda7004 Reviewed-on: https://chromium-review.googlesource.com/487848 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* mn50: initial checkinNick Sanders2017-05-126-28/+102
| | | | | | | | | | | | | | | | This firmware supports a board used to initialize firmware on new cr50 parts. BUG=b:36910757 BRANCH=None TEST=boots on scribe board, spi/usb/uart/i2c functionality works. TEST=cr50 boots on reef, CCD EC+AP SPI/UARTS work Change-Id: I48818225393a6fc0db0c30bc79ad9787de608361 Reviewed-on: https://chromium-review.googlesource.com/437627 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* CR50: constant time padding check routinesnagendra modadugu2017-05-101-23/+53
| | | | | | | | | | | | | | | | | Rewrite RSA padding-check routines to complete critical section in constant time. BRANCH=none BUG=b:35587381 TEST=TCG tests pass Change-Id: I8815f5fcabad1d966e6e17027bde836b53c5f6be Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/498856 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* npcx: system: Add support for npcx7 series ecMulin Chao2017-05-096-255/+528
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL implements two methods for hibernating on npcx7 ec. One is using PSL (Power Switch Logic) circuit to cut off ec's VCC power rail. The other is turning off the power of all ram blocks except the last code ram block. In order to make sure hibernate utilities are located in the last code ram block and work properly, we introduce a new section called 'after_init' in ec.lds.S. We also moved the hibernate utilities, workarounds for sysjump and so on which are related to chip family into system-npcx5/7.c. It should be easier to maintain. It also includes: 1. Add CONFIG_HIBERNATE_PSL to select which method is used on npcx7 for hibernating. 2. Add new flag GPIO_HIB_WAKE_HIGH to configure the active priority of wake-up inputs during hibernating. 3. Add DEVICE_ID for npcx796f. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. Build poppy board and upload FW to platform. No issues found. Make sure AC_PRESENT and POWER_BUTTON_L can wake up system from hibernate. Passed hibernate tests no matter CONFIG_HIBERNATE_PSL is enabled or not on npcx796f evb. Change-Id: I4e045ebce4120b6fabaa582ed2ec31b5335dfdc3 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/493006 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: keyboard: Add quasi-bidirectional buffers support on npcx7 ec.Mulin Chao2017-05-062-0/+11
| | | | | | | | | | | | | | | | | | | This CL added the support for the quasi-bidirectional buffer which has an open-drain output and a low-impedance pull-up resistance on KSO pins. The low-impedance pull-up is active when ec changes the output data buffers from 0 to 1, thereby reducing the low-to-high transition time. Add CONFIG_KEYBOARD_KSO_HIGH_DRIVE to enable/disable this feature for npcx7 series ec. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. Build poppy board and upload FW to platform. No issues found. Change-Id: I138f0e433394816e1e5c58b5053580f202c1ac48 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/497189 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: adc: Add support for npcx7 series ecMulin Chao2017-05-061-0/+7
| | | | | | | | | | | | | | | | | This CL added the support for additional 5 adc channels on npcx7 series ec. The pin-mux functionality of adc channels was already introduced in CL 481561. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. Build poppy board and upload FW to platform. No issues found. All 10 adc channels passed the test on npcx796f evb. Change-Id: I2c7458958ff659fce78f265eefa160050dee7daf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/497526 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip/stm32/usb_i2c: Remove obsolete implementationNicolas Boichat2017-05-052-322/+0
| | | | | | | | | | | | | | | Since a04fc68e721 "usb_i2c: refactor into common", the code in chip/stm32/usb_i2c.* is dead, let's remove it to avoid confusion. BRANCH=none BUG=b:35578857 TEST=On hammer, userspace application can still talk to trackpad. Change-Id: Idd9cc1109c80f3949fa8c4e50f4fe2e267d5a7ae Reviewed-on: https://chromium-review.googlesource.com/492768 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Chun-ta Lin <itspeter@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* npcx: i2c: Add support for npcx7 series ecMulin Chao2017-05-046-61/+257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL added support for 8 i2c controllers and 11 i2c ports in npcx7 series ec. we also added i2c-npcx5/7.c and moved the functions related to chip family to them. (Such as i2c_port_to_controller(), i2c_select_port() and so on.) Note the layout and bit position of i2c registers which are accessed in these functions are irregular between npcx5 and npcx7. We think abstracting them from i2c.c is easier to maintain. In this CL, we also modified the checking rule for I2C_PORT_COUNT in task.h in order to prevent compiler error. So far, the ECs besides stm32 only use TASK_EVENT_I2C_IDLE to wait for i2c hardware completes its job. Put (I2C_PORT_COUNT > TASK_EVENT_MAX_I2C) checking rule for all ECs seems not suitable. It also includes 1. Remove useless NPCX_I2C_PUBIT macro function. 2. Remove useless NPCX_PWDWN_CTL_COUNT in registers.h. 3. Add CGC_OFFSET_I2C2 and CGC_I2C_MASK2 to power down the other 4 i2c controllers of npcx7 ec. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. Build poppy board and upload FW to platform. No issues found. All 8 i2c controllers and 10 ports (npcx796f supports PSL.) passed i2c stress tests on npcx796f evb. Change-Id: I2b5076d21bcd0f8d17fd811cad2ff7bd200b112a Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/487541 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hammer: Pulse detection pin on USB wake eventNicolas Boichat2017-05-021-0/+9
| | | | | | | | | | | | | | | | | | When usb_wake is called (key press, trackpad event), pulse detection pin for 100us. This allows Lid EC to wake the AP even when it is in deep S3 mode, where normal wake using USB lines does not work. BRANCH=none BUG=b:35775062 TEST=Flash hammer, looks at poppy console: base power is not disconnected, but events appear in the console. Change-Id: I7b8ee407046d4caa1ce75190c30d693b71b00d2e Reviewed-on: https://chromium-review.googlesource.com/448380 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/usb: More reliable implementation of usb_wakeNicolas Boichat2017-05-021-6/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | Current usb_wake was sleeping between setting and clearing RESUME bit, which is unprecise. Instead, we count ESOF interrupts in usb_interrupt to detect when to clear RESUME. It is also important that usb_wake does not block, as the calling task (e.g. keyboard scanning) must continue to service events while the USB device is resuming. BRANCH=none BUG=b:35587173 TEST=Connect hammer, force autosuspend using: DEVICE=$(dirname $(grep 5022 /sys/bus/usb/devices/*/idProduct)) echo 500 > $DEVICE/power/autosuspend_delay_ms echo auto > $DEVICE/power/control Wait a second, type something quickly, verify that no keys are lost. Change-Id: I53b46cce5a4adb0ee4c4a7e9f935c00f7f321636 Reviewed-on: https://chromium-review.googlesource.com/490129 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: clock: misc fixesDino Li2017-05-021-46/+4
| | | | | | | | | | | | | | | | | | | | | 1. Disable USB debug interface: If we don't use GPIOH.5/6 pins for debugging, we should disable it to prevent any chances of entering debug mode. 2. command_idle_stats() behind CONFIG_CMD_IDLE_STATS: We can exclude this console command if we don't use it. 3. Remove 'dsleep' console command: DEEP_SLEEP_ALLOWED macro is enough for us. BRANCH=none BUG=none TEST=bit7 at 0xF02030(MCCR register) is cleared after initialization. Change-Id: If34e9738351459891be8c9a6619384adbfe26335 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/487843 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tcpm: it83xx: added chip infoDino Li2017-05-011-0/+2
| | | | | | | | | | | | | | | We can get the correct chip info after the change was made. BRANCH=none BUG=none TEST=console message: [0.013915 TCPC p1 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec] [0.018054 TCPC p0 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec] Change-Id: I4eb94967acb351559e745ed1c4e34a4c58f41e14 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/487767 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* rose: stm32f4: fix DMA macro to get ISR bitsRong Chang2017-04-261-1/+1
| | | | | | | | | | | | | | | | Rose reads heatmap via halfduplex SPI sensors. This change fixed the macro to get correct DMA ISR register. BUG=chromium:688979 TEST=manually run spixfer in EC console and check return value BRANCH=none Change-Id: I303bdb483032c02d01fd322095f17dba37555447 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/444631 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rose: add stm32f4 SPI master supportRong Chang2017-04-262-1/+40
| | | | | | | | | | | | | | | | This change adds stm32f4 stream DMA support and a config option to use first SPI port as master. BUG=chromium:688979 TEST=build and load on stm32f4 dev board BRANCH=none Change-Id: I2b504be70e0fbb17f16ce070119ae4715c88333a Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438911 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rose: remove dependency between stm32f4 I2C master and slave driversRong Chang2017-04-261-0/+2
| | | | | | | | | | | | | | | Frequency change hooks are needed in I2C master mode only. BUG=chromium:688979 TEST=remove CONFIG_I2C_MASTER and build rose target BRANCH=none Change-Id: I7244af73f97799d396d8680c8f131e8746a56e18 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438910 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Wei-Ning Huang <wnhuang@chromium.org>
* rose: enable stm32f4 EXTI IRQsRong Chang2017-04-261-0/+25
| | | | | | | | | | | | | | | This change copied gpio_init() from stm32f373 driver. BUG=chromium:688979 TEST=load on dev board and check button interrupt BRANCH=none Change-Id: I9dc12ffc02899211b6d07a640682899654c2bbed Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438909 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: peci: Fixed bug caused by wrong source clock of peci.Mulin Chao2017-04-261-2/+2
| | | | | | | | | | | | | | | | | | On npcx5, the peci speed should be 750K bps but we got 1.5M bps since selecting wrong source clock of peci. From the peci specification, the speed range is from 2K bps to 2M bps. That's why we still passed the peci test on npcx5's evb. This CL corrects the source clock of it from apb2 to fmclk and make sure the speed is 750K bps by the scope. BRANCH=none BUG=none TEST=Passed peci test on npcx5's evb and make sure the speed of peci is 750K bps. Change-Id: Ic5c55f7be9be195182e4c4f4ad64b7426afd42db Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/486680 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: clock: uart: Add support for npcx7 series ec.Mulin Chao2017-04-254-103/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In old clock driver, the relationships between each clock sources are ambiguous. For example, we treat OSC_CLK and FM_CLK as the same but sometimes they're not on npcx5. (Only one OSC_CLK definition cannot present the npcx ec's clock tree very well.) This CL added FM_CLK, CORE_CLK, and APBx_CLK definitions and used macro functions to confine the limitation of each clock sources in clock_chip.h to make it more clearly. We also modified the uart driver and fixed its source clock to 15MHz so far in this CL. Since npcx7 already supports uart wake-up mechanism, we removed the functions of switching pins from UART to GPIO by CHIP_FAMILY definitions for saving code space. It also includes: 1. Remove useless CHIP_VERSION definition. 2. Move frequency multiplier values M/N for OSC_CLK to clock_chip.h 3. Add clock_get_fm_freq() for the modules rely on it. Ex, peci. 4. Add clock turbo utilities for npcx7 series. 5. Support uart wake-up mechanism for npcx7 series. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. Build poppy board and upload FW to platform. No issues found. Passed clock turbo, sysjump and wake-up from UART signals stress tests on npcx796f evb. Change-Id: Id01a8a5d0263f0d2438e6346dfa33bcdef2be56e Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/486821 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: i2c: Fix i2c freq setting when APB clock is 15 MHzCHLin2017-04-251-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | To configure 1 MHz speed when the APB clock is 15 MHz, the firmware currently sets the SCLHT register to 4. However, we found out that writing 4 to this register (and to SCLLT register) is illegal and results in unexpected results. So there is a need to write 5 in that case. However, this means that the actual i2c frequency will be 750 KHz. To get a higher i2c clock frequency, there is a need to run with a higher APB clock (and a higher core clock). For example, with APB set to 20 MHz, the i2c clock frequency is 833 KHz. In this CL, the i2c freq setting for APB clock=20 MHz is also added which may be used for NPCX7 in the future. BRANCH=none BUG=chromium:714314 TEST=No build error for make buildall(except gru). Use scope to capture SCL signal on npcx5 EVB and make sure its freqency is about 750 KHz. Change-Id: I9025344e6df4b584b203c8c59bb9875250d9fe4f Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/484202 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* it83xx: i2c: increase clock low timeout to maximumDino Li2017-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | This timeout is described in SMBus specification (25ms). Some I2C devices may required longer clock stretch (The I2C specification does not specify any timeout conditions for clock stretching). So we increase this timeout to maximum. NOTE: Because this codebase already handle timeout of an I2C transfer, so maybe we can disable this mechanism. But we don't have any register to execute this, so we maximize the timeout. BRANCH=none BUG=none TEST=console commands: i2cscan, battery, charger, and accelinfo. Change-Id: I5025f640c027105152247212fc688388f645c5ba Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/485203 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: Added CONFIG_SWITCH support.Dino Li2017-04-251-0/+1
| | | | | | | | | | | | | This change updates switch status to EC MEMMAP. BRANCH=none BUG=none TEST=Use 'mmapinfo' console command to verify lid status. Change-Id: I80b9e407a8793f2de84011473cd51c5453d77859 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/483259 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Add support for npcx7 series ec.Mulin Chao2017-04-256-300/+1020
| | | | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. Add gpio_chip-npcx5/7.h files and move all macro functions related to chip family to them. (Move wui macro func from gpio_wui.h to them.) 2. Replace alternative and low-voltage mapping table with macro function NPCX_ALT_TABLE and NPCX_LVOL_TABLE. 3. Add UART wakeup mechanism in __gpio_wk1h_interrupt() ISR. 4. Add gpio register definitions of npcx7 family in registers.h. 5. Add GPIO_LOCKED flag for lock functionality. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Passed validation for all GPIO functionalities on npcx5m6g and npcx796f evb. Change-Id: I60c30ce223629a0d8cb767a54a0a9b02a69de9c5 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/481561 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Introduce npcx7 series ec chip definitions and configurations.Mulin Chao2017-04-255-36/+154
| | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish which npcx's ec is used on the board. 2. Add config_chip-npcx5/7.h files and move features depend on chip family into them. 3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on npcx7 ec. We'll use them later in gpio/system/flash drivers. 4. Add ram size checking for all npcx ec series. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/481560 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "system: Shutdown AP before entering hibernate mode"Duncan Laurie2017-04-218-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 20c439be209a9cc0bb949ad21f289c453126395f. Reason for revert: This breaks hibernate on skylake boards and needs to be tested on more than just kevin before submitting. BUG=chromium:702451 BRANCH=none TEST=power down and successfully hibernate on Eve Original change's description: > system: Shutdown AP before entering hibernate mode > > BUG=chromium:702451 > BRANCH=none > TEST=manually test on gru: confirm > 'Alt+VolUp+h' puts gru in hibernate mode and > AC plug-in wakes it up. > > Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 > Reviewed-on: https://chromium-review.googlesource.com/470787 > Commit-Ready: Philip Chen <philipchen@chromium.org> > Tested-by: Philip Chen <philipchen@chromium.org> > Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> > TBR=rspangler@chromium.org,aaboagye@chromium.org,philipchen@chromium.org # Not skipping CQ checks because original CL landed > 1 day ago. BUG=chromium:702451 Change-Id: Ie847a5e3efb28256b00ddc6534d8ae6bbbba7121 Reviewed-on: https://chromium-review.googlesource.com/482989 Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* npcx: gpio: Change second tachometer source from TB2 to TA2.Mulin Chao2017-04-182-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | In npcx's fan driver, ec selected mode 5 and capturer A as tachometer's input. Choosing TB2 as the second tachometer source is not correct since we didn't initialize the registers for TB2. This patch modified the second tachometer's input from TB2 to TA2 and passed the verification by following changes. 1. Add the second fan settings in pwm_channels, fans, and mft_channels arraies. 2. Modified ALTERNATE marco for pwm-type fans. 3. Set CONFIG_FAN from 1 to 2. 4. Set NPCX_TACH_SEL2 to 1 to test tachometer input 2. (ie.GPIO73/A6) BRANCH=none BUG=none TEST=test dual fans with fanset command on npcx_evb and use faninfo for verifying. Measure the actual rpm by scope. Change-Id: Ia1af2732d9a64e24285d12371223eb0e77e53357 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/472310 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: remove console command "rwreg"Dino Li2017-04-181-86/+0
| | | | | | | | | | | | | We don't use this command so remove it to save flash space. BUG=none BRANCH=none TEST=build all. Change-Id: I7279c56add6ad2b07f0a9b3cdc0ed849f8176e61 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/479976 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: fan: Simplified TACH_TO_RPM formula and fixed bugs.Mulin Chao2017-04-181-48/+92
| | | | | | | | | | | | | | | | | | | | | | This CL simplified TACH_TO_RPM formula and abstracted two definitions (PULSES_ROUND and RPM_DEVIATION) for the pwm-type fan used on boards. The developers can modify them in board-level driver if fan doesn't meet the default spec. In this CL, it also fixed: 1. Declare rpm_pre as array if FAN_CH_COUNT > 1. 2. Add checking for the value of next duty of pwm. 3. Use TAPND pending bit to make sure TCRA is valid. BRANCH=none BUG=none TEST=test fan used in kahlee and Sunon fan with fanset command on npcx_evb and use faninfo for verifying. Measure the actual rpm by scope. Change-Id: Ieb07482eb359912286414ccb9738341d98ea99e4 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/472289 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec: add initial soraka related filesYH Lin2017-04-151-1/+1
| | | | | | | | | | | | | For now use the files from poppy. To be changed later on. BUG=b:36995255 TEST=emerge-soraka chromeos-ec Change-Id: Iaf0b2a359586dd4cfdba483a6836eefee06f82c1 Reviewed-on: https://chromium-review.googlesource.com/476934 Commit-Ready: YH Lin <yueherngl@chromium.org> Tested-by: YH Lin <yueherngl@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* system: Shutdown AP before entering hibernate modePhilip Chen2017-04-148-8/+8
| | | | | | | | | | | | | | BUG=chromium:702451 BRANCH=none TEST=manually test on gru: confirm 'Alt+VolUp+h' puts gru in hibernate mode and AC plug-in wakes it up. Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 Reviewed-on: https://chromium-review.googlesource.com/470787 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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