| Commit message (Collapse) | Author | Age | Files | Lines |
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BUG=b:158019009
TEST=make -j BOARD=cr50 CR50_DEV=1
Change-Id: If9554fcf499fb08b301d6f58764e9a4983b6884b
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227075
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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SQA images won't be built anymore. This change removes the SQA support.
It deletes all SQA ifdefs and replaces CR50_RELAXED with CR50_DEV.
BUG=b:158011401
TEST=manual
build regular image and check eraselfashinfo and rollback aren't
included.
build image with CR50_SQA=1 and check it's no different than the
regular image.
build DBG image and make sure it still starts open, it has the
eraseflashinfo and rollback commands, and it can flash old cr50
images.
Change-Id: I5e94c88b1903cfcf0eee0081fc871e55fc8586c7
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227149
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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Not sure why this board was kept in, probably because fizz was mixed
up with fuzz.
BUG=none
TEST='make buildall -j' succeeds
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: I4b08333d12bdfe8001b7e1c2b7c5860aef947a22
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227168
Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
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This patch assigns the bit offset 0 in TPM_BOARD_CFG register to
indicate the status of INT_AP_L extension. The bit 1 means INT_AP_L
pulse extension is activated, and 0 means it is not.
BUG=b:148691139
TEST=tested on atlas and on careena.
1. Checked the default TPM_BOARD_CFG (PWRDN_SCRATCH21) value was zero
and the INT_AP_L assertion duration was 4~10 microseconds.
> md 0x400000f4 1 // memory dump on GC_PMU_PWRDN_SCRATCH21
400000F4: 0x00000000
2. Attempted to change the board configuration (with a hacked UART
command.). The register value was unchanged.
> brdcfg 0x01
TPM_BOARD_CFG = 0x00000000
> md 0x400000f4 1
400000F4: 0x00000000
3. Forced to write the board configuration with a hacked UART command.
The register value was changed.
> brdcfg 0x01 force
TPM_BOARD_CFG = 0x80000001
> md 0x400000f4 1
400000F4: 0x80000001
4. Checked the INT_AP_L assertion duration extended to 110
microseconds or longer.
5. After cr50 deep sleep, checked the pulse duration was still
extended.
- turned AP off.
- disconnected Suzy-Qable.
- waited three seconds
- connected Suzy-Qable, and checked the reset cause was 'hibernate
rbox'.
> md 0x400000f4 1
400000F4: 0x8000001
6. With 100 usec long INT_AP pulse, checked trunks_cliend
regression_test, stress_test and ext_command_test runs good.
Checked dmesg and found no TPM errors through all tests.
(ap) $ trunks_client --regression_test
(ap) $ trunks_client --stress_test
(ap) $ trunks_client --ext_command_test
7.checked no character loss during uart_stress_tester.
(chroot) $ uart_stress_tester.py -c -t 600 /dev/ttyUSB2 /dev/ttyUSB1
8. the shortest duration of INT_AP_L assertion and deassertion
observed in logic analyzer were 110 usec and 152 usec.
9. measured the depthcharge exit timestamp and cr50 flash time with
or without INT_AP pulse extended to 100 usec, on atlas and helios:
-----------------+-------------------+------------------
| atlas | helios
-----------------+-------------------+------------------
boot (sec) | 1.398 -> 1.402 | 1.004 -> 1.011
cr50 flash (sec) | 10.800 -> 14.609 | 16.024 -> 16.466
-----------------+-------------------+------------------
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: I2b9f9defb63cf05f9d91b741ccb4b49c4c6bc8e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202839
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
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This patch adds the TPM vendor-defined register, TPM_BOARD_CFG,
which indicates the board configuration status. This register is
attributed as one-time-programmable and the value is maintained
across deep sleeps. Cr50 allows a write on this register right after
a cr50 reset until it receives a TPM2_PCR_Extend command.
BUG=b:148691139
TEST=none
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: I89ae5a53c15990ef78812aec5da81a59f04d7d98
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2202838
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
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This patch adds a feature to extend each level of GPIO_INT_AP_L at
least for 100 microseconds. The assertion (low GPIO_INT_AP_L)
duration might be shorter only if AP asserts a SPS CS before
INT_AP_L deassertion, because it means means AP recognized
GPIO_INT_AP_L assertion already.
This patch increases the flash usage by 280 bytes.
BUG=b:148691139
TEST=None
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: Ie74b236bc5352e9fc21fe600c12946e50955160a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114430
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
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The code opening the RO windows to make it possible to update or
enable the RO images, leaves the window open, allowing subsequent
writes into the RO space. It has been acceptable until now, because RO
updates are usually followed up by reboots.
With introduction of the AP RO hash, there is a need to close the
window (specifically, disable write access) when not in use. This
patch adds a function for that and uses the new function everywhere
where flash_open_ro_window() is called.
BUG=b:153764696
TEST=verified successful Cr50 RO and AP RO hash updates.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Ia595e5c7ce0beb1a67ef3513117984d18655a60c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2204973
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This adds plumbing necessary to invoke the AP RO verification function
in response to the operator entering the 'magic sequence' of holding
the power button pressed and pressing/releasing the refresh button
three times within five seconds.
The code used during the 'Open box RMA' verification process is used,
with the physical presence confirmation phase bypassed.
This patch also makes sure that attempts to use CCD to program AP or
EC flash while AP RO verification is in progress would fail.
BUG=b:153764696, b:154966209
TEST=with the next patch applied, generated AP integrity verification
data using the ap_ro_hash.py script and then ran the verification
procedure, observing the 'hash match' message on the Cr50
console.
Also verified that the Open Box RMA procedure still succeeds.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Ic101fb892554ebb05f9ebe6d1546bfb439f74043
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171399
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This patch adds code which accepts the vendor command communicating
the list of the AP firmware sections to verify and the expected
cumulative sha256 sum value of the sections.
The vendor command payload is checked for sanity: each range offset is
not expected to exceed 32M bytes (the largest possible SPI flash size)
and each size is not expected to exceed 4M bytes.
If any inconsistencies are found in the payload, or the flash
integrity space is already programmed, an error is returned to the AP.
It the command validity check succeeds, the payload of the vendor
command is prepended by a header including the number of the flash
regions to check and a 4 byte checksum of the stored information.
This combined information is stored in the dedicated H1 flash space,
specifically the RO_B region, at offset of 0x3000, 2K bytes page below
the region used for the flash log.
The valid RO range in upgrade_fw.c:set_valid_sections() is modified to
prevent erasing of the AP RO hash value during Cr50 RO updates.
The new file also introduces a function used to verify the AP flash
when requested. The returned value indicates one of three conditions:
- valid verification information not found
- AP flash integrity verification failed
- AP flash integrity verification succeeded
A new console command allows to examine the contents of the space
where the list of ranges and the sum are stored. CR50_DEV builds also
allow to erase the page.
BUG=b:153764696
TEST=with the rest of the patches applied verified successful
execution of the AP RO verification sequence.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: I1894ef897a86e9d60b9f5bcff3a680f632239e1b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171398
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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This patch makes it possible to check if the INFO1 Board ID space is
programmed or not.
BUG=b:153764696
TEST='make buildall -j'
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Ic771956a08e276c2e1a426729a8ecdae3f86a04f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2204974
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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The code which allows to read a section of AP or EC flash and
calculate the section's SHA256 sum does not allow calculating the sum
over multiple non-adjacent flash areas.
This patch changes the implementation to allow calculations over more
than one region. Initialization, calculation and reporting of the
result become three separate API entries.
The loop counting the number of the read flash chunks, is being
simplified, a watchdog kick added to the brief loop interruptions, as
it turns out that sleeping alone is not enough to prevent watchdog
expiration when calculating hash over large SPI flash ranges.
Also simplified prototypes for usb_spi_board_enable() and
usb_spi_board_disable().
BUG=b:153764696
TEST=created an RO descriptor for the Atlas DUT and verified that
'gsctool -O' succeeds.
Cq-Depend: chrome-internal:2939596
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Iec7b8634c7c80ebc7600c5b708879eb322bc7fec
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2163569
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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This is a minor API clean up, it is not entirely clear why const void
pointers were not used originally, but using this type for input data
(and void pointer for output) makes interfacing with the library much
easier.
Also modified cases where the first parameter of DCRYPTO_SHA1_hash()
was typecasted unnecessarily.
BUG=none
TEST=make buildall succeeds, Cr50 image supports booting a Chrome OS
device just fine.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: Ic8a670aa7b26598ea323182845c184b7f1d715a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2163568
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Remove 'deep sleep' and 'invalid' idle actions from the idle console
command.
BUG=b:156032428
TEST='idle s' and 'idle w' work when the console is open.
Change-Id: I9da2fa0d679ef89ecb2eaaad82541bd3e9e16140
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2189616
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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The recent interrupt pulse extension brought to fore an old bug where
the AP_INT_L pulse is generated by the SPS driver before the
controller is actually ready to accept the next SPI frame.
This patch rearranges the code to make sure that the pulse is
generated after all controller clean up.
BUG=b:154458891
TEST=verified that Atlas device is still booting fine. Will test it on
other devices which seemed to be triggering the bug.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: I480760b4afea24295f96abde2fc75c414017c27f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2171452
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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If UART-EC TX is disabled, the USB input data used to be ignored in
UART-EC TX interrupt handler, but it neglected to call uartn_tx_stop(),
which was a defect. In this patch, those data shall be ignored when they
arrive from USB (in USB RX stream handler), which is earlier than
UART-EC TX interrupt, and uartn_tx_start() won't be called.
BUG=b:153198965
TEST=Repeated to lock and open CCD, and checked EC-UART is RO or RW.
Checked EC-EFS2 working, and uart_stress_tester as well.
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: I1c3c2c5a7626850f6389616bbe1f69188d5eca6d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2135140
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
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A very few changes are needed to support the packet mode:
- provide functions to report how much room is left in USB/UART
transmit buffers;
- compile out cprintf/cprints/cputs just in case to be able to catch
cases where util_precompile.py fails to convert them for whatever
reason;
- do not add CR to every LF, this messes up packet transmissions, and
the terminal is doing the right thing anyways
- there is a problem with the USB channel in packet mode: the device
reboots as soon as an attempt to send something to the host is
undertaken. The problem can be rectified by disabling the deferred
function path in the Cr50 console USB channel. A bug was open to
track it down, but in packet mode using deferred function in this
path is less critical, as the amount of sent data always is at
least as much as the packet header size
BUG=b:149964350, b:152116489
TEST=with the rest of the patches applied packet mode console works
fine. When packet mode is disabled the conventional mode console
works fine.
Change-Id: Ib010cede36adc87cf80f49e5d76ec9e274d9e608
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114238
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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To avoid some sort of race in private-cr52 endpoint initialization,
which results in a reboot loop.
Calling usb_console_enable() in HOOK_LAST instead appears stable,
at cost of missing some early console output.
While at it, reduce some SRAM usage and improve legibility
by moving to bool from int.
Strictly opt-in; behavior unchanged for existing code.
BUG=chromium:1063240
BRANCH=cr50
TEST=make buildall; cr52 build w/ usb_console now enumerates w/o resets.
Signed-off-by: mschilder@google.com
Change-Id: I352edb4c045df401cb99573da5765b88deb45d0d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2111450
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Commit-Queue: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Auto-Submit: Marius Schilder <mschilder@chromium.org>
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This path removes CONFIG_USB_HID_KEYBOARD support and
CONFIG_USB_UPDATE support because they are not used in any cr5X
board configuration.
Ths patch also removes some subsidiary configs as upload hook script
guides.
> CONFIG_USB_PAIRING
> CONFIG_TOUCHPAD_VIRTUAL_OFF
> CONFIG_USB_CONSOLE_READ
BUG=none
BRANCH=cr50
TEST=make buildall
Signed-off-by: Namyoon Woo <namyoon@google.com>
Change-Id: Iafa553fdf58772744b1d9a5c7f5460f42264f468
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2103045
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
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This patch adds a test case for EC-EFS functions.
BUG=b:150650877
BRANCH=cr50
TEST=make run-ec_comm
make runhosttests
make buildall -j
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: I90cdc3aa73cf8946da4cf094de5ca0adfaaa0a7c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2096338
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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This patch supports EC-CR50 communication.
EC activates EC-CR50 communication by setting high DIOB3, and send
a command packet to CR50 through UART_EC_TX_CR50_RX. Cr50 processes
the packet, and sends a response packet back to EC. EC deactivates
EC-CR50 communication by putting low DIOB3.
This patch supports two kinds of EC-CR50 commands:
- CR50_COMM_CMD_SET_BOOT_MODE
- CR50_COMM_CMD_VERIFY_HASH
Cr50 stores some of EC-EFS context in a powerdown register before
deep sleep and restores it after wakeup.
This patch increases flash usage by 1456 bytes.
BUG=b:119329144
BRANCH=cr50
TEST=Checked "ec_comm" console command on Octopus and
reworked Helios.
Checked uart_stress_tester.py running without character loss.
Change-Id: I23e90b9f3e860a3d198dcee718d7d11080d06e40
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1961145
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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- add ec_efs, which tracks the system boot mode.
- add ec_comm.h header file for EC-EFS related functions.
- revised vboot.h header file.
BUG=b:141143112
BRANCH=cr50
TEST=none
Change-Id: Iec1bf466b832bac5ad6be8a52304c1d699a38fb2
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055363
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This CL separates the control on USB-UART bridge of EC device from
EC UART control. USB-UART bridge shall be enabled if CCD connection
is detected and the CCD capability is enabled. Otherwise, EC USB-UART
shall be disabled. By doing so, CCD capability can be observed even
when EC-CR50 communication enables EC UART.
This patch increases the flash usage by 204 bytes
BUG=b:148247228
BRANCH=cr50, cr50_mp
TEST=ran firmware_Cr50CCDServoCap on Helios.
> ccd
State: Locked
Password: none
Flags: 0x000001
Capabilities: 0000000000000000
...
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC I2C USBEC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: UARTAP+TX UARTEC USBEC
CCD ports blocked: (none)
> ccd
State: Opened
Password: none
Flags: 0x800001
Capabilities: 5555454115000000
...
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC I2C USBEC+TX
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX
CCD ports blocked: (none)
Change-Id: I6bb560a05831105ff68a9e13e4b28b002ed98096
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018061
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This uses gpio_set_wakepin() to setup the wake pins instead of writing
to the PINMUX EXITEN registers directly.
This patch reduces the flash usage by 248 bytes.
BUG=b:35587259
BRANCH=cr50
TEST=checked pinmux configuration hasn't changed on coral.
Checked firmware_Cr50DeviceState running good on coral.
Change-Id: Ic4ef1751e34b85ea2719f257ebd9b7ad52355eec
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2047923
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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If the board supports EC-CR50 communication, Cr50 enables both
rising/falling-edge triggered interrupt on DIOB3 pin and makes
it wakable as well.Cr50 connects GPIO_AP_FLASH_SELECT to DIOB4.
If the board does not support EC-CR50 communication, Cr50 connects
GPIO_AP_FLASH_SELECT to DIOB3.
If EC puts high on DIOB3 to activate EC-CR50 communication, CR50
enables UART_EC RX and TX.
BUG=chromium:1035706
BRANCH=cr50
TEST=none
Change-Id: I1221a1a19219274622ab710568ce7c66ab2f1da7
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1989581
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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Cr50 needs a cleaner way to enable and disable wakepins. This change
adds gpio_set_wakepin() to enable the wake pin or disable.
The gpio_set_flags() or gpio_set_flags_by_mask() remain unaffecting
wake-pin configuration.
This patch increases the flash usage by 16 bytes.
BUG=b:35587259
BRANCH=cr50
TEST=verify pinmux has the same output before and after the change on
octopus.
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/533674
Tested-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Commit-Queue: Namyoon Woo <namyoon@chromium.org>
Change-Id: I0387c673aedc046ce9cf6b5f0d683c40f3079281
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2044355
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This patch reduces redundant condition checking in connecting
or disconnecting UART TX.
BUG=none
BRANCH=cr50
TEST=manually checked ccd state with/without servo connection and/or
ccd connection.
[AFTER]
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: connected
CCD EXT: enabled
State flags: UARTAP UARTEC
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: disconnected
Servo: connected
CCD EXT: disabled
State flags:
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ccdstate
AP: off
AP UART: off
EC: on
Rdd: connected
Servo: undetectable
CCD EXT: enabled
State flags: UARTEC+TX I2C SPI
CCD ports blocked: (none)
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: UARTAP+TX I2C SPI
CCD ports blocked: EC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: disconnected
CCD EXT: enabled
State flags: I2C SPI
CCD ports blocked: AP EC
> ccdstate
AP: on
AP UART: on
EC: on
Rdd: connected
Servo: ignored
CCD EXT: enabled
State flags: UARTAP+TX UARTEC+TX I2C SPI
CCD ports blocked: IGNORE_SERVO
WARNING: enabling UART while servo is connected may damage hardware
Change-Id: Icea2978b15e15bbf7cea8e48fd2bf4fdecc78f46
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013823
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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This patch extends INT_AP_L pulses to be at least 6.5 micro seconds.
It is a tentative solution to to meet Intel TGL/JSL requirement on
interrupt duration.
BUG=b:130515803
BRANCH=cr50
TEST=checked INT_AP_L pulse length ranges extended to 6.5 ~ 11 usec
with logic analyzer on Hatch.
Checked dmesg and coreboot log has no TPM errors.
Change-Id: Iea8d0a779fff7cbda0c8647f3c1de719c3c3d7e0
Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2002958
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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There is no need to keep the code supporting chip factory mode in
Chrome OS production branches, this code is never used outside of the
chip factory environment.
BRANCH=cr50, cr50-mp
BUG=none
TEST=built an image, verified that an Atlas device boots up into the
previously created Chrome OS account.
Change-Id: If72635b014d15ef6e97fbc4fd5b54b61ec23299a
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994369
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
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The only board which would be built from this branch is Cr50. bds,
fizz and host boards are necessary for proper make infrastructure
operation and tests.
lm4 and npcx are chips used by the bds and fizz boards, so they are
also kept around.
BRANCH=cr50, cr50-mp
BUG=b:145912698
TEST='make buildall -j' succeeds
Change-Id: I937b2b8642c1fe91578fc9615438ae22c165b20f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986942
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Rolling back to 0.0.22 requires erasing the INFO1 rollback protection
space, as current RW level is at two, and 0.0.22 is at one.
The only way to erase INFO1 is to run a node locked prod signed 0.3.22
image. But 0.3.22 will destroy board ID along with the rollback spaces
AND it is not capable of rollback, so to roll back to a lower than
0.3.22 version one still needs to run the SQA image. 0.3.22 will not
allow to restore the Board ID either.
Another problem is that SQA image would update the rollback INFO1
space, thus again preventing 0.0.22 from running.
This patch alleviates the situation by allowing the SQA images to
write Board ID fields and preventing SQA images from updating rollback
space in INFO1.
BRANCH=cr50
BUG=b:146522336
TEST=with the new image was able to downgrade a device from 0.4.24 to
0.0.22
Change-Id: I8babf15ae32036dc612ae9c808c773a2b3355762
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1975092
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Change the OWNERS to cr50 team members and remove OWNERS files from all
subdirectories.
BUG=none
BRANCH=none
TEST=none
Change-Id: I5ddff7c433a55b6724d92c026e9e64e82e1492ad
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957850
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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CONFIG_DCRYPTO compiles and links thirdparty/libcryptoc for cr50.
CONFIG_LIBCRYPTOC does similar things for other boards that configures
it, including host. This resulted in cr50_fuzz having concurrent
recipes for libcryptoc, as it has both configs. This change separates
CONFIG_DCRYPTO from the responsibility of building and linking libcryptoc.
Libcryptoc is now solely handles by CONFIG_LIBCRYPTOC.
BRANCH=none
BUG=b:144811298
TEST=make -j buildall > /dev/null
Observed no more "warning: overriding recipe for target
'build/host/cr50_fuzz/cryptoc/libcryptoc.a' "
Change-Id: I2186cbead773629456da254df5f82b96e9646fc2
Signed-off-by: Yicheng Li <yichengli@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949554
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit a018043265ecb3466863ff9020ab25d552105c61)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956404
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
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Both RO and RW sections have their respective rollback spaces in
INFO1, but until now Cr50 code did not honor the RO binaries' headers
rollback maps and did not update the appropriate iNFO1 space.
With this patch both RO and RW info maps are updated to the lowest
level of the two images found in the flash when invoked during
board_init() or to match the currently active RO/RW when invoked
through vendor command indicating successful OS startup.
BRANCH=cr50, cr50-mp
BUG=b:136284186
TEST=tried the new image on a chip with freshly erased INFO1 space:
first running a DBG image, which does not touch INFO1 maps:
> vers
...
RO_A: * 0.0.11/bc74f7dc
RO_B: 0.0.11/4d655eab
RW_A: * 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
RW_B: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
..
> sysinfo
...
Rollback: 0/1/1 0/128/128
...
Then running an image with debug extensions disabled:
> vers
...
RO_A: * 0.0.11/bc74f7dc
RO_B: 0.0.11/4d655eab
RW_A: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d
RW_B: * 0.4.24/cr50_v2.0.2744-d79516a9d
...
> sysinfo
...
Rollback: 1/1/1 2/128/2
...
Change-Id: I259a3f46c03199633ca85389872449d667f172fb
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949548
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
(cherry picked from commit 94cfd7cee548047d8e0f5dee2995c4c03fba665d)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954342
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Cr50 firmware is required to update the rollback prevention map in
INFO1 for both RO and RW images.
This patch adds code to display the state of the RO map and both RO_A
and RO_B headers in addition to previously reported RW information.
BRANCH=cr50, cr50-mp
BUG=b:136284186
TEST=loaded the new image and observed reported rollback state:
> sysinfo
...
Rollback: 0/1/1 0/128/128
...
Change-Id: I32206545b6a59a5693e4274e62fcf0627780f61f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949546
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
(cherry picked from commit 565c54c270bd93ee30e8f8560d3d1691d128e762)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954341
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DCRYPTO_gcm_init hardcoded key length to 128 bit causing preventing
testing of 192 and 256 bit functionality for AES-GCM.
BUG=b:135623371
BRANCH=cr50
TEST=compile, specific test for issue as described in bug
Change-Id: I4fc41f6155661709115c57aa944c8976e17bffac
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1766098
Reviewed-by: Andrey Pronin <apronin@chromium.org>
(cherry picked from commit 24f7511e41c1f8140b19d69d9440a3ea6f91bd89)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954339
Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
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In npcx7, all I2C modules have separate 32-byte transmit FIFO and
32-byte receive FIFO buffers. In this CL, we add the FIFO mode support
to the I2C driver. This will help to reduce the firmware overhead (i.e.
the occurrence of I2C interrupt) during long I2C transactions by allowing
the EC to write/read more than one byte of data at one time to I2C
module and hence improve the I2C performance.
The FIFO mode is enabled by default on all npcx7 series chips.
BUG=none
BRANCH=none
TEST=No error for "make buildall"
TEST=Connect npcx7 EVB to the I2C slave emulator, do stress test:
1. iterate ~2000 times of single i2c_xfer_unlocked API call.
i.e.
i2c_xfer_unlocked(.., I2C_XFER_SINGLE)
2. iterate ~2000 times of multiple i2c_xfer_unlocked API calls:
i.e.
i2c_xfer_unlocked(.., I2C_XFER_START)
i2c_xfer_unlocked(.., 0)
.
.
i2c_xfer_unlocked(.., I2C_XFER_STOP)
3. Issue 6 I2C transactions by 6 tasks at the same time.
iterates ~2000 times.
TEST=with this CL; build and upload an image (with/without FIFO mode
enabled.) to yorp; no symptom occurs.
Change-Id: I387e8ef6e619acef670273f08ab4150e3d2b75f2
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827137
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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The CONFIG_HOSTCMD_X86 will get automatically defined
if either CONFIG_HOSTCMD_LPC or CONFIG_HOSTCMD_ESPI
are defined. So this definition is redundant in
config_chip.h
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: I3cb9b61d4b006becba5eb75e0dabe61bd9e3c999
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868134
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The module ID in alternate function setting for spi
master should be corrected as MODULE_SPI_MASTER.
BUG=none
BRANCH=none
TEST=make buildall -j
Change-Id: Ib52b09a5f1e0c496374d4ed2f3a222dab9af2eb0
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868133
Reviewed-by: Jett Rink <jettrink@chromium.org>
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GPIO, WUC and IRQ changes for chip it83201/it83202.
BRANCH=None
BUG=b:133460224
TEST=test GPIO group O, P, Q, R
1.Input: external input 3.3v, GPDR of corresponding pin is 1.
(GCR31, GCR32 select 1.8v, validate again for O and
P group)
2.Output: GPDR of corresponding pin set 1, measure 3.3v.
3.INT: GPIO_INT input trigger => WU INT (select high, low,
rising, falling, both edge trigger mode) => INT => CPU INT
4.Test power-up and down with this CL on ampton.
Change-Id: Ifae081c87b3dafcf3f7da84f637ceaf64a5ed536
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1675704
Reviewed-by: Jett Rink <jettrink@chromium.org>
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We have seen cases where after a cold EC reboot the pin is low until the
first CEC message is sent by AP (after which the bus is left in a well
defined state again)
This is a follow up to https://crrev.com/c/1346990 which initializes
the pull up in case not done by the RO FW.
BRANCH=none
BUG=b:144548408
TEST=CEC pin only goes low for ~40ms instead of 30s.
Signed-off-by: Felix Ekblom <felixe@chromium.org>
Change-Id: I3c98f8858f407279ad1bd086210969d69df2230b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928993
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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When we go through the suspend code path, we disabled RX
monitoring, and we have done that for a 4+ years. We have
not had a unit test for that ever. One is come that needs this
BRANCH=none
BUG=b:144369187
TEST=See that disabling RX in set_state no longer causes
assertion failures in tests that it shouldn't.
Change-Id: Iab4b44d3f5fdd1fe8657b23ac59df247a384ee32
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925667
Tested-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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The new RO has a new dev key, modify the dev manifest to match the new
RO expectations.
BUG=b:74100307
BRANCH=cr50, cr50-mp
TEST=built a node locked image for ro 0.0.11 and observed it boot and
run
Change-Id: I3ce9ca8d23be6b2d959d4457ea6d08afa05376ac
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1866173
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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Counter implementation has been moved to the AP, no need to keep space
for it in the flash.
BUG=b:65253310
BRANCH=cr50, cr50-mp
TEST=generated image uses 2048 bytes less than before this patch.
Change-Id: I8225e9923932ce06ca0a4333c06508cf7d7c70d8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1753677
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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HMAC DRBG is used for U2F key generation, and as such is subject
for ACVP tests. Expose DRBG Init, Generate and Seed commands for
automated testing with externally provided test vectors.
BUG=b:138578319
BRANCH=cr50
TEST=make CRYPTO_TEST=1 BOARD=cr50 -j && test/tpm_test/tpmtest.py
Change-Id: I50a6750864d3cd9a304a9b8a8524ef29cec04410
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1912662
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
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NIST 800-90B Entropy assesment tests requires 1M of 8-bit samples for
statistical tests. While it's possible to use TPM2_GetRandom command
to get entropy on cr50 (there is no software postprocessing), this
command is not available when compiled with CRYPTO_TEST=1 due to lack
of space in firmware. Adding vendor command which is available with
CRYPTO_TEST=1 to get raw entropy from TRNG. Added support script
to save entropy in file for further analysis. Since downloading
entropy takes a long time, new option'-t' added to tpmtest.py
which only invokes download of TRNG samples
BUG=b:138577834
BRANCH=cr50
TEST=make BOARD=cr50 CRYPTO_TEST=1 && test/tpm_test/tpmtest.py -t
To run NIST tests: nist_entropy.sh
Change-Id: I237a4581332a6e2c0332fe6ecf40731ab0be3355
Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919640
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
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With the addition of external i2c keyboard controllers, chips that don't
necessarly have gpios going to a keyboard can now still have a TASK_KEYSCAN.
Therefore it's wrong to assume we want the chip/*/keyboard_raw code included.
There was no easy way to make an ways on option (eg: CONFIG_KEYBOARD_RAW)
that could get #undefd in strategic places. The place that would always
define it would be in include/config.h but I don't believe that executes
before the build.mk rules.
BUG=b:135895590
TEST=Other boards with keyboards still happy.
TEST=No compile errors (regarding missing keyboard GPIOS) when declaring
TASK_KEYSCAN on a fresh stm32 board.
BRANCH=master
Change-Id: I061812a6941a11784950280648912edd5844bd79
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693862
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Let's make sure any change to files used explicitly in Cr50 are
approved by relevant persons.
BRANCH=none
BUG=none
TEST=none
Change-Id: If6affd837063311e3215e7596a3a424dc56c7603
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919649
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
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STM32F412xE has 512 KB flash
STM32F412xG has 1 MB flash
https://www.st.com/resource/en/datasheet/stm32f412cg.pdf
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I260659a1de62f3e79f427dd38ca831b4cabed448
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902463
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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During my bug hunt I had to remove the static attribute. While that
wasn't part of the fix, it slipped through.
Also, Daisuke pointed out that the standard idiom in the EC codebase is
__aligned instead of using the full __attribute__ statement, so switch
over.
BUG=none
TEST=sweetberry gcc8 build still runs
Change-Id: I106a8a2df3d6b56bfaba9819228ea7913029f707
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1905767
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
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Some boards have CONFIG_USB_PD_PORT_MAX_COUNT defined as 3. Fix the
concerned build assert.
BUG=None
BRANCH=None
TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and
garg(2A + 1C + 1HDMI config).
Change-Id: I4dc949b69dbb3986acc5aa0444c6056268f815f7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898686
Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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