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* pit: Drop EC clock speed to 1 MHz MSI when AP is in S3/S5Randall Spangler2013-06-262-80/+153
| | | | | | | | | | | | | | | | | | Automatically drop the clock speed to 1 MHz MSI, then disable HSI and move to lower-power flash mode. This cuts power from 2400uA to 150uA. Note that at 1 MHz, we drop received characters on the UART if you type too fast (or copy/paste, or use arrow keys). Clock speed can be manually overridden back to 16 MHz via 'clock hsi'. BUG=chrome-os-partner:20414 BRANCH=none TEST=with AP on, 'clock' reports 16 MHz. with AP off, 'clock' reports 1 MHz. Change-Id: I070c80db0aa5f3a98a7bad6050890bcc2fe008d6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59832
* pit: Support changing EC clock frequencyRandall Spangler2013-06-259-68/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modules which care about system clock frequency now hook HOOK_FREQ_CHANGE. - hwtimer - i2c - uart (which is now also smart enough to use x8 oversampling instead of x16 when the system clock is too slow to support x16) Added 'clock' debug command to set system clock frequency. STM32F platforms don't change clock frequency; on those platforms, clock_get_freq() simply returns CPU_CLOCK, so behavior of those platforms is unchanged. BUG=chrome-os-partner:20414 BRANCH=none TEST=from EC console: - reboot ap-off -> to make sure AP is off during testing - clock msi2 -> reports 2MHz clock - battery -> reports battery info - clock msi1 -> reports 1MHz clock - battery -> reports battery info - clock hsi -> reports 16MHz clock - battery -> reports battery info - power on -> AP powers on and host commands succeed Change-Id: Ib8276bf124727e4fb502297ca8b3d6d4b6170241 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59645
* pit: Fix watchdog help for STM32LRandall Spangler2013-06-241-31/+72
| | | | | | | | | | | | | | | | | Clean up timer initialization code to be more general, so that we can use timer 9 for the LSB on STM32L. Then use timer 4 for the watchdog helper. BUG=chrome-os-partner:18781 BRANCH=none TEST=From EC console: timerinfo -> current time still counts up properly waitms 2000 -> prints watchdog info before rebooting Change-Id: Ib0ba496b0eadb93756dcd1841857546910baf2a9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59612 Reviewed-by: Simon Glass <sjg@chromium.org>
* pit: Disable SPI output when AP is suspendedRandall Spangler2013-06-201-0/+2
| | | | | | | | | | | | | | | This fixes the problem where the EC consumes too much power during suspend. BUG=chrome-os-partner:20223 BRANCH=none TEST=from root shell, 'powerd_suspend'. 1.8V_MICOM should not go up. after resume, 'ectool hello' should still work. Change-Id: I93b781e96bea633419e923a83f1f6d7300ae8c54 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/59474 Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Refactor host command interface to support version 3 packetsRandall Spangler2013-06-202-7/+146
| | | | | | | | | | | | | | | | | | | | | | | | | This will fix EC flash commands on pit, once the host side (u-boot and cros_ec driver) are upgraded to match. This change is backwards-compatible the EC still supports the existing version 2 protocols for talking to existing AP/kernel/ectool. Once the AP-side supports version 3 for SPI (and existing systems are upgraded), we will remove older SPI support since we haven't shipped a product which uses SPI. BUG=chrome-os-partner:20257 BRANCH=none TEST=disable cros_ec driver support in ectool; 'ectool hello' works on link And with an old ectool which predates this CL, 'ectool hello' also works. On pit, from u-boot prompt, 'crosec test' and 'crosec version' work, and keyboard works. Change-Id: I01f193e316e9aa442fe50d632dc8a4681723e282 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58908 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Queue: Doug Anderson <dianders@chromium.org>
* Falco WP is active low, not active highBill Richardson2013-06-181-0/+4
| | | | | | | | | | | | | | | | | | | Read the value of the WP GPIO correctly. BUG=chrome-os-partner:20091 BRANCH=none TEST=manual On the EC console, run gpioget WP_L Short the WP pin, run it again. You should see it change. Change-Id: Id85c1d69c88ea3df4e529e844aa2455643f1a41b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58948 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Move i2c_old_response flag to i2c interface moduleRandall Spangler2013-06-141-3/+4
| | | | | | | | | | | | | | It's not used by the host command module or handlers, so shouldn't be exposed to them. BUG=chrome-os-partner:20185 BRANCH=none TEST='ectool hello' still works Change-Id: I0122bd9ef33e71afab7e5cc035fb3b9d220334c6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58632 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Move lpc-specific flags out of host command argsRandall Spangler2013-06-141-4/+5
| | | | | | | | | | | | | | | The flags are specific to the LPC interface and not used by the host command module, so shouldn't be present at that level. BUG=chrome-os-partner:20185 BRANCH=none TEST='ectool hello' still works Change-Id: I6b2c3208fc398ea40d9e7cc7bf5ec206b3e317d8 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58631 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* Rename GPIO_HI_Z macros to more descriptive GPIO_ODR_HIGH/LOWBill Richardson2013-06-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | GPIO_HI_Z was a bit misleading (it's high impedance by default, but it's actually an output not an input), but when we added GPIO_HI_Z_OPEN to mean "open-drain output, pulled low by default", it got too confusing. This renames those macros to: #define GPIO_ODR_HIGH (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_HIGH) #define GPIO_ODR_LOW (GPIO_OUTPUT | GPIO_OPEN_DRAIN | GPIO_LOW) BUG=chrome-os-partner:18788 BRANCH=none TEST=none No functional change, just renaming some macros. If it compiles, it should be unchanged in behavior. Change-Id: Ic84d7be8531f2b240a8eca4f6cfe5291ebd2d5ef Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58596 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* stm32: add hibernate support using stm32f100 standby modeVincent Palatin2013-06-112-14/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the EC hibernate mode by using the stm32f100 standby low power mode. As we cannot de-activate the watchdog during long hibernation, the following workaround is implemented: we are woken-up once by the watchdog and go back to hibernate if we detect that condition. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=spring BUG=chrome-os-partner:19595 TEST=on Spring with rework on the EC wake-up pin, type "hibernate 10" and see the EC console going blank for 10s, then booting with reset cause equals to "hibernate". Press Alt+VolUp+H, then wake-up the system by pressing power key. Change-Id: I28150e69817ae80314f52977ec6b62750017c2c4 Reviewed-on: https://gerrit.chromium.org/gerrit/58086 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Console input support for emulatorVic Yang2013-06-101-3/+57
| | | | | | | | | | | | | | | This creates a separate thread that keeps reading characters from stdin and feed to UART process. BUG=chrome-os-partner:19235 TEST=Start up a emulator and type 'help'. See command list. TEST=Pass all tests for 300 times. BRANCH=None Change-Id: I190c1d939b0b4ad0f8f0517d8d7b06f2f3df3832 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57866 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Define watchdog_reload() to nothing if not CONFIG_WATCHDOGRandall Spangler2013-06-104-19/+14
| | | | | | | | | | | | | | | | | | | Currently, we need to have #ifdefs everywhere watchdog_reload() is called. With this fix we don't. Also don't bother including unused hardware timer watchdog code if the watchdog isn't defined. No change when CONFIG_WATCHDOG is defined (which it is for all normal builds). BUG=chrome-os-partner:20056 BRANCH=none TEST=build all platforms with CONFIG_WATCHDOG commented out in config.h Change-Id: Id3ce33af1a497eda127a4892e13651d9d2534d92 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58094 Reviewed-by: Simon Glass <sjg@chromium.org>
* Enable ADC charger current monitor for SlippyBill Richardson2013-06-071-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IOUT pin of the smart battery charger can be used to monitor the AC adapter current (default) or the battery charging current. BUG=none BRANCH=none TEST=manual Discharge the battery a bit, and connect to the EC console. With the AC power plugged in, the "battery" command should show charging status, including current. The "adc" command will display the A-D converters, including the current measurement. For example: > battery Temp: 0x0b88 = 295.2 K (22.1 C) Manuf: SMP-COS20 Device: OC2 Chem: LION Serial: 0x0005 V: 0x4130 = 16688 mV V-desired: 0x41a0 = 16800 mV V-design: 0x39d0 = 14800 mV I: 0x008e = 142 mA(CHG) I-desired: 0x0080 = 128 mA Mode: 0x6001 Charge: 98 % Abs: 94 % Remaining: 1871 mAh Cap-full: 1923 mAh Design: 2000 mAh Time-full: 0h:23 Empty: 0h:0 > > adc ADC channel "ECTemp" = 317 ADC channel "ChargerCurrent" = 455 > That current is significantly higher than the "I:" reported by the "battery" command. But look at the charger options: > sbc 0x12 0x7904 (30980) > Bit 5 controls the IOUT Selection. When clear, it monitors the current from the AC adapter. Set bit 5 to monitor the current provided to the battery: > sbc 0x12 0x7924 > adc ADC channel "ECTemp" = 318 ADC channel "ChargerCurrent" = 128 > That matches what the smart battery sees. Change-Id: I2fe351304421dfb22d83ef13d416aa44c9f56e8a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57940 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix broken ADC gpio configuration for lm4Bill Richardson2013-06-071-4/+5
| | | | | | | | | | | | | | | | | The ADC pins were being misconfigured for quite a while now. Let's fix 'em. BUG=none BRANCH=link TEST=none The effect was that the adc values that measure GPIO pins were less accurate. Since no one noticed, there's probably not much that can be done to test it. Change-Id: I9def4eb95c89f72e5df0721e6153c8caa3ef8e2a Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57939 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Change i2c port configs to make BDS the special case, not Link.Bill Richardson2013-06-061-12/+11
| | | | | | | | | | | | | This matches our reference design for the EC's i2c GPIOs. BUG=none BRANCH=none TEST=none Change-Id: I8320b6234e2db8d645d0c4d4e982e3817da9f5e7 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57809 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Send STOP to clear bus when I2C encounters an error.Bill Richardson2013-06-061-2/+7
| | | | | | | | | | | | | | | | | Reading from a nonexistant/nonresponsive smart battery fails (as it should). But then it leaves the i2c clock line low, so that subsequent i2cscan commands fail too. This change just sends a STOP to clear the bus when an i2c error occurs. BUG=chromium:247037 BRANCH=none TEST=none Change-Id: I599bed7149ed3dd3748f1a939c2ea8fdf65e3d72 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57808 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Pit stays on HSI instead of using PLL with the same 16MHz frequency.Randall Spangler2013-06-051-4/+11
| | | | | | | | | | | | | | | Leaving the PLL turned off saves about 0.5 mW (and also presumably speeds up boot a tiny amount, since we don't need to wait for the PLL to lock). BUG=chrome-os-partner:19951 BRANCH=none TEST=system boots normally. power consumption on P1.8V_MICOM rail is lower. Change-Id: I93dc1efabbf6c6b0b5a43ffebe1068d18c689bef Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57645 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* haswell: fix driving of WAKE# pin on power button pressAaron Durbin2013-06-041-5/+4
| | | | | | | | | | | | | | | | | | | | | | The WAKE# pin was being driven low when the power button was pressed and no other events were occuring. This causes a PCIE wake event to be observed on the host. This is incorrect. Therefore only assert the WAKE# pin when any other event but the power button has occured. The implementation introduces a board-specific callback, board_process_wake_events(), which handles the specific logic for the wake events. BUG=chrome-os-partner:19810 BRANCH=None TEST=Manual. Both power button wakeup and lid events were tested. The presence of PCIE Wake no longer exists for S5->S0 transitions. Change-Id: If1311ccc36629b04d2d9e021c3e103e379836a3a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56970 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Enable flash unit test on emulatorVic Yang2013-06-036-4/+157
| | | | | | | | | | | BUG=chrome-os-partner:19236 TEST=Pass all tests BRANCH=None Change-Id: I09276292499b94b2d4810830de51e4c63a9b7342 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56704 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Clean up flash section defines and increase lm4 image sizeRandall Spangler2013-06-036-81/+79
| | | | | | | | | | | | | | | | | | | | | | | The firmware defines had two almost-identical sets. Coalesce into one consistent set. Link had 256 KB flash, but only allowed 2 80KB images. Future LM4-based platforms (slippy/peppy/falco/etc) will now use the entire flash, with RO=124KB, pstate=4KB, RW=128KB. This matches what the STM32 platforms do, where pstate is contiguous with the RO firmware. No functional change to STM32-based platforms. BUG=chrome-os-partner:19176 BRANCH=none TEST=build all platforms and dump_fmap ec.bin. - stm32-based platforms should report RO=61440@0, RW=65536@0x10000 - link should report RO=81920@0, RW=81920@0x14000 - slippy should report RO=129024@0, RW=131072@0x20000 Change-Id: I20b1d95c16250d9a5d228ead06eef03d96548823 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56655
* Add wireless switch control for WWANDuncan Laurie2013-06-031-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Haswell devices have EC control of the WWAN power rail. Expose a new wireless switch enable flag for this under the existing wirless enable command. This change also abstracts the wireless enable function to call a per-board handler so the different boards can do the right thing based on their GPIO setup. The haswell boards will switch WLAN radio and WWAN power rails based on the switch inputs. These boards do not have EC control of bluetooth radio/rail power. WLAN (power and radio) still defaults to enabled. Disabling with ectool will turn off the radio but keep the power enabled in order to prevent the PCIe device from disappearing. WWAN (power) still defaults to disabled. Disabling with ectool will turn off the power rail. BUG=chrome-os-partner:19871 BRANCH=none TEST=manual: boot on slippy DEFAULT: > ectool gpioget pp3300_wlan_en GPIO pp3300_wlan_en = 1 > ectool gpioget wlan_off_l GPIO wlan_off_l = 1 > ectool gpioget pp3300_lte_en GPIO pp3300_lte_en = 0 ENABLE WWAN: > ectool wireless 0x7 Success. > ectool gpioget pp3300_lte_en GPIO pp3300_lte_en = 1 DISABLE WLAN (radio): > ectool wireless 0x7 Success. > ectool gpioget pp3300_wlan_en GPIO pp3300_wlan_en = 1 > ectool gpioget wlan_off_l GPIO wlan_off_l = 0 Change-Id: I6f760b8cf5ab47d8f7f0dd8cd4d3e6563464043e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57215 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* slippy/falco: Add back in flash and hiberantion setup codeDuncan Laurie2013-06-032-9/+0
| | | | | | | | | | | | | | | | | | | | These were tested to make sure they are not responsible for bricking boards. The flash code is necessary for software sync, and it is essential to be able to update boards without servo. The hibernate setup code was breaking jumping between images and the passing of data between the images -- needed for SW SYNC but also needed for things like "reboot ap-off". BUG=chrome-os-partner:19366 BRANCH=none TEST=manual: emerge-slippy chromeos-ec, flash+boot, update again via SW Sync Change-Id: Ib1363b353f18b21e0cad3209783e1e0b4ff24e86 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56820
* Fix a bug in emulator persistent storageVic Yang2013-05-281-1/+3
| | | | | | | | | | | | | The path string is not terminated properly, causing occasional crashes. BUG=chrome-os-partner:19235 TEST=Dump the path and check it's correct. BRANCH=None Change-Id: I9ccbd565ce68ffdad98f2dd90ecf19edf9805ec0 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56700 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* More low-level flash interface cleanupRandall Spangler2013-05-243-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting at-boot protection always used the same start/range (RO+PSTATE), so no point in passing that to the physical layer as params. flash_dataptr() should take a pointer to const data. No functional changes; just rearranging code. BUG=chrome-os-partner:15613 BRANCH=none TEST=build pit, link, spring - flashinfo -> (no flags) - enable WP (via screw or dut-control) - flashinfo -> wp_gpio_asserted - flashwp enable - flashinfo -> wp_gpio_asserted ro_at_boot - flashwp now - flashinfo -> wp_gpio_asserted ro_at_boot all_now (and possibly ro_now) - flashwp disable -> fails - flashinfo -> wp_gpio_asserted ro_at_boot all_now - reboot ap-off - flashinfo -> wp_gpio_asserted ro_at_boot ro_now - disable WP (via screw or dut-control) - reboot - flashinfo -> ro_at_boot - flashwp disable - flashinfo -> (no flags) Change-Id: Ifd6553dc907fa6fafce81b56af0c648ac6d6bee1 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56628
* Move flash_get_protect() and flash_set_protect() to flash_common.cRandall Spangler2013-05-243-280/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Much more flash code is now common between platforms, for more consistent behavior and easier testing. Also change STM32L to use pstate, the same way LM4 and STM32F do. BUG=chrome-os-partner:15613 BRANCH=none TEST=build pit, link, spring; do - flashinfo -> (no flags) - enable WP (via screw or dut-control) - flashinfo -> wp_gpio_asserted - flashwp enable - flashinfo -> wp_gpio_asserted ro_at_boot - flashwp now - flashinfo -> wp_gpio_asserted ro_at_boot all_now (and possibly ro_now) - flashwp disable -> fails - flashinfo -> wp_gpio_asserted ro_at_boot all_now - reboot ap-off - flashinfo -> wp_gpio_asserted ro_at_boot ro_now - disable WP (via screw or dut-control) - reboot - flashinfo -> ro_at_boot - flashwp disable - flashinfo -> (no flags) Change-Id: Iccd098786454ad9b72b4e5f9f312d86819a0c8eb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56109
* Remove 64-byte workaround from STM32L flash writingRandall Spangler2013-05-242-54/+35
| | | | | | | | | | | | | | | | | | | | | This was left over from ancient code where host commands only had a 64-byte payload, and page writes need to happen in 128-byte increments. This is no longer an issue with SPI host interface. Also added capability for word writes, since that'll be necessary for writing pstate (in the next CL). BUG=chrome-os-partner:9526 BRANCH=none TEST=hack flashwrite command in flash_common.c to allow write size = 4 bytes flasherase 0x1fc00 0x400 flashwrite 0x1fc00 0x100 -> success; uses fast path flashwrite 0x1fd00 4 -> success; uses word-write path Change-Id: I61434d8f714ea46deb65cadd82c45a61ad0ce68b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56627 Reviewed-by: Simon Glass <sjg@chromium.org>
* Create board configuration for peppy bringupDave Parker2013-05-231-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This change copies the slippy board configuration as a starting point for peppy. This change is essentially the same as https://gerrit.chromium.org/gerrit/55820 BUG=chrome-os-partner:19640 BRANCH=none TEST=manual Tested on slippy as there are no peppy-specific changes yet. cros_workon --board peppy start chromeos-ec emerge-peppy chromeos-ec ~/trunk/src/platform/ec/util/flash_ec --board peppy Signed-off-by: Dave Parker <dparker@chromium.org> Change-Id: I4c5f7a77fa55a6364effe838f7a656d56bfad9fb Reviewed-on: https://gerrit.chromium.org/gerrit/56332 Reviewed-by: Olof Johansson <olofj@chromium.org> Commit-Queue: Dave Parker <dparker@chromium.org> Tested-by: Dave Parker <dparker@chromium.org>
* Move write protect GPIO handling to flash moduleRandall Spangler2013-05-234-15/+30
| | | | | | | | | | | | | | | | | Write protect signal naming is now consistent across boards. New CONFIG_WP_ACTIVE_HIGH is present on systems where the write protect signal is active-high (e.g. Link). This will be used in the next CL, which moves flash_get_protect() to flash_common.c BUG=chrome-os-partner:15613 BRANCH=none TEST=flashinfo properly reports WP signal status Change-Id: I502ab033c3eb36661cc3ee97320874b3fbf6fc0d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56087 Reviewed-by: Vic Yang <victoryang@chromium.org>
* Move flash persistent state to flash_commonRandall Spangler2013-05-235-264/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Persistent state is needed by all platforms to hold the protect-ro-at-boot flag. STM32F100 and LM4 implementations were near-identical, and are now common code (with one #ifdef to handle the single place where they weren't). STM32L doesn't use pstate yet, but it'll need to. I can't simply store the protect-ro-at-boot flag inside the WRP registers themselves because they're still writable in EC-RW. The change to STM32L to use pstate is coming next. BUG=chrome-os-partner:15613 BRANCH=none TEST=build pit, link, spring; on link and spring, do - flashinfo -> (no flags) - enable WP (via screw or dut-control) - flashinfo -> wp_gpio_asserted - flashwp enable - flashinfo -> wp_gpio_asserted ro_at_boot - flashwp now - flashinfo -> wp_gpio_asserted ro_at_boot all_now (and possibly ro_now) - flashwp disable -> fails - flashinfo -> wp_gpio_asserted ro_at_boot all_now - reboot ap-off - flashinfo -> wp_gpio_asserted ro_at_boot ro_now - disable WP (via screw or dut-control) - reboot - flashinfo -> ro_at_boot - flashwp disable - flashinfo -> (no flags) (Note that on Spring you'll need to 'forceen on' before enabling WP, or the console will be disabled once you enable ro_at_boot and reboot.) Change-Id: I415388b98ec8bf1d149803aaaa7fe8c7f3076c36 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56064
* Clean up option byte register definitions for STM32LRandall Spangler2013-05-232-13/+13
| | | | | | | | | | | | No functional changes, just renaming and defining a few additional regs. BUG=chrome-os-partner:15613 BRANCH=none TEST=build pit Change-Id: I67b2a96608431ffc418e6d4c81009d497f34568b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55813
* Support flash write protect on STM32LRandall Spangler2013-05-223-96/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for write protecting the RO code at boot, and the entire flash on demand. Implementation if WP# is not asserted is currently a little different than STM32F and LM4; RO is still protected at boot if ro_at_boot, but can be unprotected and the change will commit on the next reboot. This saves the bank of flash which we use for pstate on LM4 and STM32F. I think I can use one of the unused option bits (WRP2 bit 0) to hold the RO-at-boot flag, in which case I can more closely match the behavior of the other chips, but I'd like to do that (or give up and implement pstate) in a separate CL so it's clearer what I'm doing. BUG=chrome-os-partner:15613 BRANCH=none TEST=manual - flashinfo -> (no flags) - enable WP (via screw or dut-control) - flashinfo -> wp_gpio_asserted - flashwp enable - flashinfo -> wp_gpio_asserted ro_at_boot - flashwp now - flashinfo -> wp_gpio_asserted ro_at_boot all_now - flashwp disable -> fails - flashinfo -> wp_gpio_asserted ro_at_boot all_now - flasherase 0x1fc00 0x400 -> fails - reboot - flashinfo -> wp_gpio_asserted ro_at_boot ro_now - flasherase 0xfc00 0x400 -> fails - flasherase 0x1fc00 0x400 -> succeeds - disable WP (via screw or dut-control) - reboot - flashinfo -> ro_at_boot ro_now - flashwp disable - flashinfo -> ro_now - reboot - flashinfo -> (no flags) - flasherase 0xfc00 0x400 -> succeeds - flasherase 0x1fc00 0x400 -> succeeds Change-Id: Id1b6b099a44a1985a5ab9387feb882a8f26e3aa1 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55594
* Create board configuration for falco bringupBill Richardson2013-05-204-9/+10
| | | | | | | | | | | | | | | | | | | | | | | | This change just copies slippy and tweaks a few things that were slippy-specific instead of not-link-specific (there are still bugs open for those things). BUG=chrome-os-partner:18788 BRANCH=none TEST=manual Since there are no Falco-specific changes yet (just slippy with another name), I can try it on Slippy: cros_workon --board falco start chromeos-ec emerge-falco chromeos-ec ~/trunk/src/platform/ec/util/flash_ec --board falco I also built and tested Link EC, to make sure nothing broke there either. Change-Id: I9b3682032bd51adab4450520dfe52e3036750ef9 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55820 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Support write protect GPIO on pitRandall Spangler2013-05-171-8/+4
| | | | | | | | | | | | | | | | Daisy doesn't have a write protect signal, so emulate it as a fake signal which is always low; this maintains the current behavior on daisy. BUG=chrome-os-partner:15613 BRANCH=none TEST=flashinfo shows gpio not asserted then short across the WP screw and flashinfo shows it asserted Change-Id: I329424efe1c3b065976e17395e2bf9588cdce88c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51500 Reviewed-by: Vic Yang <victoryang@chromium.org>
* Fix detecting inconsistent flash stateRandall Spangler2013-05-172-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the last bank of flash in a region was protected and the rest of the region was unprotected, flash_get_protect() shoud return the INCONSISTENT flag, but this wasn't being properly detected. Port the existing fix from STM32F. BUG=chrome-os-partner:19529 BRANCH=none (not likely worth porting to link) TEST=protect just the last bank of RW firmware, then flashinfo > flashinfo Physical: 128 KB Usable: 128 KB Write: 64 B Erase: 256 B Protect: 4096 B Flags: all_now INCONSISTENT Protected now: ........ ........ ........ .......Y Should have the inconsistent flag set. Change-Id: I407737cef42748da6b3ec40d84968c76ee07972c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51498 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Set SPI lines to inputs when AP is offRandall Spangler2013-05-162-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When AP is off, turn off pullup on NSS, and set MISO to an input so the SPI module won't drive it high if the last sent bit was a 1. This reduces leakage when the AP is off. This patch also fixes a bug where gpio_set_alternate_function() set the wrong pins to normal-mode when func=-1; that didn't hit anything else because that functionality wasn't used on STM32 until now. BUG=chrome-os-partner:19304 BRANCH=none TEST=boot pit On EC console, with AP on, 'rw 0x40020000' returns read 0x40020000 = 0x6569aa20 <- must have 0x____aa__ Then 'apshutdown' and 'rw 0x40020000' returns read 0x40020000 = 0x65690020 <- must have 0x____00__ The 'power on' and AP turns back on. At u-boot prompt, 'sspi 2:0 256 9f00000000' returns FDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFDFEEC010001 (some number of 0xFD's followed by FEEC...) This shows SPI functionality is restored when AP is powered back on, and not just at init time. Change-Id: Ia3cd3e0bc222dc663d635509918fa3d383fd7971 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51182 Reviewed-by: Simon Glass <sjg@chromium.org>
* lm4: break out board-specific fan/tach pin configAaron Durbin2013-05-161-10/+0
| | | | | | | | | | | | | | | | | The current lm4 pwm module was using board-specific pins during this configuration. Move the implementation of configure_fan_gpios() to the board-specific files so that the pin configuration policy isn't a part of the common infrastructure. BUG=chrome-os-partner:19504 BRANCH=none TEST=successfully booted slippy with backlight turning on in OS. Change-Id: I325f1ac4639b4a78d8b860df7a8b688ca385b71b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51471 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Add console command to force enable consoleVic Yang2013-05-152-48/+17
| | | | | | | | | | | | | | | | | | | | | | When system is locked, the console is disabled. However, we need console for debugging and testing. This CL uses a bit from back-up register to indicate if the console should always be enabled. (This bit is currently used by fake WP, which is removed in this CL.) With this, we can set this bit with console command 'forceen 1' to ensure console is never disabled. To prevent device shipped in this state, the chip name is postfixed with '-unsafe' so that the device is not able to pass HWID check. BUG=chrome-os-partner:19293 TEST=Manual BRANCH=spring Change-Id: I88556e973ca542c1bdc27ba64988718291e01a26 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51086 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* LM4: Support configurable host UART interfaceDuncan Laurie2013-05-131-56/+62
| | | | | | | | | | | | | | | | | | | | | | | Slippy uses UART2 instead of UART1 and so the EC needs to be able to tolerate having the host use a different interface. There are of course many ways to accomplish that but this approach adds two config variables to specify the host uart and the host uart irq. The UART port setup is split out to allow them to be configured separately rather than needing to be adjacent in a for loop. The interrupt functions were renamed (to ec and host) in order to indicate which interface they are responsible for. BUG=chrome-os-partner:19356 BRANCH=none TEST=boot slippy and see host serial output Change-Id: I1913ff3d650f329224c9654eee7bb7412fae5402 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50837
* Slippy: Changes needed to boot EC without bricking.Bill Richardson2013-05-105-2/+23
| | | | | | | | | | | | | | | | This commits the hacks made during board bringup. Bugs can be filed and fixed based on this starting point. BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Try it and see. Change-Id: Ia663eaf9a357633873b1b5d5cc6dbdda63513082 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50875 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* i2c: Allow for i2c "ping" that's a write of 0 bytesDoug Anderson2013-05-081-1/+3
| | | | | | | | | | | | | | | | | | | The i2cdetect command on Linux likes to probe by doing a write of 0 bytes. Rather than always returning success because there was nothing to write, let's actually implement this command. At the moment we only implement for the stm32l. We also don't try to implement the "read of 0" bytes since I don't think anyone uses that. BUG=chrome-os-partner:18778 BRANCH=none TEST=i2cdetect -y -a 20 now detects the right devices Change-Id: Ia159ce9b8c957d5cd11f187f1a179ca5967bf96f Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50009 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* i2c: stm32l: Fix i2c reads of sizes other than 1Doug Anderson2013-05-082-11/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | The STM32L manual has a whole section on i2c master reads and describes the correct method for receiving exactly 2 bytes and more than 2 bytes. We weren't following those instructions and thus larger transfers weren't working. BUG=chrome-os-partner:19265 BRANCH=none TEST=i2cxfer r16 0x90 0 ...doesn't fail TEST=i2cxfer r 0x90 0 ...doesn't fail TEST=Use pydevi2c and test some commands: >>> tps = I2CDevice(20, 0x48) >>> [hex(x) for x in tps.Get(0, 20)] ['0x1e', '0x0', '0x3e', '0x0', '0x12', '0x20', '0x4b', '0xbf', '0xff', '0xff', '0x20', '0x12', '0x1e', '0x1e', '0x1e', '0x1f', '0x1f', '0x1f', '0x1f', '0x1f'] Change-Id: Ifaab6d8b700e099bcd9c374c70fca0983858ed3f Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50229 Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* Add lid switch test and enable kb_mkbp testVic Yang2013-05-081-0/+5
| | | | | | | | | | | BUG=chrome-os-partner:19236 TEST=Pass both tests BRANCH=None CQ-DEPEND=CL:50467 Change-Id: I59cc407c2d1bf7f549ff9c46226cf7fa60fe7157 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50466
* Use uintptr_t when converting integer from/to pointerVic Yang2013-05-071-2/+2
| | | | | | | | | | | | | | | Perviously we use uint32_t for this, but this doesn't compile for 64-bit environment (and likely doesn't for 16-bit either.) Use uintptr_t so that we don't get size mismatch errors. BUG=chrome-os-partner:19257 TEST=Run host emulated tests BRANCH=None Change-Id: I3cd66a745fa171c41a5f142514284ec106586acb Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50358 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f: Set ADC single read timeoutVic Yang2013-05-071-4/+13
| | | | | | | | | | | | | | | If an ADC read fails and EOC bit is somehow never set, we will be stuck in the read function holding mutex lock forever, which is really bad. Let's set a timeout for this. BUG=chrome-os-partner:18997 TEST=Boot Spring. Check ADC works. BRANCH=spring Change-Id: I19b108326f34f380497606fe92eabfaf0a778bb4 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50338 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* spi: Fix OOBE in bounds-checking the replyDoug Anderson2013-05-071-1/+1
| | | | | | | | | | | | | | | | | | | | | There was an off-by-one error in bounds checking the reply. You could trigger it with pydevi2c with: >>> tps = I2CDevice(20, 0x48, force=True) >>> tps.Get(0, 249) The EC would show: ASSERTION FAILURE 'msg_len < sizeof(out_msg)' in reply() at chip/stm32/spi.c:184 BUG=chrome-os-partner:18778 BRANCH=none TEST=Run the above commands and see no error. Change-Id: I9789405a9d70c5dc3fa237504fea8f46a139386c Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50254 Reviewed-by: Simon Glass <sjg@chromium.org>
* Fix and enable SPI for pitRandall Spangler2013-05-073-66/+47
| | | | | | | | | | | | | | | | | | | | | | | | | I've simplified the SPI module, since we only ever use SPI1 (and there were already a number of places which assumed this was true). Somewhere along the way I fixed a number of problems keeping the code from compiling and working on STM32L. The code isn't currently used anywhere else, but should still work there (that is, I don't think I broke it working on STM32F if you re-enable it on some STM32F platform). BUG=chrome-os-partner:19073 BRANCH=none TEST=from u-boot console, sspi 2:0 64 9f0000 u-boot prints: FDFDFDFDFDFDFDFD ec prints: [193.740912 HC 0x9f][193.741141 HC err 1] [sjg: gpio optimization back in for now] [dianders: add comment as rspangler requested; update SOBs] Change-Id: Ib9419403e4e44dadc1f17681e48401882cb49175 Signed-off-by: Randall Spangler <rspangler@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49684
* Add persistent storage for emulatorVic Yang2013-05-074-1/+89
| | | | | | | | | | | | | | This is needed for non-volatile register emulation. Also, this can be used to implement system jump or reset flags. BUG=chrome-os-partner:19235 TEST=Run utils test. Check persistent storage file exists. BRANCH=None Change-Id: I699f95718ef6f5de6c3bbb4e37619ee015fb6c4a Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50313 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Pthread-based emulator for unit testingstabilize-4100.38.BVic Yang2013-05-076-0/+293
| | | | | | | | | | | | | | This is the first version of pthread-based RTOS emulator. With this, we will be able to test high-level modules entirely on the host machine. BUG=chrome-os-partner:19325 TEST='make runtests' and see tests passing. BRANCH=None Change-Id: I1f5fcd76aa84bdb46c7d35c5e60ae5d92fd3a319 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49954 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add some ifdefs to distinguish between Link and SlippyBill Richardson2013-05-025-5/+20
| | | | | | | | | | | | | | | I'll still need to decide what to do differently for Slippy, but for now let's just identify the places where there will likely be a difference. BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Link still works. Change-Id: I950f0e5356ccf9838f2140d853122235f884e34f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49931
* Support power button on slippy, make it compile again.Bill Richardson2013-05-021-0/+2
| | | | | | | | | | BUG=chrome-os-partner:18825 BRANCH=slippy TEST=none Change-Id: If20ebaf8e718bc24d61a976026586445ccb6685e Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49914
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