| Commit message (Collapse) | Author | Age | Files | Lines |
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HC version v1 response has 132 bytes, but ISH response buffer is
smaller than this. We will get error as below:
localhost ~ # ectool version --name=cros_ish
EC result 14 (RESPONSE_TOO_BIG)
Hence increase ISH response buffer size to 260 bytes.
BUG=b:271502099
BRANCH=none
TEST=on Rex platform with ISH enabled, "ectool version --name=cros_ish"
will print firmware version, no error.
Change-Id: I81cbea19a2b4719b88b232bfea02803b0a244b89
Signed-off-by: Li Feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4302834
Reviewed-by: Yuval Peress <peress@google.com>
Reviewed-by: Tanu Malhotra <tanu.malhotra@intel.com>
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The USB_SPI_CONFIG() macro allowed a set of "run-time" flags to be given
by board.c. However, these flags have to be known at compile time, and
always are. They can more conveniently be given through a CONFIG_
define.
With the above, and a little tweak in hammer/board.h (mimicking what was
already done for I2C), then every invocation of the USB_SPI_CONFIG()
across the codebase is identical, setting the stage for moving the
declarations into usb_spi.c, and eliminating the macro altogether.
BUG=b:273601311
TEST=none
Change-Id: Id565338238a7c21f7e2c6c24b7c4e3d7648482f6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4368551
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Brian Nemec <bnemec@google.com>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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For some reason, all methods in usb_spi.c pass along pointers to config
and state, as if prepared to have multiple USB interfaces each
implementing their own instance of the SPI->USB bridge protocol. Doing
so would make little sense, as a single instance is already able to
manipulate multiple SPI busses.
This CL eliminates the pointer parameters, for a tiny performance
improvement, and code simplification.
BUG=b:273601311
TEST=none
Change-Id: Ifbfdb18b4a2ba656732e4eb143de9f678416067a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4352128
Reviewed-by: Brian Nemec <bnemec@google.com>
Tested-by: Jes Klinke <jbk@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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The pre-watchdog warning interrupt handler currently invokes
get_panic_data_write() to retrieve a pointer to panic data. This has a
side-effect of initializing the panic data with PANIC_MAGIC and a panic
data size without other pertient fields set. As a result, the EC reports
malformed panic to the AP causing an unparsable EC crash to be reported.
Revert the ITE watchdog warning interrupt usage of
get_panic_data_write() to using the global PANIC_DATA_PTR pointer to
panic data.
BRANCH=none
BUG=b:247100203
TEST=On drawcia, dead battery boot, invoke waitms 1100 (pre-wdt warning),
invoke ectool panicinfo to check for well-formed panic data
TEST=On drawcia, invoke crash watchdog, invoke ectool panicinfo to check
for well-formed panic data.
Change-Id: I5a75bec0efa79d00c358edc0645a0a0d39a879d2
Signed-off-by: Aaron Massey <aaronmassey@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4358752
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Enhance the interface to board-specific SPI driver such that it can take
flags for advanced serial flash chip protocols (dual/quad lanes, dummy
cycles, double transfer rate).
BUG=b:273601311
TEST=c2d2 can still flash (using single-lane)
Change-Id: Iee6a17077ea8c382c7d59bd404bf5d033bd9b517
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4336273
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
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This patch enables SHA256 accelerator for all boards using NPCX9.
Before:
[0.007394 hash start 0x00040000 0x0002f97c]
[0.291092 hash done e7faf382c6bd60c892cb4af...]
After:
[0.038571 hash start 0x00040000 0x0002f97c]
[0.095532 hash done e7faf382c6bd60c892cb4af...]
BUG=b:272132276
BRANCH=None
TEST=Agah
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I10660e423ee16b2a6bcb3dd147593b6c7e4cf952
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4348896
Reviewed-by: Jes Klinke <jbk@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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During my investigation into performance of SPI flashing with servo-like
devices, I stumbled upon an odd behavior. It seems that asynchronous
execution of write-only SPI transactions does not quite work on STM
chips.
For transactions that consist of writing a few bytes followed by reading
a block of data, the current spi_transaction_async() works well, in that
it first performs the write part, then waits for the DMA to finish,
before setting up the larger read part, and returning without waiting
for it to finish. Later, spi_transaction_flush() will call
spi_dma_wait() to know when the transfer has completed.
For write-only transactions, however, spi_transaction_async() blocks in
its "intermediate" spi_dma_wait(), before realizing that there is
nothing to read, meaning spi_transaction_async() in effect blocks until
the transaction is complete, and the subsequent spi_dma_wait() in
spi_transaction_flush() is superfluous.
I have found that with this very small change, spi_transaction_async()
will return soon after a write-only transaction has been initiated, and
spi_transaction_flush() will wait for its completion.
BUG=b:273601311
TEST=Flash using c2d2 and HyperDebug
Change-Id: I015f2870b1f0e561050b75618545dee6bcf04690
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4336269
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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The config from EC collides with the same config from Zephyr.
BUG=b:239712345
BRANCH=none
TEST=make runhosttests buildall
Change-Id: Ic6e63ea6dd9e745e82feb2af04b77069c2d78af1
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4295699
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Commit-Queue: Patryk Duda <patrykd@google.com>
Tested-by: Patryk Duda <patrykd@google.com>
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The ADC drivers for STM32L4 (and L5) seems to have significant flaws.
The chip has the ability to continuously perform ADC conversions
according to a set sequence of channels and bit depths. In addition to
that, the chip can perform a one-off "injected" sequence of up to four
channels, in response to a hardware or software trigger.
The driver uses only a software triggered "injected" sequence to convert
two pre-set channels.
The code of `adc_read_channel()` has some odd properties, though. On
first invocation, it sets up the injected sequence to consist of the two
configured ADC channels. Each invocation takes one particular ADC
channel number as input, but the code simply kicks of the sequence of
two channels to read, and then returns the relevant of the two,
discarding the other reading.
The has the needless limitation that it cannot be used with more than
two ADC channels.
Since it is permitted to modify the list of channels in the injected
sequence as long as no conversion is in progress, it would be more
straightforward, if each invocation of `adc_read_channel()` would
reconfigure the injected sequence to consist of a single channel, the
one requested. This CL makes that change.
BUG=b:269621551
TEST=Read and of a dozen ADC channels on HyperDebug
Change-Id: I62387979faf494cfefc3b6e7dd1d9a1954017ae6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265223
Tested-by: Jes Klinke <jbk@chromium.org>
Commit-Queue: Eric Yilun Lin <yllin@google.com>
Auto-Submit: Jes Klinke <jbk@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@google.com>
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The STM32L4/5 ADCs use three bits to configure the time to sample the
input voltage, that is the time during which an analog MUX conducts,
allowing the internal holding capacitor to settle. The enums declared
in adc_chip.h has eight usable values, plus an additional value called
DEFAULT.
It makes sense to have the DEFAULT be represented by a zero value, such
that if a board.c file does not mention the sample_time field in its
adc_t, then due to the C convention of data being zero-initialized, the
code can detect it and apply a sensible default.
However, the body of adc_configure() has no such logic, but takes the
raw enum value and attempts to stuff it into a 3-bit field, which will
be off by one, and overrun for the largest enum value of 8.
Also, I find the term "sample rate" misleading, as it implies a
continuous process. This sample time setting applies equally to one-off
injected conversions, as it refers to the duration of the sampling of
the input signal, before conversion begins, not a rate of conversions
happening.
BUG=b:269621551
TEST=Made measurements with the longest same time setting
Change-Id: Id8d297fcec883565dea1e09d6bbbfa1ab564778d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265222
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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In several cases, the L4 and L5 series can use the same driver, which is
different from other STM32Lx chips.
This CL introduce a warning at the top of such files, alerting readers
to the fact that they are also used by L5 despite this not being
apparent from the file name.
BUG=b:269621551
TEST=none
Change-Id: I6edff6c0aea57ea9679729db20a292d75b4b8df0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4264176
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
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The convention of the STM32_ADC1_ISR register is that writing a 1 to any
bit clears that one latched interrupt status bit. Existing code wrongly
uses |= on this register, effectively clearing every latched bit in the
register, not merely the intended one.
BUG=b:269621551
TEST=Observe ADC conversions on HyperDebug
Change-Id: Ia9fe3f6ca6f2f67614628b23bc7ba2e3a3caf058
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265221
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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The L5 family has basically the same ADC component as L4.
L5 does not have ADC3, but that happened to not be used by the
stm32l4.c, so the existing implementation can be used without
modification.
BUG=b:269621551
TEST=Observe ADC conversions on HyperDebug
Change-Id: I4ce279dca3ff23ae2a9d2f00c23399732eecf15f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4265220
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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Adapt dfu_bootmanager_main.c to compile without flash support.
BUG=b:192262089
TEST=make BOARD=hyperdebug
Change-Id: I9ceca733062b46ed7087ef7725bc1f6ac68c6b0a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4193071
Commit-Queue: Jes Klinke <jbk@chromium.org>
Reviewed-by: Brian Nemec <bnemec@google.com>
Tested-by: Jes Klinke <jbk@chromium.org>
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Looking at the code, it is apparent that the "pll" parameter to the
"clock" console command is valid whether STM32_HSE_CLOCK is defined or
not (though the effect may be slightly different).
This CL updates the documentation to list "pll" as a valid option also
when STM32_HSE_CLOCK is not defined.
BUG=none
TEST=make BOARD=hyperdebug
Change-Id: I7da89c15b44fbc3dad2a5fe129b0e361d7f50714
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4216263
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
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ARM Cortex documentation calls for an ISB instruction to be executed
immediately after modifying the stack pointer, see for instance:
https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/programmers-model/core-registers
It would seem that instruction prefetch will "anticipate" stack pointer
movements by counting the push and pop instructions, and that the
prefetch queue needs to be cleared if the stack pointer is manually
changed. Our particular code executes does not use the stack pointer,
but executes a register jump, which I assume will also clear the
prefetch queue. So in all likelihood, the barrier instructions is not
required here, but we could as well add it, as the documentation calls
for it.
BUG=none
TEST=make BOARD=hyperdebug, observe DFU upgrading still works
Change-Id: I2a0609670b3554a39057b429fc2e0cd1201d185c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4216262
Reviewed-by: Brian Nemec <bnemec@google.com>
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
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Remove the .isort.cfg from platform/ec and use the one from chromite
instead. This should be compatible with cros format.
BRANCH=None
BUG=b:267757300
TEST=Ran firmware_builder.py
Change-Id: Ice4955b6995bd1f9380e97f58e89efb7c1e8aeb1
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4221928
Auto-Submit: Jeremy Bettis <jbettis@chromium.org>
Tested-by: Jeremy Bettis <jbettis@chromium.org>
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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The STM32L5 series behaves the same as STM32L4 to a large degree, so
this CL adds code to enable RTC clock on L5 using the same register bits
as on L4.
The "backup registers" however, sit in a new "Tamper" component on L5,
and not in the RTC component as on L4. This CL adds register
declarations for the TAMP component.
Lastly, jumping to the ROM bootloader with C function pointer
call, as was done in jump_to_dfu(), does not work on the STM32L5 ROM
bootloader (at least not on my Nucleo-X552EZ board.) The flaw seems to
be that an ARM vector table contains a reset vector, and separately
contains an initial value for the stack register. The previous code
made no attempt at setting the stack point as the bootloader expected,
and depending on how the EC code (and the STM ROM bootloader) is
compiled, this may or may not work. This CL adds assembly code to set
the stack pointer to the value given in the ROM header, before
performing the jump.
BUG=b:192262089
TEST=Upgrade firmware on STM32L5 based Nucleo board using dfu-util
Change-Id: I2a871f0eaf9ea9f4c27c75ccb472cd4ff9616524
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4190164
Reviewed-by: Brian Nemec <bnemec@google.com>
Tested-by: Jes Klinke <jbk@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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Originally, I copied STM32L4 declarations for STM32L5, making
adjustments for base addresses, and other obvious differences. It turns
out that the external interrupt controller has som subtle changes to its
registers. Most notably the EXTICR registers (used for selection which
external pin is routed to which of the 16 edge detection "engines") have
been moved from the SYSCFG component into EXTI component.
BUG=b:192262089
TEST=Observe edge detection working on HyperDebug (based on STM32L5)
Change-Id: I4ad4f2559c60bef73a29812ebac1316cfa389a3e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4166670
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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The code in espi_msvw[12]_interrupt relies on undefined behavior today.
__builtin_ctz is specified as returning values in the range [0, 31], but
we are checking for 32.
This behavior may be unexpected compared to the CTZ/CLZ instruction on
ARM, which use the value 32 to indicate that there are no ones in the
provided input.
GCC 11+ optimizes the two loops below into infinite loops, as it can see
that the condition will never be met.
After this change, the disassembly of espi_mswv1_interrupt can be
confirmed to contain an exit behind a branch.
... // r4 is loaded with girq24_result and has bits successively cleared
1a: b90c cbnz r4, 20 <espi_mswv1_interrupt+0x20>
1c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
20: fa94 f5a4 rbit r5, r4
...
BUG=None
BRANCH=main
TEST=Examined the disassembly for espi_msvw[12]_interrupt; see above
Change-Id: I68a5c753233a17b6b0fb61a31f1eeccf78c00aba
Signed-off-by: Dustin L. Howett <dustin@howett.net>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4114450
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
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Existing code for extracting chip independent EC pin flags from stm32
registers suffered from a copy/paste error, meaning that it could never
recognize interrupt triggering on a falling edge.
BUG=none
TEST=make BOARD=hyperdebug
Change-Id: I4c752b092bfd3c6ea70192006a9453e0b81b0d9b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4166669
Tested-by: Jes Klinke <jbk@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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Fix checkpatch error:
> Prefer 'unsigned int' to bare use of 'unsigned'
BUG=b:262047616
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
BRANCH=none
Change-Id: Ibf82332a1e1ea0a0a03d3993336e24883e495e05
Signed-off-by: Andrea Grandi <agrandi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4126483
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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The coding of the enum ncl_status is not correctly defined in the SHA256
chip driver. This CL fixed it to meet the actual return code from the
SHA ROM API.
BRANCH=none
BUG=b:155771688
TEST=manually dump and check the return value from SHA ROM API.
Change-Id: Iee3ec5c7102ddc93f7afda6523c59393a5a0047a
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4113813
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Reviewed-by: Fabio Baltieri <fabiobaltieri@google.com>
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The STM32L5 series of chips have a SPI controller capable of using up to
eight data lines for fast transfers, primarily with SPI flash chips.
This CL adds declarations of register addresses and bits.
BUG=b:192262089
TEST=Flashed OpenTitan FPGA via HyperDebug OctoSPI
Change-Id: I33d16ba493756cf338353a5f0952be97070720d6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4087327
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Tested-by: Jes Klinke <jbk@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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The STM32L5 series has a special "OctoSPI" controller, which differs
from the standard spi controllers in capabilities and means of
programming. Rather than adding drivers for OctoSPI to the common EC
code, this change allows special-purpose drivers for HyperDebug to be
implemented in its board directory.
BUG=b:192262089
TEST=Observed HyperDebug forwarding to OctoSPI controller
Change-Id: Ia31eefcb53b08cc23aa0f14a8899bc227a88ea0c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077429
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Tested-by: Jes Klinke <jbk@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
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For devices similar to Servo Micro, in case of multiple entries in
spi_devices, this change allows the USB host to request which device its
transaction requests are to be forwarded to.
BUG=b:192262089
TEST=HyperDebug board forwards to two SPI busses
Change-Id: Ic94e66a8d7f5502c3016a26a1beb24236b3c4893
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077428
Commit-Queue: Jes Klinke <jbk@chromium.org>
Tested-by: Jes Klinke <jbk@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This CL add support logging system boot time and hostcommand to get
boot time info.
EC logs elapsed time (in micro second) info since boot for different
signal events,that can be used to calculate system boot time in cold
boot and warm boot scenarios.
Below are the events when EC logs time info
ARAIL EC turns on A-RAIL
RSMRST EC releases RSMRST#
ESPIRST ESPIRST received
PLTRST_LOW PLTRST# asserted
PLTRST_HIGH PLTRST# deasserted
EC_CUR_TIME EC current time
cnt increments on every warm reboot and reset to 0 on
cold reboot
BUG=b:249163956
BRANCH=none
TEST='ectool boottime' AP console command is used to fetch data
'reboot' on AP console to trigger warm reboot
'apshutdown' on EC console to trigger cold reboot
Signed-off-by: Rajesh Kumar <rajesh3.kumar@intel.com>
Change-Id: I47abe3f8a0b7ab43f2af11bf8387c006ba383020
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4081566
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Tested-by: Li-Yu Yu <aaronyu@google.com>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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This reverts commit c8325ba18b9f4d5b1f3f3bc739e83d8f591308cf.
Reason for revert: broke at least 9 cq builds (https://ci.chromium.org/ui/p/chromeos/builders/cq/cq-orchestrator/b8795833246203447793/overview)
Original change's description:
> ec: Support logging system boot time info
>
> This CL add support logging system boot time and hostcommand to get
> boot time info.
> EC logs elapsed time (in micro second) info since boot for different
> signal events,that can be used to calculate system boot time in cold
> boot and warm boot scenarios.
>
> Below are the events when EC logs time info
>
> ARAIL EC turns on A-RAIL
> RSMRST EC releases RSMRST#
> ESPIRST ESPIRST received
> PLTRST_LOW PLTRST# asserted
> PLTRST_HIGH PLTRST# deasserted
> EC_CUR_TIME EC current time
> cnt increments on every warm reboot and reset to 0 on
> cold reboot
>
> BUG=b:249163956
> BRANCH=none
> TEST='ectool boottime' AP console command is used to fetch data
> 'reboot' on AP console to trigger warm reboot
> 'apshutdown' on EC console to trigger cold reboot
>
> Signed-off-by: Rajesh Kumar <rajesh3.kumar@intel.com>
> Change-Id: I15fedbde252e0452270ef0e3fd4391bf624169f1
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3794612
> Reviewed-by: Boris Mittelberg <bmbm@google.com>
> Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Bug: b:249163956
Change-Id: Ie83026c4a3a38c3dd24522901233f06e03430a54
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4077335
Reviewed-by: Jonathon Murphy <jpmurphy@google.com>
Commit-Queue: Piotr Pawliczek <pawliczek@chromium.org>
Tested-by: Piotr Pawliczek <pawliczek@chromium.org>
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This CL add support logging system boot time and hostcommand to get
boot time info.
EC logs elapsed time (in micro second) info since boot for different
signal events,that can be used to calculate system boot time in cold
boot and warm boot scenarios.
Below are the events when EC logs time info
ARAIL EC turns on A-RAIL
RSMRST EC releases RSMRST#
ESPIRST ESPIRST received
PLTRST_LOW PLTRST# asserted
PLTRST_HIGH PLTRST# deasserted
EC_CUR_TIME EC current time
cnt increments on every warm reboot and reset to 0 on
cold reboot
BUG=b:249163956
BRANCH=none
TEST='ectool boottime' AP console command is used to fetch data
'reboot' on AP console to trigger warm reboot
'apshutdown' on EC console to trigger cold reboot
Signed-off-by: Rajesh Kumar <rajesh3.kumar@intel.com>
Change-Id: I15fedbde252e0452270ef0e3fd4391bf624169f1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3794612
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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Sort all includes in board with the clang-format rules used by
the zephyr project.
BRANCH=None
BUG=b:247100970
TEST=zmake build -a
TEST=./twister --clobber -v -i
TEST=make -j72 buildall_only runtests
TEST=zmake compare-builds -a
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Change-Id: I6ad72b167cbb768a64c338fa633eb4bf5a401897
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4060360
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: Jeremy Bettis <jbettis@chromium.org>
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
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Sort all includes in chip with the clang-format rules used by
the zephyr project.
BRANCH=None
BUG=b:247100970
TEST=zmake build -a
TEST=./twister --clobber -v -i
TEST=make -j72 buildall_only runtests
TEST=zmake compare-builds -a
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Change-Id: I13454e38fa3766aa0ba26a058075f51965b8462e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4053346
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
Tested-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Add "chip/stm32/usb_hw.h" for usb_uint
Add <stddef.h> for size_t
Switch from board.h to config.h
BRANCH=None
BUG=b:247100970
TEST=zmake build -a
TEST=./twister --clobber -v -i
TEST=make -j72 buildall_only runtests
TEST=zmake compare-builds
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Change-Id: I8d6c7cb89cd54812b90afd9ec06d81f8122fbdc7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4053345
Reviewed-by: Tomasz Michalec <tmichalec@google.com>
Commit-Queue: Tomasz Michalec <tmichalec@google.com>
Auto-Submit: Jeremy Bettis <jbettis@chromium.org>
Tested-by: Jeremy Bettis <jbettis@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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It was found that the hardware SHA256 accelerator is broken. This is
caused by the table address of SHA ROM API changed from 0x100 to 0x13C
since the ES2 chip.
This CL fixed the issues described above.
BRANCH=none
BUG=b:155771688
TEST=burn the same RW image; #define/#undef CONFIG_SHA256_HW_ACCELERATE;
verify the RW hash value is the same in the console message.
TEST=with the test CL:2455022, move test patterns in test/sha256.c
to board/npcx9_evb/test_sha256.c; pass all test patterns.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I12ce8531a925f02474f66d90bf7efd950b3eeba3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4033807
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Commit-Queue: Boris Mittelberg <bmbm@google.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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ISH should set PMC LTR(Latency Tolerance Reporting) for DMA operation.
Without doing this, we observed system shutdown during D0i3.
This CL set LTR to 2ms before DMA operation and set LTR to a large
number after DMA operation is completed to enable SOC to go into the
lowest possible power state.
BUG=b:234136500
BRANCH=none
TEST=on Nirwen platform, ISH enter D0i3 host loading case, and also
stitching to coreboot case; S0i3 is hit and no shutdown.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Signed-off-by: Li Feng <li1.feng@intel.com>
Change-Id: Ib0fe907470774998dda29a40197d6c18ad6372f1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4003320
Code-Coverage: Haribalaraman Ramasubramanian <haribalaraman.r@intel.corp-partner.google.com>
Reviewed-by: Kyoung Kim <kyoung.il.kim@gmail.com>
Reviewed-by: Haribalaraman Ramasubramanian <haribalaraman.r@intel.corp-partner.google.com>
Commit-Queue: Kangheui Won <khwon@chromium.org>
Tested-by: Haribalaraman Ramasubramanian <haribalaraman.r@intel.corp-partner.google.com>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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CONFIG_STM_HWTIMER32 was used to choose between a 32-bit timer and
16-bit timer. The 16-bit timer code was removed in
https://crrev.com/c/3388064, so we no longer need this config.
Command used:
git grep --name-only CONFIG_STM_HWTIMER |\
xargs sed -i '/CONFIG_STM_HWTIMER32/d'
BRANCH=none
BUG=b:214423235
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I89da8915cd5a467975cd8f90e734ea2b11f18cb3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3388065
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Reviewed-by: Patryk Duda <patrykd@google.com>
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stm32/hwtimer.c simulates a 32-bit timer with two 16-bit timers. The
only boards still using this file were "discovery" and "twinkie".
"twinkie" is an STM32F072B, which has support for 32-bit timers (TIM2
and TIM3). See Section 18 "General-purpose Timers":
https://www.st.com/resource/en/reference_manual/dm00031936-stm32f0x1-stm32f0x2-stm32f0x8-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf.
"discovery" is an STM32L152RC, which is a "Category 3" product that
has the 32-bit timer TIM5. See Section 17 "General-purpose Timers" and
"Table 3. STM32L15xxx product categories":
https://www.st.com/resource/en/reference_manual/cd00240193-stm32l100xx-stm32l151xx-stm32l152xx-and-stm32l162xx-advanced-arm-based-32-bit-mcus-stmicroelectronics.pdf.
BRANCH=none
BUG=b:214423235
TEST=make buildall -j
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I41b3a54bbbbce5d0dfee178b6fa87ff492646ce1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3388064
Reviewed-by: Patryk Duda <patrykd@google.com>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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Prevent possibility of array[-1] access
BUG=b:64477774
BRANCH=none
TEST=none
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I130b7d3872f857dc6e8dabca3f07d0d919b7ce64
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4018487
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
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When building with clang, it fails with:
chip/mchp/lfw/ec_lfw.c:310:2: error: non-ASM statement in naked function
is not supported
uart_puts("EXCEPTION!\nTriggering watchdog reset\n");
^
chip/mchp/lfw/ec_lfw.h:25:41: note: attribute is here
void fault_handler(void) __attribute__((naked));
^
BRANCH=none
BUG=b:172020503
TEST=./util/build_with_clang.py
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: If998119e285b3a068623909a373f3ebaf426b2e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3977110
Reviewed-by: Eric Yilun Lin <yllin@google.com>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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Linking with clang/lld fails since it tries to include .ARM.exidx in the
VECTOR region:
ld.lld: error: section '.ARM.exidx' will not fit in region 'VECTOR':
overflowed by 328 bytes
We don't need the exception index table or exception table (see
https://crrev.com/c/3857943). This matches the behavior in our other
linker scripts:
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/platform/ec/core/cortex-m/ec.lds.S;l=745;drc=84b2904dead700e10073080c54e69ea162d8a7c5
This change does not affect the gcc/ld build (identical output before and
after).
BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I65df11f3ab0c439ea3d4ce2805afaac942b22a0e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3989667
Reviewed-by: Diana Z <dzigterman@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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Both ISH shim loader and main firmware have PM initialization. Main
firmware doesn't do a full configuration because some are done in shim
loader.
This is working fine if we use host loading main firmware
scheme. We observed problem in IPAPG if stitching main firmware to coreboot
and skip shim loader.
This CL modifies pm_init to fully configure PM. So ISH main firmware
functions correctly in both loading methods.
BUG=b:234136500
BRANCH=none
TEST=make buildall
TEST=on ADL-P RVP, ISH enter IPAPG state in host loading case, and also
stitching to coreboot case.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Signed-off-by: Li Feng <li1.feng@intel.com>
Change-Id: I603e2f107fdce672ac12bac9d848820f58474910
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3985606
Reviewed-by: Kyoung Kim <kyoung.il.kim@gmail.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Commit-Queue: Reka Norman <rekanorman@chromium.org>
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Linking with clang/lld fails since it assumes the region .fill should
use is VECTOR:
ld.lld: error: section '.fill' will not fit in region 'VECTOR':
overflowed by 328 bytes
This change does not affect the gcc/ld build (identical output before and
after).
BRANCH=none
BUG=b:172020503
TEST=./util/compare_build.sh -b all -j 120
=> MATCH
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ieeff37fc13befe495dbc567b4be363da07a75c3a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3989666
Reviewed-by: Eric Yilun Lin <yllin@google.com>
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The flash bank definition is used to check the protection block. There
is no reason to define it following the flash erase size setting.
This CL sets the smallest flash bank size to 64KB, which is 1/8 of 512KB
or 1/16 of 1MB flash.
BRANCH=none
BUG=b:254877499
TEST="BOARD=npcx9_evb make", use console command flashwp/flashinfo to
check the flash protection.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I9dfdc4083e2aa0a198ff882ecaa7794bb6ac5ad5
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3980704
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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The current driver reports the configured level regardless of the GPIO's
direction (input/output). It should report it only when the pin in
question is an output. Also, it should read the level from the PxDOUT
register instead of the PXDIN register.
BRANCH=none
BUG=b:254739925
TEST=build npcx9_evb with CONFIG_GPIO_GET_EXTENDED and
CONFIG_CMD_GPIO_EXTENDED defined, check the report form `gpioget`
console command is correct.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I1f40bb757c1a012697374b294b57934608d5e293
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3967955
Tested-by: CH Lin <chlin56@nuvoton.corp-partner.google.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Andrew McRae <amcrae@google.com>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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The EC code has generally been good about adding comments about
intentional fallthrough in switch statements, but there were a few cases
without comments (e.g., https://crrev.com/c/3949622). Enabling
-Wimplicit-fallthrough generates a compiler warning if the fallthrough
is not annotated with __attribute__((fallthrough)). For convenience, we
add a "__fallthrough" macro for this attribute.
See https://clang.llvm.org/docs/AttributeReference.html#fallthrough and
https://gcc.gnu.org/onlinedocs/gcc/Statement-Attributes.html.
BRANCH=none
BUG=b:253644823
TEST=make buildall
LOW_COVERAGE_REASON=legacy code
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I9f4d6049f4507a25ce706675d159b70e28b4b825
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3957420
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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EC software reset doesn't reset pltrst# by default.
This change was made to reset pltrst# during espi reset.
So Ampton won't get stuck after watchdog reset.
BRANCH=octopus
BUG=b:235443631
TEST=Ampton won't get stuck after watchdog reset.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ice77a902185046757d6b7bc70edee53eb81e64dc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3959261
Commit-Queue: Henry Sun <henrysun@google.com>
Reviewed-by: luluboy luluboys <luluboy5208@gmail.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Tested-by: Luluboy Jian <luluboy_jian@asus.corp-partner.google.com>
Tested-by: luluboy luluboys <luluboy5208@gmail.com>
Reviewed-by: Luluboy Jian <luluboy_jian@asus.corp-partner.google.com>
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There are no longer any boards that use chip/mec1322.
BRANCH=none
BUG=none
TEST=CQ passes
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ie03535c6c62c61c86fc2714ec4e7bc48eb0e2d79
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3953934
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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When building with clang it warns:
chip/mchp/lpc.c:966:9: error: implicit conversion from enumeration type
'enum ec_error_list' to different enumeration type 'enum ec_status'
[-Werror,-Wenum-conversion]
return EC_SUCCESS;
~~~~~~ ^~~~~~~~~~
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=reef_mchp
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I680cea90f72d3743ef4b92e13e57e63557cba702
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3953490
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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These macros are easier to read and use than the underlying pragmas.
BRANCH=none
BUG=b:172020503
TEST=make buildall
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I2f67cbb3f83230b7e1a6a4512471bbd2bec0498f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3872552
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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It's always enabled in the core/<core>/core_config.h files. The
following script demonstrates that it's enabled in all boards:
for board in `make print-boards`; do
make print-configs board="${board}" | grep -q CONFIG_SOFTWARE_PANIC
if [ $? -ne 0 ]; then
echo "${board} failed"
exit 1
fi
done
BRANCH=none
BUG=none
TEST=make buildall
Cq-Depend: chromium:3943248
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: If683b244f17b48bedf3699f2b24e83b5ad6e849e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3933255
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
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When building with clang it warns:
chip/stm32/clock-stm32l4.c:400:9: error: explicitly assigning value of
variable of type 'uint32_t' (aka 'unsigned int') to itself
[-Werror,-Wself-assign]
val = val;
~~~ ^ ~~~
BRANCH=none
BUG=b:172020503
TEST=CC=clang make BOARD=hyperdebug
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: Ie4fae7251747d27b96ed08c3ef166fddd5411b9a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3947822
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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