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* cr50: use run time generated public RMA key definitionVadim Bendebury2018-04-041-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Use RMA public key definition generated based on the binary blob containing the key and key ID. Key generation is controlled by the make file in common/, but actual key blob comes from the board directory. The structure holding the key and key ID is being modified to allow initialization using a flat array. No more need in defining CONFIG_RMA_AUTH_SERVER_PUBLIC_KEY and CONFIG_RMA_AUTH_SERVER_KEY_ID. BRANCH=cr50, cr50-mp BUG=b:73296144, b:74100307 TEST='make buildall' still succeeds. test RMA server generated authentication codes are accepted when unlocking RMA. Change-Id: I8ade94de6eb69b3e49bc5b948dbac20e59962acf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/990783 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Add support for PWM LEDs.Aseda Aboagye2018-02-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds support for a common framework for PWM controlled LEDs. If there are multiple LEDs, they will all follow the same pattern. The pattern is such that it follows the Chrome OS LED behaviour specification, essentially a similar version of led_policy_std.c but for PWM controlled LEDs. To use this framework, a board must do the following: - First, define the number of logical PWM LEDs which will be controlled by this common policy, CONFIG_LED_PWM_COUNT. - Then declare those logical LEDs and define the PWM channels that comprise those LEDs. (struct pwm_led pwm_leds[]). - Next, define what each color should look like (struct pwm_led led_color_map[]). By default, the colors follow the recommended colors in the LED behaviour spec, which assume an LED with a red and green channel. If a board differs or wishes to change the colors in general, they can redefine the colors (CONFIG_LED_PWM_*_COLOR) as they see fit. The colors must be one in enum ec_led_colors. These colors are the ones that can represent the charging state, SoC state, etc. BUG=b:69138917,chromium:752553 BRANCH=None TEST=make -j buildall TEST=Enable led_pwm for meowth, and verify that LEDs behave as expected. Change-Id: I945b86a7f8ed30df58d7da835d83577192548bea Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/888220 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* samus_pd: Remove 'adc' console commandShawn Nematbakhsh2018-01-301-1/+1
| | | | | | | | | | | | | | | Remove console command for flash / RAM savings. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Ibfccbdf45e5c86260cc55237387994fdf094c19c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/885463 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Make CONFIG_MALLOC partition-specificVincent Palatin2018-01-261-4/+3
| | | | | | | | | | | | | | | | | | | Allow to have CONFIG_MALLOC defined for one partition and not the other. The typical use-case is asymetric firmware whose small RO is typically just an updater/verifier (and RW signature verification currently doesn't like malloc as the memory initialization is done too late). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:72360575 TEST=make buildall Change-Id: I67cc04cd11385d4c05556ea41ef674cb7a232e65 Reviewed-on: https://chromium-review.googlesource.com/885820 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* CBI: Read board info from EEPROMDaisuke Nojiri2018-01-181-0/+1
| | | | | | | | | | | | | | | This patch adds Cros Board Info APIs. It reads board info from EEPROM. This patch sets CONFIG_CBI for Fizz to make it use CBI. BUG=b:70294260 BRANCH=none TEST=Read data from EEPROM. Change-Id: I7eb4323188817d46b0450f1d65ac34d1b7e4e220 Reviewed-on: https://chromium-review.googlesource.com/707741 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec_ec_comm_master: Functions for EC-EC communication masterNicolas Boichat2018-01-051-0/+1
| | | | | | | | | | | | | | This adds functions required for the master in EC-EC communication, requesting base battery static and dynamic information, and charger control. BRANCH=none BUG=b:65526215 TEST=Flash lux and wand, EC-EC communication works. Change-Id: I7a46ee3f5848d22c2c9bea7870cbd7e74141cf3d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/839201
* espi: Add API to test if signal is eSPI virtual wireScott Worley2018-01-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | Add espi_signal_is_vw in new file common/espi.c for testing if a signal is an eSPI virtual wire. API used in power common and intel_x86. Fix CONFIG_BRINGUP support for eSPI (off by default). Add espi_vw_get_wire_name returning a pointer to constant string. Chip modules do not need to maintain names of eSPI signals. BRANCH=none BUG= TEST=Build poppy and other eSPI enabled boards. Test power state machine. Change-Id: I13319e79d208c69092a02ec3ac655477d3043d61 Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/836818 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* ec_ec_comm_slave: EC-EC communication slave task and functionsNicolas Boichat2017-12-201-0/+1
| | | | | | | | | | | | | | | | | This adds functions required for the slave in EC-EC communication, including the task that processes requests from the master. This also adds required CONFIG_EC_EC_COMM_SLAVE/MASTER/BATTERY config options. BRANCH=none BUG=b:65697962 TEST=Build wand and lux boards, flash it, EC-EC communication works. Change-Id: I772d9023a830f4fbc37316ca31e4da8240de7324 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/828180 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* eve_fp: update fingerprint architectureVincent Palatin2017-12-061-0/+1
| | | | | | | | | | | | | | | | | split the common FP sensor code and use the updated private driver. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:69460856 TEST=do a finger capture on Eve EVT. CQ-DEPEND=CL:*520759 Change-Id: I8b46762218eed0773a4c49a02c2ee6c3966cfa60 Reviewed-on: https://chromium-review.googlesource.com/806166 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* ppc: Create generic PPC driver framework.Aseda Aboagye2017-12-061-0/+1
| | | | | | | | | | | | | | | | | | | | | This commit introduces a driver framework for power path controllers. It provides some common PPC APIs as well as allowing a board to use multiple different PPCs drivers/parts. This should make it easier to add PPC drivers in the future. BUG=None BRANCH=None TEST=`make -j buildall` TEST=Flash zoombini; verify PPC works as expected. TEST=Flash meowth; verify PPC works as expected. Change-Id: Icfb99f384610590b431456cfd28d4aff18442cb2 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/807630 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* buttons: Make buttons[] common.Aseda Aboagye2017-11-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Nearly every board had a buttons array defined in which its contents had the standard volume buttons. This commit creates a single common buttons array that can contain the standard volume buttons and recovery buttons. If a board has volume up and down buttons, they can simply define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with the standard definition. The buttons are active low and have a 30 ms debounce period. Similiarly, if a board has a dedicated recovery button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the buttons array with a recovery button. BUG=chromium:783371 BRANCH=None TEST=make -j buildall. TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume buttons still work. Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/773794 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* motion_sense: Put set_range in common codeGwendal Grignou2017-11-171-2/+1
| | | | | | | | | | | | | | | | At the end of the sensor initialization, all _init sensor routines set the range to the default value from board.c file. Put all the code in a single place, move it from sensor_common.c to motion_sense.c. BUG=none BRANCH=none TEST=compile Change-Id: If89cf27c6438e0f215c193d68a480e027110174c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767610 Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Add software CTZ implementation when needeedGwendal Grignou2017-11-161-0/+1
| | | | | | | | | | | | | | | | | CTZ - Count Trailing Zero - is not implemented in hardware on cortex0 or nds32. Used in ST sensor drivers. BUG=none BRANCH=none TEST=compile Change-Id: I2d62fd60f05169189b24ba2a3308bec69ed9de9c Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/767609 Commit-Ready: Ely Vazquez <nadia198877@gmail.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Use CONFIG_BATTERY to indicate whether a board has a batteryShawn Nematbakhsh2017-10-131-8/+1
| | | | | | | | | | | | | BUG=b:35528297 BRANCH=None TEST=`make buildall -j` Change-Id: I9e4814b4172f20711f7edd691c9569f9130aec8e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/713395 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* charge_ramp: Move ramp allowed / ilim callbacks to common codeShawn Nematbakhsh2017-10-061-1/+2
| | | | | | | | | | | | | | | | | | | | | The decision on whether to ramp (and how high) depends on the quirks of charger identification, so move the decision out of board, into the drivers that implement usb_charger. Also, rename CONFIG_CHARGE_RAMP to CONFIG_CHARGE_RAMP_SW, to better contrast with the existing CONFIG_CHARGE_RAMP_HW. BUG=None TEST=Manual on kevin, verify ramp occurs when port plugged into Z840 workstation. BRANCH=None Change-Id: I5b395274133837a18a4f4ac34b59b623287be175 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/702681 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: pd: Remove CONFIG_CASE_CLOSED_DEBUGShawn Nematbakhsh2017-10-051-1/+0
| | | | | | | | | | | | | | | | | | CONFIG_CASE_CLOSED_DEBUG (CCD functionality implemented by EC) is no longer used in conjunction with CONFIG_USB_POWER_DELIVERY, and the common routines are only used by one board. BUG=chromium:737755 BRANCH=None TEST=`make buildall -j` Change-Id: Idc3d2fccef6cbec2af786cef634d752a02a0e859 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656315 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rtc: Add functions and tests for time conversionPhilip Chen2017-09-261-0/+1
| | | | | | | | | | | | | | | | | | | | | To implement rtc driver for some ec chips, we need to convert between calandar date and seconds (since epoch time, 01-01-1970 00:00:00). Sicne these functions are HW-independent, let's add common/rtc.c, include/rtc.h, and unit test for this. BUG=b:63908519 BRANCH=none TEST=make buildall test -j Change-Id: Icb1e768d2b3674d5225b83e09475e984eb104d06 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/666985 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* Add WebUSB descriptor supportVincent Palatin2017-09-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The WebUSB specification defines a specific Platform Descriptor in the Binary Object Store: https://wicg.github.io/webusb/#webusb-platform-capability-descriptor This descriptor provides a special 'Landing page' URL to the host browser and associated privileges for it. Bump the USB version for BOS descriptors to 2.1 to be compatible with Chrome implementation. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=none BRANCH=twinkie TEST=manual: on Twinkie (chip/stm32) and HG proto2 (chip/g), enumerate WebUSB descriptors with lsusb and connect to a WebUSB page in Chrome R61+. Change-Id: I7211ab554f4a6c156c1e8e79a3d9f0d6644217c6 Reviewed-on: https://chromium-review.googlesource.com/664813 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Makefile: Generate hashes for the touchpad FWNicolas Boichat2017-09-151-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the passed TOUCHPAD_FW parameter to the make command, the build system generates hashes for the touchpad FW. To generate the hashes, gen_touchpad_hash splits the touchpad FW in blocks of CONFIG_UPDATE_PDU_SIZE, that are hashed individually (SHA-256), and then stored in the EC image. This will allow the USB updater code to verify the integrity of the touchpad firmware being flashed. When no FW is provided, zeros are output, which do not match any valid data. BRANCH=none BUG=b:63993173 TEST=make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \ BOARD=hammer -j TEST=Using variations of make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_3.0.bin \ BOARD=hammer -j make TOUCHPAD_FW=SA459C-1211_ForGoogleHammer_4.0.bin \ BOARD=hammer -j make BOARD=hammer -j Check that TPHASH touchpad_fw_hash.h is only regenerated when the parameter changes. Change-Id: Ie347270aa9c00342de13489c9422e45e681b94c2 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/615321 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* acpi: Map EC features into ACPI EC memory spacePatrick Georgi2017-08-301-1/+1
| | | | | | | | | | | | | | | | | Reserve EC address space offset 0x0a-0x0d for device features. Same value as with the host command, just different way to access it. BUG=b:64705535 BRANCH=none TEST=none Change-Id: I420aed1ae8d0fb7da477fc72ac55ea75a9f9350b Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/626976 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* ec_features: Move feature flags out of ec_command into its own unitPatrick Georgi2017-08-301-1/+1
| | | | | | | | | | | | | | | | | | Prepare for exposing the feature flags through EC ACPI memory space by moving the definitions and collection function into its own unit. BUG=b:64705535 BRANCH=none TEST=builds and returns the same value Change-Id: I66eabebe0d039fdcd14d11b9ecf77c0f1040d006 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/633925 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* EFS: Rename CONFIG_VBOOT_EC to _EFSDaisuke Nojiri2017-08-291-1/+1
| | | | | | | | | | | | | | This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tpm: Add optional event loggingShawn Nematbakhsh2017-08-101-0/+1
| | | | | | | | | | | | | | | | | | Allow TPM to log events in a circular buffer through tpm_log_event(). Logs can be retrieved through a new vendor command VENDOR_CC_POP_LOG_ENTRY. BUG=b:63760920 TEST=On eve, store TPM logs through 'logentry' cr50 console command, verify logs are fetched correctly through 'trunks_send --pop_logentry'. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idbc405728c0ba68078447fb59717d6115830e3d8 Reviewed-on: https://chromium-review.googlesource.com/599352 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* pd_log: Make PD logging more generic for general purpose loggingShawn Nematbakhsh2017-08-021-1/+1
| | | | | | | | | | | | | | | | | | We can re-use our pd_log FIFO for other purposes, such as TPM logging. Carve out event_log, a generic logging module which pd_log is compatible with. BUG=b:63760920 TEST=On kevin, verify PD logging is still functional and entries are seen in dmesg. BRANCH=None Change-Id: I8e6ad6f93e9eebc676aca64652c60f81da471a94 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/597314 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* battery/max17055: Add max17055 fuel gauge driverPhilip Chen2017-07-271-0/+1
| | | | | | | | | | | | | | | | | BUG=chromium:736603 BRANCH=none TEST=Follow the steps below 1) add MAX17055 config to Scarlet and build the code 2) hook up max17055 eval board and a single cell battery 3) battery command from ec console shows reasonable numbers for temperature, voltage, and charge percentage Change-Id: I3f838ff92c591665e9f1d0a7ba636ff83d9b7612 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/578300 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cr50: Add case closed debugging V1 configurationRandall Spangler2017-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the CCD configuration module, and the console commands to control it. It is not wired up to any of the CCD capabilities; that's coming in the next CL. Briefly: * CCD configuration is persistently stored in nvmem_vars. Use ccdinfo to print it. * CCD can be Locked, Unlocked (some capabilities), or Opened (all capabilities), using the ccdlock / ccdunlock / ccdopen commands. * CCD config can be restricted by setting a password via ccdpass. * Individual config capabilities can be set via ccdset. Some of those will be used to gate access to things like write protect and UARTs. Others affect the requirements for ccdunlock / ccdopen (for example, is physical presenc required). * The entire config can be reset via ccdreset. If only unlocked, config that is restricted to Opened is not reset. * If CR50_DEV=1, ccdoops will force-reset and open the config. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual with CR50_DEV=1 build gpioget # make sure GPIO_BATT_PRES_L=0 ccdlock # lock, because CR50_DEV=1 builds start unlocked ccdinfo # locked, flags=0, all capabilities default ccdpass # access denied (we're locked) ccdreset # access denied ccdset flashap always # access denied ccdunlock ccdinfo # unlocked ccdpass foo ccdinfo # flags=2 (password set when unlocked) ccdset flashap always # access denied ccdset uartectx unlesslocked ccdinfo # yes, uartectx permission changed ccdlock ccdunlock # fails without password ccdunlock bar # wrong password ccdunlock foo # busy (wait 3 sec) ccdunlock foo ccdreset ccdinfo # no password, flags 0, capabilities all default ccdopen # requires physical presence; tap power or use 'pp' ccdset uartectx unlesslocked ccdset batterybypasspp ifopened ccdpass baz ccdinfo # password set, flag 0, ccdset changes worked ccdunlock ccdreset ccdinfo # uartectx back to ifopened, password still set ccdopen baz # still requires physical presence ccdset opennolongpp always ccdlock ccdopen baz # no pp required ccdset unlocknoshortpp unlesslocked ccdlock ccdopen baz # short pp sequence required (3 taps) ccdlock ccdunlock baz # short pp sequence required ccdopen baz # pp not required ccdset unlocknoshortpp always ccdlock testlab open # access denied testlab enable # access denied ccdunlock baz testlab open # access denied testlab enable # access denied ccdopen baz testlab enable # requires short pp ccdinfo # flags 1 ccdreset ccdinfo # no password, flags=1, caps all default ccdlock testlab open ccdinfo # opened testlab disable # requires short pp; let it time out ccdinfo # still opened, flags=1 ccdlock ccdoops # backdoor in CR50_DEV images to force-reset CCD ccdinfo # opened, flags=0, all defaults (yes, oops wipes out testlab) ccdreset rma ccdinfo # flags = 0x400000, everything but Cr50FullConsole always ccdreset # back to flags=0, all default Change-Id: I24e8d8f361874671e6e94f27492ae00db919bea9 Reviewed-on: https://chromium-review.googlesource.com/569439 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: Add physical presence state machineRandall Spangler2017-07-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This will be used as part of case closed debugging configuration. Currently, this only adds the state machine, and a test command which is available when CR50_DEV=1. It also adds a new sleep mask flag for physical presence detect, instead of oveloading FORCE_NO_DSLEEP. The physical presence state machine supports both short (tap 5 times in 15 seconds) and long (short, followed by 4 more taps 1-5 minutes apart) sequences. It will call a callback function at the end of the sequence, so that multiple things can each request physical presence in turn. This will be used by ccdopen / ccdunlock / testlab commands for CCD V1. Eventually, CCD config will replace the unlock sequence handling in wp.c. But for now, we don't touch that. See go/cr50-ccd-wp for more information. BUG=b:62537474 BRANCH=none TEST=manual Short sequence: pp short pp pp pp # See "Physical presence good" Timeout pp short pp # 15 sec later, get timeout error Long sequence: pp long pp pp pp (wait 2 sec) pp (wait 2 sec) pp # See "PP good" Long sequence, presses too fast: pp long pp pp pp pp # See "PP L too soon" (wait 2 sec) pp (wait 2 sec) pp # See "Physical presence good" Abort: pp short pp abort # See "Physical presence aborted" Change-Id: I09da81ad11d328e7d7740c3fe838a5f67d7b8708 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/568796 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* vboot: Move common code under common/vbootDaisuke Nojiri2017-07-131-2/+3
| | | | | | | | | | | | | | | This patch moves the code which can be shared with other data verification schemes (e.g. RWSIG) under common/vboot. It also adds unit tests for it. BUG=b:38462249 BRANCH=none TEST=make run-vboot. Verify verification succeeds on Fizz. Change-Id: Icab4d96dd2c154a12b01c41ebe9b46286b4b590e Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/563463 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* core/cortex-m0/curve25519: Integrate fast curve25519 implementationNicolas Boichat2017-07-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Move generic implementation to curve25519-generic.o - Always use optimized version on cortex-m0. - Rename .s files to .S, remove unnecessary lines in assembly files. - Rename crypto_scalarmult_curve25519 to x25519_scalar_mult to match the signature provided by the generic implementation. - Replace some handcoded memcpy with function calls - Remove unnecessary "volatile" specifications in the code. BRANCH=none BUG=b:62813194 TEST=To test old implementation only: - Increase CONFIG_RO_SIZE to 60kb - Increase console stack size to 2048 make BOARD=hammer PROJECT=x25519 TEST_BUILD=y ./util/flash_ec --board=hammer --image=build/hammer/x25519.bin EC console: runtest, taskinfo => Used to takes ~4'17" to run (X25519 duration 256347 us). 1496/2048 stack size usage in CONSOLE task => Now takes ~1'25" to run (X25519 duration 84520 us) 732/2048 stack size usage in CONSOLE task TEST=In test/x25519.c, uncomment #define TEST_X25519_1M_ITERATIONS make BOARD=hammer PROJECT=x25519 TEST_BUILD=y ./util/flash_ec --board=hammer --image=build/hammer/x25519.bin EC console: runtest, wait ~23 hours, test passes. TEST=- Define CONFIG_CURVE25519_CORTEXM0 (next patch) makes newsizes build/hammer/RW/ec.RW.flat shrank by 1888 bytes: (52208 to 50320) Change-Id: Icce38d3c32f431a85ac0f951cf34456b490dc665 Reviewed-on: https://chromium-review.googlesource.com/540962 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* common: Add RMA reset auth challenge-response cryptoRandall Spangler2017-06-301-0/+1
| | | | | | | | | | | | | | | | RMA auth uses X25519 to generate a relatively small challenge and response. Currently, nothing calls the rma_auth code. We'll need console and TPM vendor commands to do so. BUG=b:37952913 BRANCH=none TEST=make buildall Change-Id: Iec7f2d0e3dc8243f79b009ead16bb3ba9f1bef9d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/544184
* Add support for reporting device eventsDuncan Laurie2017-06-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | In order to report specific wake events from differernt devices add a host command that allows setting device event mask, and triggering a host event when that device event is set. This is done as a separate command and mask because we are running out of host events, and it takes over the unused thermal overload event that was never used in EC or BIOS. The first use case for this is platforms that have AP wake events that go to the EC, for instance devices that use Deep S3 and have a limited set of wake pins. (such as Eve) This allows the AP to determine the exact wake source for an event so it can be logged and acted on by the AP if necessary. BUG=b:36024430 BRANCH=eve TEST=manual testing on eve with trackpad and dsp wake events Change-Id: I48d94014c00dc1dad098ab96af0ddc7860229762 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/555632 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* Add U2F implementationVincent Palatin2017-06-291-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add the common code to support FIDO U2F (Universal second factor authentication) protocol implementation: the APDU parsing and standard commands execution, plus a few non-standard flags and hooks. The u2f.h header is the unmodified copy from the U2F v1.1 Specifications archive. Mostly copied over from the cr52 code-base. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=cr50 BUG=b:35545754 TEST=with follow-up CLs, run U2FTest on Eve. CQ-DEPEND=CL:*390230 Change-Id: I636d4a77ea69d69b5ab18a958e58ee6fcb2476bc Reviewed-on: https://chromium-review.googlesource.com/518136 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: Add base32 encodingRandall Spangler2017-06-281-0/+1
| | | | | | | | | | | | | | Base32 encoding is used to turn the RMA reset binary challenge/response into less-typo-prone text, at 5 bits per character. BUG=b:37952913 BRANCH=none TEST=make runtests Change-Id: I474750a20204ba353cea1e91982aa03e8071c0c2 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/544177 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* vboot: Add vboot for EC by ECDaisuke Nojiri2017-06-281-0/+1
| | | | | | | | | | | | | | | | | This patch adds vboot for EC by EC (vboot EC) for x86 systems. When ec is transitioning s5->s3, it checks the power supply is enough to boot AP or not. If not, it runs other checks and may finally validate and jump to a RW image. BUG=b:38462249 BRANCH=none TEST=Boot Fizz on barrel jack and type-c charger. Change-Id: I5988b0595976370c5303c45541702ae89d86fc97 Reviewed-on: https://chromium-review.googlesource.com/518254 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Add non-volatile flash counterVincent Palatin2017-06-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the implementation of a robust non-volatile incrementing counter using 2 pages from the underlying flash. It is used to implement the U2F functionality. The main goal of the counter is providing a strictly incrementing value whatever adverse events (malicious or not) happen as it is used to prevent rollback attacks in the U2F protocol. Given the limitation of the flash process: ie wear-out endurance and 2kB-page erase granularity only and possible isolated bit-flips (accentuated by power losses), the counting is done by pulling down several bits at a time from their erased state (1) to 0. The counting is implemented this way with 2 pages called LOW and HIGH: The LOW page is implemented in a strike style, with each "strike" zero-ing out 4 bits at a time, meaning each word can be struck a total of 8 times. Once the LOW page is completely struck, the HIGH page is incremented by 2. The even increment is for the value, the odd increment is a guard signal that the LOW page must be erased. So as an example: If HIGH is 2, the LOW page would increment to 3, erase itself, and then increment to 4. If this process is interrupted for some reason (power loss or user intervention) and the HIGH left at 3, on next resume, the HI page will recognize something was left pending and erase again. For a platform with 2-kB flash pages, it can count up to 8388608, then it is stuck at 0xFFFFFFF indefinitely. Mostly copied over from Marius code in cr52 code-base. Signed-off-by: Marius Schilder <mschilder@google.com> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=cr50 BUG=b:35545754 TEST=with follow-up CLs, run U2FTest on Eve Change-Id: Idd0756078e3641c4a24f9c4ccf6611909bd5f00f Reviewed-on: https://chromium-review.googlesource.com/518135 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* i2c: separate slave and master codeWei-Ning Huang2017-04-261-1/+2
| | | | | | | | | | | | | | | | | | | | Split i2c.c code in two (i2c_slave.c and i2c_master.c). i2c_slave.c is used when EC has no i2c device connected (i2c master code not needed) but EC is connected to AP via i2c. BRANCH=none BUG=b:37584134 TEST=1. Compile rose board with CONFIG_I2C and CONFIG_CMD_HOSTCMD. Then make sure EC_CMD_GET_PROTOCOL_INFO works. 2. On Kevin and Elm, cherry-pick to firmware branch respectively, build and flash ec, i2c function works. Change-Id: I1f95ad277713c5e30913e0a010ca03dfd9ec248c Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://chromium-review.googlesource.com/484999 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common/rollback: Add support for rollback protectionNicolas Boichat2017-04-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement actual rollback protection. First, we add a new field in the version structure, which is an incrementing integer (we'll start by shipping images with version 0, and gradually increase the number as required). This allows us to release new versions of the EC without necessarily bumping the rollback protection. For the rollback protection block itself, it contains 2 sub-blocks of equal size (normally, 2k), that are individually erasable. The rollback code looks at both, and takes the most restrictive one to determine the desired rollback minimum version. The blocks are also allowed to be erased (full of 1's), in which case the rollback minimum version is assumed to be 0. We also add an FMAP entry, in case we later decide to allow the signer to increment the rollback version. Also note that, like any version_data struct change, this change breaks compatibility between old and new RO/RW. Follow-up code will take care of auto-updating the rollback block as required, and properly manage block protection. BRANCH=none BUG=b:35586219 TEST=Flash hammer rollbackinfo => 1 version 0 block, 1 empty block, RW verifies correctly. rollbackupdate 0; rollbackinfo => No change rollbackupdate 1; reboot => RO refuses to jump to RW rollbackupdate 2, 3, 4; rollbackinfo => Writes alternate between the 2 blocks. rollbackupdate 2 => Refuses to downgrade version Change-Id: Ia969afb481a93deb912b9153bdd95ace01ad8fa7 Reviewed-on: https://chromium-review.googlesource.com/452815 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add option to adjust compiler optimization on RSAVincent Palatin2017-03-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | Using -O3 optimization level rather than -Os results in a large speed-up for a minor code size increase for the RSA code with our current GCC toolchain. Add the CONFIG_RSA_OPTIMIZED option to do it on platforms which are not too size-constrained. On cortex-M4 based STM32L432, I'm measuring a 37 to 40% speed increase (depending on CPU frequency) for a 200 bytes code size delta. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=manual: benchmark RSA2048 with F4 exponent on STM32L432: -Os -O3 @16Mhz 185163 us --> 111942 us @80Mhz 39286 us --> 24582 us Change-Id: I8c2e4b757f037f4f645fb73ba0faaaa471b24896 Reviewed-on: https://chromium-review.googlesource.com/445218 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* curve25519: strip-down, build and testVincent Palatin2017-02-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Keep only the most compact version of the curve25519 code and remove the remaining unused code for easier compilation. Do the minimal changes to make it compile in the EC code base, there should be no real functional changes. Re-use the wording from BoringSSL include/openssl/curve25519.h for the header. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:62991 TEST=run x25519 on host (ie 'make run-x25519') and the STM32L4 target: make BOARD=eve_fp PROJECT=x25519 TEST_BUILD=y ./util/flash_ec --board=eve_fp --image=build/eve_fp/x25519.bin execute 'runtest' in the console. Change-Id: I13dbe453eff39b461effb1b3ffa549afc1749fef Reviewed-on: https://chromium-review.googlesource.com/444187 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Adam Langley <agl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* console: Add non-verbose print config optionShawn Nematbakhsh2017-02-111-1/+2
| | | | | | | | | | | | | | | | | Shorten certain long prints and reduce the precision of timestamp prints when CONFIG_CONSOLE_VERBOSE is undef'd. BUG=chromium:688743 BRANCH=gru TEST=On kevin, cold reset the EC, boot to OS, and verify cros_ec.log contains all data since sysjump and is < 2K bytes (~1500 bytes). Change-Id: Ia9390867788d0ab3087f827b0296107b4e9d4bca Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/438932 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* driver: accel: Add acc driver basics and FIFO for LIS2DH/LIS2DH12Mario Tesi2017-02-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add driver for acc sensor ST lis2dh/lis2dh12 Support interrupt management for FIFO watermark Starting to share common code with other devices like lsm6dsm/lsm6dsl (acc/gyro) or new lis2mdl (mag) TODO: Add all embedded functions support (click, tap and so on) BUG=none BRANCH=master TEST=Tested on discovery BOARD with sensor connected on EC i2c master bus. Added motion sense task on discovery board task list, added gpio info in board configuration file and tested with motion sense console commands. Data for acc seems ok: can successfully change ODR and full scale range. Also FIFO and interrupt tested Device tested is lis2dh (lis2dh12 simply differs for low pin count but share the same registers) Change-Id: I16abeac3f139a604094b38d8d8b857a62c93a242 Signed-off-by: Mario Tesi <mario.tesi@st.com> Reviewed-on: https://chromium-review.googlesource.com/412700 Commit-Ready: mario tesi <mario.tesi@st.com> Tested-by: mario tesi <mario.tesi@st.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* cleanup: Remove charge_state_v1Sam Hurst2017-02-061-1/+0
| | | | | | | | | | | | | | | | All boards have been transitioned to charge_state_v2.c So charge_state_v1.c, HOOK_CHARGE_STATE_CHANGE, and CONFIG_CHARGER_TIMEOUT_HOURS can be removed BUG=chrome-os-partner:36272 TEST=make -j buildall BRANCH=none Change-Id: I3f20c5198ea75185f9894deb792575a1be31432a Reviewed-on: https://chromium-review.googlesource.com/435467 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: introduce malloc/free implementationVadim Bendebury2017-01-051-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | The new code allows to replace the existing one buffer at a time shared memory facility with a malloc/free implementation. A new configuration option is being provided (CONFIG_MALLOC). The names of functions allocating and freeing memory are not being changed to allow to switch between the two implementations seamlessly. A double linked list of buffers is used to keep track of free and allocated memory. During initialization the entire free memory block is considered a single free buffer. No allocations/frees are allowed from within interrupts. The control structures are protected by a semaphore, so allocate and free invocation could be blocking. A test is added which randomly allocates and frees memory, continuing until all branches in the allocate and free functions are taken. BUG=chrome-os-partner: TEST=make buildall -j succeeds, which includes testing the new malloc/free implementation. Change-Id: I5e71c0190c6c247ec73bb459f66a6d7a06e3d248 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/420466 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* charger_profile: Add common code for charger profile overrideVijay Hiremath2017-01-021-0/+1
| | | | | | | | | | | | | | | | | | | Added common code for charger profile override for fast charging. Fast charging configs can be defined in the respective board battery file and use the common code for imposing the custom data. BUG=chrome-os-partner:59393 BRANCH=none TEST=Enabled the config on Reef. Manually overrode the temperature and voltage. Observed correct charge profile config is selected for each tests. Change-Id: I075d271258470b98d38e4d5395d749469d3fd469 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/407928 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* als: Define CONFIG_ALS when HAS_TASK_ALS is present.Gwendal Grignou2016-12-281-1/+1
| | | | | | | | | | | | | | For oak, set a different list of task (no als, no accel) for compiling revision 4 or less. Fix GPIO include issue. BUG=chrome-os-partner:59423,chrome-os-partner:59084 TEST=compile for oak with board 4 and 5, tested on Reef. BRANCH=kevin,reef Change-Id: I09051a69cbad6d477a7b3bf9907f4c5c144b5136 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/424220 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add nvmem-backed key=value variable storageBill Richardson2016-12-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_FLASH_NVMEM option implements persistent, reliable storage regions in flash. This adds CONFIG_FLASH_NVMEM_VARS, which uses one of those storage regions for free-form variables. Refer to the comments in include/nvmem_vars.h and common/nvmem_vars.c for usage and implementation details. BUG=chrome-os-partner:61107 BRANCH=none TEST=make runtests This CL includes a number of new tests, specifically for this feature. No target boards use this feature yet so there's nothing to test on actual hardware, but the test/nvmem_vars executable includes console commands ("get", "set", "print") to try it out. Change-Id: I8597415dc3b00a1462f5b164eeb5073129030525 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/414194 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* i2c_passthru: fix virtual battery operationphilipchen2016-12-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | In some cases, the virtual battery code creates transactions that violate SB spec. One example: If the host command is structured as two messages - a write to 0x03 (reg addr), followed by two bytes of write data, the first byte of the second message (write data) will be sent to virtual_battery_read(), as if it were a reg read request. Let's do the following change for virtual battery: 1. Parse the command more carefully with state machines. 2. Support write caching for some critical registers. 3. Cache more attributes (0x03 and 0x0f). BUG=chrome-os-partner:59239, chromium:659819 BRANCH=none TEST='power_supply_info' works on kevin Change-Id: Icdeb12b21f0dc3c329f29b206b7b9395ca4c9998 Reviewed-on: https://chromium-review.googlesource.com/407987 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: flash: Use common code for SPI flash protect reg translationShawn Nematbakhsh2016-12-011-0/+1
| | | | | | | | | | | | | | | | | | | | | | Common code is more flexible and supports more parts, so delete the npcx-only register translation code. BUG=chrome-os-partner:60029 BRANCH=gru TEST=Manual on gru, run 'flashrom -p ec --wp-enable' and check that 0x28 gets written to SR1, which matches our desired 'protect botton 128KB', according to the datasheet. Also run 'flashrom -p ec --erase' then read back EC SPI contents, verify ROM is erased except for first 128KB region. Change-Id: I526401997ff7ec77f2a6047a4a9af74a671ed69a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/413228 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 43634d36d273887b1f2349c333a7b4b229a83365) Reviewed-on: https://chromium-review.googlesource.com/415498 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* accel: add accel driver for LSM6DSMMario Tesi2016-11-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | This add basics for acc and gyro sensor ST lsm6dsm Still need to add interrupt management for embedded functions and FIFO BUG=none BRANCH=master TEST=Tested on discovery BOARD with sensor connected on EC i2c master bus. Added motion sense task on discovery board task list, added gpio info in board configuration file and tested with motion sense console commands. Data for acc/gyro seems ok, can successfully change ODR and full scale range for acc and gyro. Change-Id: Ie50c8c0ee366994ed97f7ff3252633893b813ac2 Signed-off-by: Mario Tesi <mario.tesi@st.com> Reviewed-on: https://chromium-review.googlesource.com/406947 Commit-Ready: mario tesi <mario.tesi@st.com> Tested-by: mario tesi <mario.tesi@st.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
* common: Add tablet_mode APIGwendal Grignou2016-11-081-0/+1
| | | | | | | | | | | | | | | | | | | Simple API to set/get the tablet mode. It can be set via lid angle calculation or if a board has a dedicated HAL sensor/GPIO. Merged from glados branch, add MKBP switch support. BUG=chromium:606718 BRANCH=gru TEST=Check with Cave that both mode works. Reviewed-on: https://chromium-review.googlesource.com/402089 Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit c940f36ceabcf2425284001298f03ebdb4c3079e) Change-Id: I2ee5130f3e0a1307ec3ea543f7a32d66bc32b31d Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/404915 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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