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* Update license boilerplate text in source code filesstabilize-quickfix-15278.72.B-ishstabilize-quickfix-15183.78.B-ishstabilize-15446.B-ishstabilize-15439.B-ishstabilize-15432.B-ishstabilize-15429.B-ishstabilize-15415.B-ishstabilize-15395.B-ishstabilize-15393.48.B-ishstabilize-15381.B-ishstabilize-15364.B-ishstabilize-15361.B-ishstabilize-15359.B-ishstabilize-15359.58.B-ishstabilize-15359.50.B-ishstabilize-15359.45.B-ishstabilize-15335.B-ishstabilize-15329.59.B-ishstabilize-15329.44.B-ishstabilize-15317.B-ishstabilize-15301.B-ishstabilize-15300.B-ishstabilize-15278.64.B-ishstabilize-15251.B-ishstabilize-15245.B-ishstabilize-15236.66.B-ishstabilize-15208.B-ishstabilize-15207.B-ishstabilize-15185.B-ishstabilize-15185.7.B-ishstabilize-15183.82.B-ishstabilize-15183.69.B-ishstabilize-15183.14.B-ishstabilize-15174.B-ishstabilize-15167.B-ishstabilize-15129.B-ishstabilize-15122.B-ishstabilize-15120.B-ishstabilize-15117.86.B-ishstabilize-15117.48.B-ishstabilize-15117.111.B-ishrelease-R114-15437.B-ishrelease-R113-15393.B-ishrelease-R112-15359.B-ishrelease-R111-15329.B-ishrelease-R110-15278.B-ishrelease-R109-15237.B-ishrelease-R109-15236.B-ishrelease-R108-15183.B-ishrelease-R107-15117.B-ishishfirmware-ti50-prepvt-15315.B-ishfirmware-skyrim-15390.B-ishfirmware-skyrim-15369.B-ishfirmware-nissa-15217.B-ishfirmware-nissa-15217.45.B-ishfirmware-nissa-15217.126.B-ishfirmware-duplo-15151.B-ishfirmware-corsola-15194.B-ishfactory-trogdor-15210.B-ishfactory-skyrim-15384.B-ishfactory-nissa-15199.B-ishfactory-corsola-15197.B-ishfactory-corsola-15196.B-ishfactory-brya-15231.B-ishMike Frysinger2022-09-141-1/+1
| | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: I5b357b85ae9473a192b80983871bef4ae0d4b16f Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3893394 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-151-3/+4
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* common: separate VirtAddr and PhysAddr usageTzung-Bi Shih2020-12-161-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "VirtAddr" and "PhysAddr" are inconsistent for all ELF segments. Taking the following figure as an example: - 0x00000000 in the 1st segment is virtual address in SCP. - 0x50000000 in the 4th segment is physical address in AP. $ /opt/coreboot-sdk/bin/riscv64-elf-readelf -l build/asurada_scp/ec.obj Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x00000000 0x00000000 0x08198 0x08198 R E 0x1000 LOAD 0x009198 0x00008198 0x00057fff 0x00001 0x00001 RW 0x1000 LOAD 0x000db0 0x000ffdb0 0x000ffdb0 0x00000 0x00250 RW 0x1000 LOAD 0x00a000 0x50000000 0x50000000 0x00180 0x00180 R E 0x1000 Let "VirtAddr" for EC (SCP) view address; "PhysAddr" for AP view address. After the patch, the ELF's program header should be as the following. $ /opt/coreboot-sdk/bin/riscv64-elf-readelf -l build/asurada_scp/ec.obj Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x00000000 0x10500000 0x08198 0x08198 R E 0x1000 LOAD 0x009198 0x00008198 0x10557fff 0x00001 0x00001 RW 0x1000 LOAD 0x000db0 0x000ffdb0 0x105ffdb0 0x00000 0x00250 RW 0x1000 LOAD 0x00a000 0x10000000 0x50000000 0x00180 0x00180 R E 0x1000 BRANCH=none BUG=b:173753688 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I921d1e14b2ca1eb553ae4f7cd3dd83ac01749043 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2553996 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* common: fix IPI buffer vaddr locationTzung-Bi Shih2020-12-161-1/+1
| | | | | | | | | | | | | There should be an offset: CONFIG_PROGRAM_MEMORY_BASE. BRANCH=none BUG=b:173753688 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I6c84b8e12ad6b24ba969b48c7b70aba4684e1572 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2553995 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* common: embed IPI shared buffer address in ELFTzung-Bi Shih2020-11-171-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Embeds IPI shared buffer address in ELF. Creates a NOBITS segment for holding the address. E.g.: $ /opt/coreboot-sdk/bin/riscv64-elf-readelf -l build/asurada_scp/ec.obj Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align LOAD 0x001000 0x00000000 0x00000000 0x08180 0x08180 R E 0x1000 LOAD 0x009180 0x00008180 0x00057fff 0x00001 0x00001 RW 0x1000 LOAD 0x000db0 0x000ffdb0 0x000ffdb0 0x00000 0x00250 RW 0x1000 LOAD 0x00a000 0x50000000 0x50000000 0x00180 0x00180 R E 0x1000 Section to Segment mapping: Segment Sections... 00 .image.RW 01 .padding 02 .ipi_buffer 03 .image.RW.dram The .ipi_buffer is at 0x000ffdb0 and its size 0x00250. BRANCH=none BUG=b:156222508 BUG=b:156222459 TEST=make BOARD=asurada_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I574fafcfaa990da8c42388554945da6725e12264 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2534230 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* common: Format firmware_image linker scriptCraig Hesling2019-12-171-42/+47
| | | | | | | | | | | | | | | This is a cleanup/reformat of the linker script. This brings no functional change. BRANCH=none BUG=b:146083406 TEST=make buildall Change-Id: Ia86d7ed16ad3d12c26688b23e79ffb6f4bba9531 Signed-off-by: Craig Hesling <hesling@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1970812 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* mt_scp: Add support to store some code in DRAMNicolas Boichat2019-01-241-0/+9
| | | | | | | | | | | | | | | | | This allows to store specific code/data in a .dram region. This is used by mt_scp to run code off DRAM, as we plan to have more code than what can fit in SRAM. BRANCH=none BUG=b:122058243 TEST=make BOARD=kukui_scp -j objdump -x build/kukui_scp/ec.obj => Some code is loaded in DRAM TEST=Load kukui_scp, icachetest works Change-Id: Idbab809ba86cabe3b984944adc2781b37d2d544b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1391542
* npcx: Build RW_B and support sysjump to itDaisuke Nojiri2017-07-131-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows a board to include another RW image in ec.bin. The size of each copy is a quarter of the flash size on Fizz. BUG=b:38462249 BRANCH=none CQ-DEPEND=CL:568297 TEST=Run sysjump RW/A/B. Verify there is no size change by running make savesizes/newsizes. Run objdump -h build/fizz/ec.obj: Idx Name Size VMA LMA File off Algn 0 .image.RO 0001700c 10088000 10088000 00008000 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 1 .image.RO.key 00000340 1009f00c 100a7c40 0001f00c 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 2 .image.RW 00016ddc 1009f34c 100c8000 0001f34c 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 3 .image.RW.sign 000001b8 100b6128 100e7c00 00036128 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 4 .image.RW_B 00016ddc 100b62e0 100e8000 000362e0 2**0 CONTENTS, ALLOC, LOAD, READONLY, CODE 5 .image.RW_B.sign 000001b8 100cd0bc 10107c00 0004d0bc 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 6 .padding 00000001 100cd274 10107fff 0004d274 2**0 CONTENTS, ALLOC, LOAD, DATA 7 .ARM.attributes 00000014 00000000 00000000 0004d275 2**0 CONTENTS, READONLY Change-Id: Iaa687c1d7d704fec4cccfa127376c8db102267fa Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/557305 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Define load addresses using macrosDaisuke Nojiri2017-07-121-21/+25
| | | | | | | | | | | | | | | This patch defines load addresses of regions using macros to increase readability. BUG=none BRANCH=none TEST=Diff firmware_image.lds before and after the change. Change-Id: I24a13f4676b194efb748522f03c3134d1568f5ae Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/566940 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* common: Add support for flash with regions of different sizeRong Chang2017-06-021-3/+0
| | | | | | | | | | | | | Add support to handle devices with flash regions of different sizes. BRANCH=none TEST=compile BUG=b:38018926 Change-Id: I8f842abaa50de724df60dd7e19f9e97cb9660367 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/264031 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* common: Split rwsig parts from rsa.h headerNicolas Boichat2017-04-111-1/+1
| | | | | | | | | | | | | | | | We're going to add more rwsig-related functions, and adding them to rsa.h seems increasingly incorrect. BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I334c1774ce9a6ed8e219140f65ebe94d653e22d2 Reviewed-on: https://chromium-review.googlesource.com/468708 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common/rollback: Add support for rollback protectionNicolas Boichat2017-04-061-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement actual rollback protection. First, we add a new field in the version structure, which is an incrementing integer (we'll start by shipping images with version 0, and gradually increase the number as required). This allows us to release new versions of the EC without necessarily bumping the rollback protection. For the rollback protection block itself, it contains 2 sub-blocks of equal size (normally, 2k), that are individually erasable. The rollback code looks at both, and takes the most restrictive one to determine the desired rollback minimum version. The blocks are also allowed to be erased (full of 1's), in which case the rollback minimum version is assumed to be 0. We also add an FMAP entry, in case we later decide to allow the signer to increment the rollback version. Also note that, like any version_data struct change, this change breaks compatibility between old and new RO/RW. Follow-up code will take care of auto-updating the rollback block as required, and properly manage block protection. BRANCH=none BUG=b:35586219 TEST=Flash hammer rollbackinfo => 1 version 0 block, 1 empty block, RW verifies correctly. rollbackupdate 0; rollbackinfo => No change rollbackupdate 1; reboot => RO refuses to jump to RW rollbackupdate 2, 3, 4; rollbackinfo => Writes alternate between the 2 blocks. rollbackupdate 2 => Refuses to downgrade version Change-Id: Ia969afb481a93deb912b9153bdd95ace01ad8fa7 Reviewed-on: https://chromium-review.googlesource.com/452815 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* rwsig: Add support for rwsig image typesNicolas Boichat2017-02-171-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | usbpd1 futility image type is deprecated and should not be used for new designs. This adds proper support for rwsig image type. Key and signatures are added at linker stage step (futility cannot directly create such signed images). Thanks to VB21 header, rwsig.c can now tell how many bytes of the RW image need to be cryptographically verified, and ensure that the rest is blank (0xff). BRANCH=none BUG=chromium:690773 TEST=make BOARD=hammer; flash, RW image is verified correctly. TEST=make runtests -j TEST=For the rest of the tests: Change config option to CONFIG_RWSIG_TYPE_RWSIG TEST=make BOARD=hammer; flash, hammer still verifies correctly. TEST=cp build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig; futility sign --type rwsig --prikey build/hammer/key.vbprik2 \ build/hammer/ec.RW.bin diff build/hammer/ec.RW.bin build/hammer/ec.RW.bin.orig => Same file TEST=Add CONFIG_CMD_FLASH, flashwrite 0x1e000, reboot, EC does not verify anymore. TEST=dump_fmap build/hammer/ec.bin shows KEY_RO and SIG_RW at correct locations. Change-Id: I50ec828284c2d1eca67fa8cbddaf6f3b06606c82 Reviewed-on: https://chromium-review.googlesource.com/441546 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cr50: add ability to include two identical RW sections in the EC imageVadim Bendebury2015-12-091-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A typical EC image includes two similar in their functionality subsections, RO and RW. CR50 has a small RO subsection, all it does - detects a proper RW image to run and starts it up. To provide for reliable firmware updates, the CR50 image needs to include two RW sections, while the code is running from one RW subsection, the other one can be upgraded. This patch adds the ability to generate two identical RW sections, mapped half flash size apart, and include them into the resulting EC image. To keep things simple the previously existing RW section's name is not being changed, while the new (identical) RW section is named RW_B. Two configuration options need to be defined to enable building of the new image type: CONFIG_RW_B to enable the feature and CONFIG_RW_B_MEM_OFF to define where RW_B should be mapped into the flash. A new rule added to Makefile.rules allows to generate a different lds file from the same source (core/cortex-m/ec.lds.S) by defining a compile time variable to pick a different base address for the rewritable section, when RW_B is built. BRANCH=none BUG=chromium:43025 TEST=as follows: - make buildall -j still succeeds - verified that regular CR50 image starts successfully - modified chip/g/loader/main.c to launch RW_B first, re-built and re-run the image, observed on the console: vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv cr50 bootloader, 20151118_11218@80881, no USB, full crypto Valid image found at 0x00084000, jumping --- UART initialized after reboot --- [Reset cause: power-on] [Image: unknown, cr50_v1.1.4160-4c8a789-dirty 2015-12-07 18:54:27 vbendeb@eskimo.mtv.corp.google.com] [0.001148 Inits done] This FPGA image has no USB support Console is enabled; type HELP for help. > [0.002212 task 2 waiting for events...] ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ (note that the image base address is 0x840000, which is RW_B). Change-Id: Ia2f90d5e5b7a9f252ea3ecf3ff5babfad8a97444 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/316703 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: Fixed flash layout issue for npcxMulin Chao2015-09-211-1/+13
| | | | | | | | | | | | | | | | | | | | Fixed flash layout issue for npcx Modified drivers: 1. config_flash_layout.h: Fixed layout issue for npcx 2. flash_ec: add flashrom support for boards without JTAG in servo connector BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I0b9b679c52b8a8e2a26c278b5024d0350fb77338 Reviewed-on: https://chromium-review.googlesource.com/300392 Commit-Ready: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Fix npcx buildShawn Nematbakhsh2015-09-171-7/+1
| | | | | | | | | | | | | | | | | | | | The previous commits left npcx in a bad state. Change CONFIG_PROGRAM_MEMORY_BASE to point to the actual start of code memory and correct the linker file. This still results in a non-working npcx image (more changes forthcoming) but it does build. BUG=chrome-os-partner:23796 TEST=make clean; make buildall -j BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia300c5d18695dccd8d9fd9a6122cd7d30353adfa Reviewed-on: https://chromium-review.googlesource.com/300295 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-161-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* build-infr: Add support for shared RO library.Aseda Aboagye2015-07-171-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces the build infrastructure changes needed for creating a shared RO library. (libsharedobjs). The end goal is for the library to contain various objects that can be shared with both the RO and RW EC images. Now, there are 3 make goals: ro, rw, and libsharedobjs. In order for changes that are only specific to a single image (ie: RW only) to be applied correctly, the object files are now built separately for the RO, RW, shared objects library targets. NOTE: Certain EC targets are incompatible with this model due to the fact that only one image is present within flash at a time. BRANCH=none BUG=None TEST=make -j buildall tests TEST=make -j BOARD=cr50 xrefs TEST=make BOARD=samus dis TEST=Built samus EC image and compared that the final EC image was identical to the upstream version (except for the git SHAs & version strings). CQ-DEPEND=CL:285934 Change-Id: I8e67f089710be9c6d7017718109262394bdad2f5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/274079 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* nuc: Add SHI driver for arm-based platform in chip folder.Ian Chao2015-06-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* cleanup: Rename image geometry CONFIGsShawn Nematbakhsh2015-05-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Rename image geometry configs with a uniform naming scheme to make their purposes more clear. CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Set date / version strings to constants then `make buildall -j`. Verify that each ec.bin image is identical pre- and post-change. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd Reviewed-on: https://chromium-review.googlesource.com/270189 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* mec1322: lfw loader + RO/RW architectureDivya Jyothi2015-04-231-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mec1322 only has 96KB program memory, vs 256KB flash space on lm4.We no longer have enough program memory to load both RO and RW at boot. We'll want to implement a small loader program that will load either RO or RW from flash, and then jump to the loaded image. CONFIG_FW_INCLUDE_RO is enabled to include RO image into the build. pack.py script is altered to load the (lfw + R)O on boot. Software sync is not added.Distinguish between RO/RW is yet to be added. flash_ec is altered to support padding 0xFFs to 256k ec.bin to match the size of the SPI flash of the board. BUG=chromium:37510 BRANCH=None TEST=Make -j buildall,Verified ec.bin to be 256k. Verified RW image at offset 0h and (lfw + RO) at offset 2000h. On boot sysjump to lfw. lfw checks in shared SRAM (currently RO) and jumps to RO image. Change-Id: Ib9b114e2f24a615d5e5bd8b3803be621d1e5bd17 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265807 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
* Remove extra EAh at end of RW image.Gwendal Grignou2014-12-051-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EAh is used at the end marker for calculating hash in EC. The extra EAh make hash calculated by EC different from calculated in host by sha256sum for the RW image. The RO image is fine. Fix a comment, no A,B images anymore. BUG=chromium:438326 TEST=Check sha256sum is similar for Ryu EC image. On EC console > hash rw [28.740271 hash start 0x00010000 0x0000ea24] > [28.938875 hash done e2c40d0168ce4b20e8320438c7fc719d2188d7f88d9cb7ca694527b3f507e534] sha256sum of built image: sha256sum build/ryu_p1/ec.RW.flat e2c40d0168ce4b20e8320438c7fc719d2188d7f88d9cb7ca694527b3f507e534 build/ryu_p1/ec.RW.flat TEST=Check firmware upgrade still works: Using a modify version of coreboot with - ryu_p1 as main ec firmware - code to reenable SW sync: CL:233222 Ryu with an older image: cros_ec_init: CrosEC protocol v3 supported (128, 128) Google ChromeOS EC driver ready, id 'ryu_p1_v1.1.2570-942248a' Clearing the recovery request. VbEcSoftwareSync(devidx=0) EC hash:e2c40d0168ce4b20e8320438c7fc719d2188d7f88d9cb7ca694527b3f507e534 EC-RW hash address, size are 0x835b4ff8, 32. Hash = b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46 Expected hash:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46 EC-RW firmware address, size are 0x837f9374, 59924. VbEcSoftwareSync() - expected len = 59924 Computed hash of expected image:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46 VbEcSoftwareSync() updating EC-RW... VbEcSoftwareSync() jumping to EC-RW VbEcSoftwareSync() jumped to EC-RW VbEcSoftwareSync() in RW; done Check that at next reboot the firmware is not upgraded: cros_ec_init: CrosEC protocol v3 supported (128, 128) Google ChromeOS EC driver ready, id 'ryu_p1_no_version' Clearing the recovery request. VbEcSoftwareSync(devidx=0) EC hash:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46 EC-RW hash address, size are 0x835b4ff8, 32. Hash = b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46 Expected hash:b183cd58d668d3d42a7cec95f2dcbb8ddee33f6a42d873f4b78106f85d341b46 VbEcSoftwareSync() in EC-RW and it matches BRANCH=ToT Change-Id: I2db275a16b16fbcea95f53287e95104ba921593e Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232952 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Move core-specific toolchain configuration to core/ directoryVincent Palatin2013-11-071-2/+2
| | | | | | | | | | | | | | | | This is preparatory work to introduce a second core architecture. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23574 TEST=./util/make_all.sh Change-Id: Icae8a7e475a4ba2a13f0d8f95629e8498a5a61da Reviewed-on: https://chromium-review.googlesource.com/175419 Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Make a top-level config.h file to include sub-configsRandall Spangler2013-07-161-1/+0
| | | | | | | | | | | | | | | | | This file will soon contain the exhaustive list of all CONFIG defines and their descriptions. Chip-level configs are renamed to config_chip.h to avoid naming conflicts. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms Change-Id: I9e94146f5b4c016894bd3ae3d371c4b9f3f69afe Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62122 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Clean up flash section defines and increase lm4 image sizeRandall Spangler2013-06-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | The firmware defines had two almost-identical sets. Coalesce into one consistent set. Link had 256 KB flash, but only allowed 2 80KB images. Future LM4-based platforms (slippy/peppy/falco/etc) will now use the entire flash, with RO=124KB, pstate=4KB, RW=128KB. This matches what the STM32 platforms do, where pstate is contiguous with the RO firmware. No functional change to STM32-based platforms. BUG=chrome-os-partner:19176 BRANCH=none TEST=build all platforms and dump_fmap ec.bin. - stm32-based platforms should report RO=61440@0, RW=65536@0x10000 - link should report RO=81920@0, RW=81920@0x14000 - slippy should report RO=129024@0, RW=131072@0x20000 Change-Id: I20b1d95c16250d9a5d228ead06eef03d96548823 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56655
* Remove firmware BRandall Spangler2012-07-171-7/+0
| | | | | | | | | | BUG=chrome-os-partner:11449 TEST=build link, snow, bds; ectool reboot_ec cold to make sure enums line up Change-Id: Ie09db2080a00f1a7e2c05579b9b41ea5137c1af0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27658 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Rename A and B images to RW and RW_B, part 1Randall Spangler2012-07-171-4/+4
| | | | | | | | | | | | | | | | | | | All of our current EC configs have RO and a single RW image. Calling that image 'A' is confusing, particularly when combined with EC software sync (where the RW image is updated from either the A or B AP RW firmware). So, rename it. This changes all the build artifacts and constants. Internal EC commands and host commands still refer to A/B; that will be fixed in part 2. BUG=none TEST=build link, snow, bds Change-Id: Icfed4914745f0799bb71befb6a6563cfd8bc90ab Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27649 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Only one RW image is now the defaultRandall Spangler2012-06-261-1/+2
| | | | | | | | | | | | And if RW B isn't enabled, it's not even linked. BUG=chrome-os-partner:10881 TEST=on link, should be no B image, and 'sysjump B' should fail On BDS, still should be A and B images Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: Icb2af07881cc7e28b9b877f45824486a22fde8d7 Reviewed-on: https://gerrit.chromium.org/gerrit/26116
* Clean up linker scripts; detect out-of-flash problem.Bill Richardson2012-05-211-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | The VMA of the .data segment is in RAM, but we actually put it into FLASH. The linker doesn't notice if it runs out of flash, so it creates an invalid image. This adds an explicit check to be sure it all fits. It also refactors the region declarations to be more explicit. For vboot-enabled configurations, CONFIG_SECTION_* - describes the extent of flash for one entire image CONFIG_FW_* - the region within the SECTION for the firmware only CONFIG_VBLOCK_* - the region within the RW SECTIONs for the vblocks CONFIG_VBOOT_ROOTKEY - the region within the RO SECTION for the root key Look at chip/lm4/config.h for the best example. BUG=chrome-os-partner:9839 TEST=manual Build it, run it. Change-Id: I3c652e82d58a5328115cc750c80ecba6a3fd99a3 Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* Fix flash base in full image ELFVincent Palatin2012-05-191-4/+4
| | | | | | | | | | | | | | | When the flash base address is non null (e.g. stm32), it's nice to have the full ELF image (including the 3 copies) at the right address. This doesn't change anything to the final .bin image but allow to load directly the .obj with tools which handle ELF format. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=Flash ec.obj on a Snow board using the ST-Link JTAG over GDB. Change-Id: I51a6d9c00b359c6204bd51b30ee7a4fec362d88e
* Mark end of each RW firmware image so we can find it.Bill Richardson2012-05-081-0/+2
| | | | | | | | | | | | | | This just adds a single byte to the end of the RW firmware, so that we can scan backwards from the end of the reserved block, skipping 0xff until we find the actual firmware size. We need this so we can resign existing firmware images without either signing a bunch of padding or forgetting to sign a trailing 0xff that might be important. BUG=chrome-os-partner:7459 TEST=none Change-Id: If5cadb4d58c1bce39f66815c328ffd18cc3d444b Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* Add basic FMAP to EC firmware image.Bill Richardson2012-05-011-3/+7
| | | | | | | | | | | | | | | | | | | | | | | This is very basic, so you can only rely on RO_SECTION, RW_SECTION_A, and RW_SECTION_B for now. We'll fill in more regions as we add vboot stuff. Still, you should be able to do things like this: flashrom -p internal:bus=lpc -r ec.bin flashrom -p internal:bus=lpc -w ec.bin -i RW_SECTION:ec.B.flat BUG=chrome-os-partner:8198 TEST=manual Build the image, look for the FMAP in it. cd src/platform/ec make BOARD=link dump_fmap ./build/link/ec.bin Change-Id: I0adbbfb8e975faae805bda271873fcef46590cf4 Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* Temporarily remove image RW.B due to code size.Vic Yang2012-02-161-0/+7
| | | | | | | | | | | | | | | To accomodate our growing code, image RW.B is removed so that RO and RW.A can both have 60K space. This is just a temporary solution. Add RW.B back when we have enough space for all three images. Also add license header to firmware_image.lds.S so that repo does not complain about it. BUG=chrome-os-partner:8079 TEST=build image and run on proto-0. Change-Id: I85b723f3e645c12fd89b189263ca44d58c4621eb Signed-off-by: Vic Yang <victoryang@chromium.org>
* Initial sources import 3/3Vincent Palatin2011-12-071-0/+23
source files mainly done by Vincent. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Change-Id: Ic2d1becd400c9b4b4a14d4a243af1bdf77d9c1e2
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