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* core: Allow .bss and .data sections in DRAMNicolas Boichat2019-02-181-1/+10
| | | | | | | | | | | | | | | | | We manually copy other .data from the original section on boot, and clear DRAM .bss. This way, a single object file (or archive) can be moved fully to DRAM. BRANCH=none BUG=b:122058243 TEST=With next CL, dram_test works Change-Id: I1a434bbd8a4135d16b3f49b0d1b75b96506e3e24 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1445652 Reviewed-by: Jett Rink <jettrink@chromium.org>
* lpc/espi: convert remaning CONFIG_LPC to CONFIG_HOSTCMD_X86Jett Rink2018-05-221-1/+1
| | | | | | | | | | | | | | We have converted all LPC-only configs to HOSTCMD_LPC so the remaining CONFIG_LPC defines represent the common case. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Iba9a48f2cab12fadd0d9ab8eab0d5d5476eab238 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067503 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fizz: Execute PMIC reset before vboot_mainDaisuke Nojiri2018-02-081-0/+6
| | | | | | | | | | | | | | | | | | | When AP requests cold reboot, currently EC does not perform PMIC reset because chipset_handle_reboot is executed only after EC jumps to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME events because power rails do not cycle. This patch will make EC execute PMIC reset to before vboot_main. BUG=b:73093795 BRANCH=none TEST=reboot, reboot ap-off, verify USB ports are powered after transitionining to dev mode. Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/908094 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Enable PD communication in RO for external displayDaisuke Nojiri2018-02-031-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | This patch makes EC enable PD communication if it's running in manual recovery mode. This is required to show recovery screen on a type-c monitor. This patch also makes EC-EFS ignore power availability. It will make EC verify & jump to RW even if power is sourced by a barrel jack adapter. This should allow depthcharge to show screens (e.g. broken, warning) on a type-c monitor. BUG=b:72387533 BRANCH=none TEST=On Fizz with type-c monitor, verify - Recovery screen is displayed in manual recovery mode. - Critical update screen is displayed in normal mode. - Warning screen is displayed in developer mode. Monitors tested: Dingdong, Dell S2718D Change-Id: Ib53e02d1e5c0f5b2d96d9a02fd33022f92e52b04 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/898346 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* buttons: Make buttons[] common.Aseda Aboagye2017-11-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Nearly every board had a buttons array defined in which its contents had the standard volume buttons. This commit creates a single common buttons array that can contain the standard volume buttons and recovery buttons. If a board has volume up and down buttons, they can simply define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with the standard definition. The buttons are active low and have a 30 ms debounce period. Similiarly, if a board has a dedicated recovery button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the buttons array with a recovery button. BUG=chromium:783371 BRANCH=None TEST=make -j buildall. TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume buttons still work. Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/773794 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* host_event: Perform lpc_init_mask before keyboard/button initFurquan Shaikh2017-10-241-0/+11
| | | | | | | | | | | | | | | | | | | | | | keyboard/button init are responsible for checking if user requested manual recovery. However, by this time, hook init is not run and hence host event set operation for manual recovery is dropped. This change adds a call to lpc_init_mask before keyboard/button init operations are performed. BUG=b:68189465 BRANCH=None TEST=Verified that manual recovery works fine. Recovery using software command works too: reboot ap-off hostevent set 0x4000 powerb Change-Id: I15cb648d4b253a523293c7ab2cd3e8e08e31a763 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/735799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Remove 'ryu' boardShawn Nematbakhsh2017-09-111-10/+0
| | | | | | | | | | | | | | | Remove 'ryu' and related ryu-only code. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: I19b966ea6964a7ed083724f7de80ae192235a406 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656314 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Remove jtag_pre_init()Shawn Nematbakhsh2017-09-071-3/+0
| | | | | | | | | | | | | | | Use our newly-created chip_pre_init() for doing JTAG initialization. BUG=chromium:747629 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic5771895a214a9f1aa9bd289eef576f52adf973f Reviewed-on: https://chromium-review.googlesource.com/629676 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* EFS: Rename CONFIG_VBOOT_EC to _EFSDaisuke Nojiri2017-08-291-4/+3
| | | | | | | | | | | | | | This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: Move chip pre-init to chip_pre_init()Randall Spangler2017-08-241-0/+4
| | | | | | | | | | | | | | | | | | | | Currently, chip/g uses jtag_pre_init() to do some chip pre-initialization that isn't actually related to JTAG. This has been harmless, but it's currently the only chip which actually does "JTAG" pre-init, and we'd like to get rid of that. So, move that functionality to a new optional chip_pre_init() function. BUG=chromium:747629 BRANCH=cr50 TEST=make buildall boot cr50 make all dis; confirm chip_pre_init() is called early in <main> Change-Id: I3cae0747ab0c3cc974fce9f108947207b38e035f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/629876 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* g: slightly optimize boot on USB resumeVincent Palatin2017-08-021-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Save a small amount of time when the USB resume is making the chip boot from deep-sleep by removing the verbose serial traces in main and increasing the usb initialization priority. This brings us from borderline timings wrt the USB specification to a reasonable margin. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:38160821 TEST=run on hotelgolf, go to deep-sleep on USB-suspend. On USB resume, measure the time from CPU boot to the end of usb_init using the CPU cycle count. We are shaving 1.3ms. Change-Id: Ia5bf69c0ca26748dec59a87f3908a5fe68296b36 Reviewed-on: https://chromium-review.googlesource.com/563206 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* vboot: Add vboot for EC by ECDaisuke Nojiri2017-06-281-0/+2
| | | | | | | | | | | | | | | | | This patch adds vboot for EC by EC (vboot EC) for x86 systems. When ec is transitioning s5->s3, it checks the power supply is enough to boot AP or not. If not, it runs other checks and may finally validate and jump to a RW image. BUG=b:38462249 BRANCH=none TEST=Boot Fizz on barrel jack and type-c charger. Change-Id: I5988b0595976370c5303c45541702ae89d86fc97 Reviewed-on: https://chromium-review.googlesource.com/518254 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* rwsig: do not jump if reset source is hard pin resetWei-Ning Huang2017-04-271-3/+15
| | | | | | | | | | | | | | | | | | | According to the new MCU secure update model, EC should wait for host if reset source is reset-pin. BRANCH=none BUG=b:37584134 TEST=on rose, toggle reset pin from host. EC should stay in RO, showing [0.426089 Hard pin-reset detected, disable RW jump] in console. Change-Id: Ie1908cb0744773e2e3ca8b3d8c627b8a9ef4567f Reviewed-on: https://chromium-review.googlesource.com/485199 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* rwsig: Make it possible to run as a taskNicolas Boichat2017-04-111-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | (Optionally) split rwsig verification into a separate task. This allows us to initialize other components (e.g. USB) while the verification is in progress, speeding up the boot process to active USB in RO case. After CONFIG_RWSIG_JUMP_TIMEOUT, the EC will jump to the RW section if no action is taken by the AP (such as a forced request to jump to RW, or starting an update). Note: This comes with a ~36ms boot time regression, as other code gets to run before verification starts. BRANCH=none BUG=b:35587171 TEST=Flash, board boots to RW after 1s TEST=Change jump timeout to 5s, add 5s delay in check_signature, add console command to manually abort/continue rwsig verification. 'rwsig continue' works => Board jumps to RW after check_signature is completed (or immediately while waiting for timeout) 'rwsig abort' works => Board does not jump to RW. Change-Id: Ica5732b9298bb4d3b743cae2ba78df259db915ef Reviewed-on: https://chromium-review.googlesource.com/468709 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Split rwsig parts from rsa.h headerNicolas Boichat2017-04-111-1/+1
| | | | | | | | | | | | | | | | We're going to add more rwsig-related functions, and adding them to rsa.h seems increasingly incorrect. BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I334c1774ce9a6ed8e219140f65ebe94d653e22d2 Reviewed-on: https://chromium-review.googlesource.com/468708 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* button: Check volume up/down status and set recovery modeNicolas Boichat2017-01-201-0/+4
| | | | | | | | | | | | | | Add support for entering recovery mode using volume up/down keys. BRANCH=none BUG=chrome-os-partner:61930 TEST=Press Power+Volume Up+Volume Down, poppy enters recovery Change-Id: Id40a144e9b430cfb9dfd47048e9e96d598bc3db8 Reviewed-on: https://chromium-review.googlesource.com/428530 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix various misspellings in commentsMartin Roth2016-11-151-1/+1
| | | | | | | | | | | | | No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* g: CONFIG_FLASH should be optionalBill Richardson2016-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The application may need to read/write/erase the flash memory, but we not want console users to do so. This CL adds CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH to be undefined while still providing the chip-specific flash_physical_* accessor functions. There aren't many board.h files that needed changes, since CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH. BUG=chrome-os-partner:57408 BRANCH=none TEST=make buildall; try on Gru with and without CR50_DEV=1 See that it still boots, updates, wipes, restores, etc. without linking common/flash.o in the production image; and that the flash commands are still there in the dev build. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93 Reviewed-on: https://chromium-review.googlesource.com/391188 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: enable case closed debugMary Ruthven2016-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a ccd console command to control the usb endpoints. The uart console command is moved into this command so 'ccd uart [enable|disable]' controls the AP and EC TX signals instead of the 'uart' console command. CCD can be enabled using 'ccd enable'. This switches the PHY used by the USB controller to be the external PHY. Changing the PHY exposes the cr50, AP, and EC consoles as well as the upgrading mechanisms for the AP, EC and cr50. The AP and EC consoles will be read only until 'ccd uart enable' is called. Cr50 can be updated using the usb upgrade endpoint. The EC and AP can be updated using the USB SPI endpoint. When CCD is disabled the usb controller will switch to using the AP PHY. None of the endpoints will be visible to the host. The USB SPI endpoint can be used to flash the EC or AP using 'flashrom -p raiden_debug_spi:target=[AP|EC]'. If CCD is not enabled running flashrom using the raiden_debug_spi programmer will fail. Cr50 will not forward the commands to the external AP or EC ROM, so flashrom will not be able to find the chip. The UART TX signals are now controlled by the 'ccd uart' console command instead of the 'uart' console command. The UART TX is enabled separately from CCD, because we want to be able to enable CCD while servo is connected, and having the cr50 UART TX pins wired directly to the Servo TX lines could damage both devices. The AP and EC consoles are be read only until 'ccd uart enable' is called. 'ccd uart disable' disconnects the AP and EC TX pins from the UART peripheral. When RDD becomes reliable on cr50, ccd_set_mode will select the PHY being used by the g chip USB controller. BUG=chrome-os-partner:49960,chrome-os-partner:52281 BRANCH=none TEST=manual TEST SERVO power cycle the DUT connect servo and check that the AP and EC consoles still work check that both the AP and EC can be flashed using servo. TEST SUZY Q Attach Suzy Q Connect to the all three consoles. Check that the cr50 console is in read-write mode and the EC and AP consoles are read only. Attach Servo. Verify all of the servo functionality described above still works with suzy q attached and ccd enabled. Disconnect Servo. run 'ccd uart enable' on the cr50 console and check both the AP and EC consoles can be written to. Check that the AP and EC can be programmed using the raiden_debug_spi programmer. Change-Id: I96db2a72fc95086871c9e4c778c19ebd01efb851 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342563
* system: Add support to reclaim space from loader.Aseda Aboagye2015-10-131-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain ECs which cannot load both the RO and RW images into memory simultaneously have a little firmware (LFW) loader that is loaded into the beginning of the program memory. This loader is responsible for loading the RO/RW images, however once we begin executing code from main(), the loader has already completed it's purpose. We can reuse this space by allocating portions of the .bss section here. This currently saves us 3k for mec1322. This section is .bss.slow. To use this feature simply define the following config option in board.h. #define CONFIG_REPLACE_LOADER_WITH_BSS_SLOW In some cases, such as the mec1322, this region of RAM is optimized for code and not data. Therefore, ideally infrequently used data should go into this region. BUG=chrome-os-partner:46056 BUG=chrome-os-partner:46063 BRANCH=None TEST=Flash GLaDOS; sysjump rw; Verify that we are in rw; sysjump ro; Verify we are back in ro. TEST=Build GLaDOS, check output memory map for LDR_REGION and .bss.slow section. TEST=make -j buildall tests Change-Id: I5b95cacc211278cf780a857b5a2ecfc1a0a28c45 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305254 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* eoption: Remove unused eeprom option storage codeAnton Staaf2015-09-081-4/+0
| | | | | | | | | | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I2174a904df160d19d47f1aa2d053349356cb4291 Reviewed-on: https://chromium-review.googlesource.com/297805 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hooks: Move HOOK_INIT to after task switching.Aseda Aboagye2015-07-131-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | This commit changes the way in which tasks are started. Instead of having all tasks marked as ready to run upon initialization, only the hooks task is marked as ready to run. HOOK_INITs are now run at the beginning of the hooks task. After the HOOK_INITs, the hooks task calls back to enable the rest of the tasks, reschedules, and proceeds as usual. This also allows the removal of checks for task_start_called(). BUG=chrome-os-partner:27226 BRANCH=None TEST=Built and flash EC image for samus and verified that EC boot was successful as well as AP boot. Additionally, verified that charging, keyboard, tap-for-battery were all still functional. TEST=make -j buildall tests Change-Id: Iea53670222c803c2985e9c86c96974386888a4fe Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/283657 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* Add option to enable GCC LTOVincent Palatin2015-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the flash footprint of the firmware. Add additional protection to some functions/data to avoid removal by the linker when their usage is not obvious. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall (with and without LTO enable on all boards) Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059 Reviewed-on: https://chromium-review.googlesource.com/271291 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* CCD: Switch PD_NO_DEBUG logic to use system_is_lockedAnton Staaf2015-04-131-10/+5
| | | | | | | | | | | | | | | | | | | | The system_is_locked function encompases the required checks for asserting PD_NO_DEBUG. It also supports forcing a system to be unlocked at build time, as well as handling systems without flash. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I676acb5a2ae169f9739a19910a760706f69f5b7b Reviewed-on: https://chromium-review.googlesource.com/265463 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* Ryu: Add PD_NO_DEBUG logicAnton Staaf2015-04-131-0/+15
| | | | | | | | | | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=chromium:470299 TEST=make buildall -j Change-Id: I79f831c8a0b581561472470986b86c77b7f824a1 Reviewed-on: https://chromium-review.googlesource.com/264796 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* Add RW firmware signature verification for common runtimeVincent Palatin2014-12-011-0/+9
| | | | | | | | | | | | | | | | | | For accessories without software-sync mechanism, add the option to do a RSA-based signature verification of the Read-Write firmware. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:31192 TEST=enable the configuration on Fruitpie and see the RW firmware validated and jump to. Tried with good and bad RW images. Change-Id: I3c886c2cbe17ca9543e19bf8599061c3f9751d4f Reviewed-on: https://chromium-review.googlesource.com/229594 Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org>
* Add CONFIG_BRINGUP option to help debug signals for bringupBill Richardson2014-06-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When this option is configured, two changes take place. First, the AP doesn't power on by default when the EC reboots. To boot it, you can run the "powerbtn" command, or poke the power button manually, or any of the normal things. Second, we watch for power-related signal changes (anything that's connected to the power_signal_interrupt() function) and keep track of them as they happen. After a second with no further changes, we print the time and value of each change. For example: [19.939212 Port 80: 0x29] [19.967971 HC 0x23] [19.976236 Port 80: 0x3a] [19.995700 HC 0x87] [20.567884 Port 80: 0x73] 11 signal changes: 19.638241 +0.000000 PCH_SLP_SUS_L => 1 19.654378 +0.016137 PCH_SLP_S5_L => 1 19.654457 +0.000079 PCH_SLP_A_L => 1 19.654535 +0.000078 PCH_SLP_S3_L => 1 19.654587 +0.000052 PCH_SLP_S4_L => 1 19.659630 +0.005043 PGOOD_1_5V_DDR => 1 19.663199 +0.003569 PGOOD_1_5V_PCH => 1 19.664751 +0.001552 PGOOD_1_8VS => 1 19.668735 +0.003984 PGOOD_VCCP => 1 19.671883 +0.003148 PGOOD_VCCSA => 1 19.868406 +0.196523 PGOOD_CPU_CORE => 1 [21.908551 Port 80: 0xf0] [21.908855 HC 0x48] BUG=none BRANCH=ToT TEST=manual Build with CONFIG_BRINGUP, notice those two changes. Change-Id: I55fd2021a0eae7dbfd1aaf5d93971f65bf2367b9 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/202574 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Add cprints() and ccprints()Vic Yang2014-05-211-2/+3
| | | | | | | | | | | | | | | | | | | | | Our code base contains a lot of debug messages in this pattern: CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n") The strings are taking up spaces in the EC binaries, so let's refactor this by adding cprints() and ccprints(). cprints() is just like cprintf(), except that it adds the brackets and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...) This saves us hundreds of bytes in EC binaries. BUG=chromium:374575 TEST=Build and check flash size BRANCH=None Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200490 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Initalize DMA before UARTRandall Spangler2013-09-101-0/+6
| | | | | | | | | | | | | | This is in preparation for enabling DMA-based UART transfers, to improve UART performance on STM32. BUG=chrome-os-partner:20485 BRANCH=none TEST=Boot pit. Host commands should still be received; this verifies DMA is still operational. Change-Id: Ibc3b2e2cd187547eb61b85e4a086704accd7f2fb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168810
* Introducing MPU module for Cortex-M3Daisuke Nojiri2013-09-051-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Preventing instruction fetch from RAM for Link except iram.text, which is used for hibernation. Stm32 on Snow does not support MPU. Tested on Link using commands 'crash nxtext/nxdata/nxstack', which run code from .iram.text, .data section, and the stack, respectively: ... RAM locked. Exclusion 20005980-200059a0 ... > crash nxtext Running from 20005984 > crash nxdata === PROCESS EXCEPTION: 04 ====== xPSR: 61000000 === r0 :00000000 r1 :0000dff2 r2 :00000005 r3 :0000086d r4 :00000000 r5 :00000032 r6 :2000544c r7 :00000000 r8 :00000000 r9 :20005456 r10:00000000 r11:00000000 r12:20005961 sp :20002748 lr :000008d7 pc :20005960 Instruction access violation mmfs = 1, shcsr = 70001, hfsr = 0, dfsr = 0 =========== Process Stack Contents =========== 200027b0: 0000086d 00000002 0000d504 00009f27 200027c0: 2000544c 20005452 00000000 00000000 200027d0: 00000000 00000000 00000000 00000000 200027e0: 00000000 00000000 00000000 00000cbb Rebooting... > crash nxstack === PROCESS EXCEPTION: 04 ====== xPSR: 20000200 === r0 :00000070 r1 :00000047 r2 :00000000 r3 :200027a8 r4 :00000000 r5 :00000001 r6 :2000544c r7 :00000000 r8 :00000000 r9 :20005456 r10:00000000 r11:00000000 r12:00000002 sp :20002740 lr :00000913 pc :200027ac Instruction access violation mmfs = 1, shcsr = 70001, hfsr = 0, dfsr = 0 =========== Process Stack Contents =========== 200027ac: 00000070 00000047 00000002 0000d57c 200027bc: 00009f9f 2000544c 20005452 00000000 200027cc: 00000000 00000000 00000000 00000000 200027dc: 00000000 00000000 00000000 00000000 Rebooting... BUG=chrome-os-partner:16904 BRANCH=master TEST=stated above Change-Id: I7c6593c527f29609442f33550f9d16755f32297c Signed-off-by: Daisuke Nojiri <dnojiri@google.com> Reviewed-on: https://chromium-review.googlesource.com/51337 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Pthread-based emulator for unit testingstabilize-4100.38.BVic Yang2013-05-071-1/+1
| | | | | | | | | | | | | | This is the first version of pthread-based RTOS emulator. With this, we will be able to test high-level modules entirely on the host machine. BUG=chrome-os-partner:19325 TEST='make runtests' and see tests passing. BRANCH=None Change-Id: I1f5fcd76aa84bdb46c7d35c5e60ae5d92fd3a319 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49954 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Replace generated CONFIG_TASK_ macros with HAS_TASK_Bill Richardson2013-04-241-1/+1
| | | | | | | | | | | | | | | CONFIG_ macros should be set directly. Expanding the task names in the same way made it difficult to tell what was a configuration choice and what was due to changes in ec.tasklist BUG=chrome-os-partner:18343 TEST=build all, run link BRANCH=none Change-Id: Ib82e34f974238ee2dd216f33b701b6f4c6a4f1f1 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49098 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Clean up board configurationRandall Spangler2013-04-051-3/+6
| | | | | | | | | | | | | | | | | Board configuration interfaces are now defined in board_config.h, not in every board.h file. Tidied /alphabetized CONFIG defines. No functional changes, just rearranging code. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all targets Change-Id: I6196591784f8fa9ce6dfccd31891b679fb200063 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/47419
* Add support for calling deferred functionsRandall Spangler2013-04-021-6/+2
| | | | | | | | | | | | | | | | | This is a cleaner way of deferring work from interrupt-time to task-time without requiring a task for each module which needs this. Replaces/supersedes delayed hook notification, which didn't scale well (since every function would have needed to be its own hook type). BUG=chrome-os-partner:18473 BRANCH=none TEST=boot system. plug/unplug AC power; notifies the host properly Change-Id: I50263fe1ce37e74c1ef8db3671379098997102ed Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/46953 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Move files in preparation for merging keyboard_scan modulesRandall Spangler2013-03-271-2/+1
| | | | | | | | | | | | | | | | | | This is part one of a series to merge the keyboard scan interface to be common across all platforms. This change just moves and renames files and APIs and removes some read code, and sets up protocol-specific CONFIG options. It makes the next CL which actually merges keyboard scanning easier to parse. BUG=chrome-os-partner:18360 BRANCH=none TEST=compile all boards; test keyboard on spring and link Change-Id: I815a40aae4e5d5f333b8501aff9656080533d913 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/46549 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Watchdog is reloaded by HOOK_TICK, not its own taskRandall Spangler2012-10-301-1/+1
| | | | | | | | | | | | | This reduces memory footprint. BUG=chrome-os-partner:15714 BRANCH=none TEST=system still boots; 'waitms 1500' prints watchdog error dump Change-Id: Ieb0248a34655514b03d919cc36c2b369691da716 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36937 Reviewed-by: Simon Glass <sjg@chromium.org>
* Clean up UART moduleRandall Spangler2012-10-301-12/+16
| | | | | | | | | | | | | | And change some direct uart_printf()/uart_puts() output to console output methods instead. Disable unused comxtest debug command. No other functional changes. BUG=chrome-os-partner:15579 BRANCH=none TEST=boot system; should still see debug output with reset flags Change-Id: I57fe6bb781a1ba7884afa6d090b74a92f45a53cc Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36835
* Hook functions no longer return valuesRandall Spangler2012-10-231-1/+1
| | | | | | | | | | | | | | | Previously, all hook functions returned EC_SUCCESS, which was meaningless because nothing ever looked at the return value. Changing the return value to void saves ~100 bytes of code size and an equal amount of source code size. BUG=none BRANCH=none TEST=code still builds; link still boots Change-Id: I2a636339894e5a804831244967a9c9d134df7d13 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36372
* Add CONFIG_CONFIGURE_BOARD_LATE for late board initSimon Glass2012-08-271-0/+3
| | | | | | | | | | | | | | | | It is useful to be able to perform some board init after GPIOs are set up. When defined, configure_board_late() will be called after GPIOs are ready. BUG=chrome-os-partner:13064 BRANCH=snow,link TEST=manual build and boot on snow with later changes. See the AC power GPIO does not change when un/plugging power. Change-Id: Idc56c0acde9f7bd46b4379731b973d1fce760b3f Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/31303
* Enable PLL only briefly during ADC initRandall Spangler2012-08-091-5/+1
| | | | | | | | | | | | | | | | | | It was previously only enabled for 1500us during boot, but in a way that triggered a needless round of notifications to other modules. This is cleaner. This also fixes adc_init() not initializing the task IDs to wake when interrupts come in, and removes some unneeded code from other init functions. BUG=chrome-os-partner:12472 TEST=boot system and run adc command. Should still provide reasonable data. Change-Id: I9ae5857d988c727caf5d53f551a2f12b30974c0f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/29806 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Remove signature-based vboot supportRandall Spangler2012-08-071-20/+0
| | | | | | | | | | | | | | | | | | | | Superseded by EC software sync (hash-based). Sig-based vboot was correctly implemented, but ended up being too slow to be useful given the limited processing power of the EC chips, and we also couldn't come up with a manageable way to handle A/B autoupdate of signed EC firmware. This change and an associated vboot_reference change shrinks the EC binary by ~2KB. BUG=chrome-os-partner:11232 TEST=build link,snow; boot link and check that 'hash' command still works. Change-Id: I3f03ae2d0a4030977826980d6ec5613181e154c2 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/29496 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Flash pre-init reboots if it needs to clear protection registersRandall Spangler2012-07-161-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:11171 TEST=manual 1. Clear some of the writable-bits in the flash registers > ww 0x400fe40c 0xffff1234 write 0x400fe40c = 0xffff1234 > rw 0x400fe40c read 0x400fe40c = 0xffff1234 2. Reset using power+refresh 3. Register should be clear again > rw 0x400fe40c read 0x400fe40c = 0xffffffff 4. Sysinfo should indicate reset-pin reason AND hard-reset reason > sysinfo Reset flags: 0x0000000a (reset-pin power-on) 5. Reset using power+refresh 6. Sysinfo should indicate reset-pin reason only > sysinfo Reset flags: 0x00000002 (reset-pin) 7. Clear writable-bits again > ww 0x400fe40c 0xffff1234 write 0x400fe40c = 0xffff1234 8. Jump to another image. This should NOT trigger a hard reset. > sysjump A > sysinfo Reset flags: 0x00000402 (reset-pin sysjump) Change-Id: Ie1d6af2acc68217bb82faae464798ee85d63d1ea Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27540 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Refactor reset reasonsRandall Spangler2012-07-161-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Reasons are really bitflags, not a single reason. This will make it easier to implement flash protection on LM4, where hibernate is a subset of power-on reasons. Also added some additional flags we pass in a hibernate register so... 1) We don't recognize spurious RTC wake reasons 2) Hard reset via system_reset(1) is detected as a hard reset, not a RTC wake BUG=chrome-os-partner:11368 TEST=manual 1. Keyboard reset = power-on reset-pin 2. Pull battery = power-on 3. reboot = soft 4. reboot hard = power-on rtc-alarm 5. hibernate 10 then push power button = power-on wake-pin 6. reboot 3 sec later = soft 7. hibernate 1 = power-on rtc-alarm Change-Id: Icbbdbcf6dfd13c8a6a4f80a23f64cebebbfba26e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27417
* Only disable sysjump in main if we're doing signature-based verified bootRandall Spangler2012-07-091-1/+1
| | | | | | | | | | | | | | | | | | EC software sync still needs to be able to sysjump later after the AP decides which image the EC should be running. BUG=chrome-os-partner:11087 TEST=manual sysjump A sysjump RO sysjump A sysjump RO Change-Id: I74eaf10dacf6eaa6aeabae2ff3b21ad387517605 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/26896 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Strip out vboot signature code and stay in RO for linkRandall Spangler2012-06-261-26/+48
| | | | | | | | | | | | | | BUG=chrome-os-partner:10880 TEST=boot EC; should stay in RO and not do signature check (verify via debug console output) Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: I831aa91f8273bc7fb1a624cf36d9f21d52d8f3d8 Reviewed-on: https://gerrit.chromium.org/gerrit/26115 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Tested-by: Randall Spangler <rspangler@chromium.org> Commit-Ready: Randall Spangler <rspangler@chromium.org>
* Enable checking for divide by 0 and alignment faultsSimon Glass2012-06-211-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These likely indicate errors, so we shold trap them. Possibly this should be reconsidered for production. BUG=chrome-os-partner:10148 TEST=manual: build on all boards build and boot on snow with a special rw command containing a division by 0. See that it is trapped: > rw 0 === EXCEPTION: 03 ====== xPSR: 01000000 =========== r0 :0000000b r1 :08005eba r2 :00000000 r3 :20001048 r4 :00000000 r5 :08004fd4 r6 :08004f8c r7 :200012a8 r8 :08004fd4 r9 :00000002 r10:00000000 r11:00000000 r12:00000000 sp :200009a0 lr :08002861 pc :0800368a Divide by 0, Forced hard fault, Vector catch mmfs = 02000000, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 Turn off the cpu_init() setup, and see that it is ignored. > rw 0 read 0x0 = 0x00000000 > Similarly, try an unaligned access with the rw command with this enabled: > rw 1 === EXCEPTION: 03 ====== xPSR: 01000000 =========== r0 :0000000b r1 :00000041 r2 :00000001 r3 :200012ac r4 :00000000 r5 :08004fd4 r6 :08004f8c r7 :200012a8 r8 :08004fd4 r9 :00000002 r10:00000000 r11:00000000 r12:00000000 sp :200009a0 lr :08002861 pc :08003686 Unaligned, Forced hard fault, Vector catch mmfs = 01000000, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008 but disabled it works: > rw 1 read 0x1 = 0x5d200010 > Change-Id: Id84f737301e467b3b56a7ac22790e55d672df7d8 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/25410 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Unify the watchdog API over stm32 and lm4Simon Glass2012-06-051-1/+1
| | | | | | | | | | | | | | | | Use the same prototype for watchdog_init() everywhere. One version takes a parameters and one doesn't. We don't need the parameter since we have a #define. Tidy this up. Also move watchdog defines into watchdog.h. BUG=chrome-os-partner:10145 TEST=build for all boards Change-Id: I38ae63d7cc137b93017c850e767703d5f90f56ad Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/24394 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add system_is_locked() to prevent sysjump on consumer systemsRandall Spangler2012-05-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | This returns true when both HW and SW write protect are enabled. Once WP is enabled, sysjump will be locked out. system_is_locked() can be used to gate other dangerous-ish commands too. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7468 TEST=manual sysinfo -> unlocked, copy A sysjump B -> works flashwp lock reboot (make sure flashinfo shows WP asserted and flash locked; note there is a HW bug on proto1 which makes this flaky) sysinfo -> locked, copy A sysjump B -> fails (remove WP screw) reboot hard flashwp unlock Change-Id: I849b573675c2c1cb4c44b9a05d6973e38247ca23
* Maintain timer value across sysjumps and clean up init debug outputRandall Spangler2012-05-111-9/+15
| | | | | | | | | | | This helps us keep track of how long vboot is taking on the EC. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9651 TEST=reboot system and look at debug log. time shouldn't start over after it jumps to image A. Change-Id: Iad86e90d42dabf1c67b2c2be80dda1151cf9a288
* Call timer_init() before other interrupts are initializedRandall Spangler2012-05-111-5/+7
| | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9647 TEST=hack code to put a uart_puts() immediately following uart_init() It shouldn't crash. Change-Id: Ia1867a631934dbd457a23183010fdf9f5c284873
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