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* Update license boilerplate text in source code filesstabilize-quickfix-15278.72.B-ishstabilize-quickfix-15183.78.B-ishstabilize-15446.B-ishstabilize-15439.B-ishstabilize-15432.B-ishstabilize-15429.B-ishstabilize-15415.B-ishstabilize-15395.B-ishstabilize-15393.48.B-ishstabilize-15381.B-ishstabilize-15364.B-ishstabilize-15361.B-ishstabilize-15359.B-ishstabilize-15359.58.B-ishstabilize-15359.50.B-ishstabilize-15359.45.B-ishstabilize-15335.B-ishstabilize-15329.59.B-ishstabilize-15329.44.B-ishstabilize-15317.B-ishstabilize-15301.B-ishstabilize-15300.B-ishstabilize-15278.64.B-ishstabilize-15251.B-ishstabilize-15245.B-ishstabilize-15236.66.B-ishstabilize-15208.B-ishstabilize-15207.B-ishstabilize-15185.B-ishstabilize-15185.7.B-ishstabilize-15183.82.B-ishstabilize-15183.69.B-ishstabilize-15183.14.B-ishstabilize-15174.B-ishstabilize-15167.B-ishstabilize-15129.B-ishstabilize-15122.B-ishstabilize-15120.B-ishstabilize-15117.86.B-ishstabilize-15117.48.B-ishstabilize-15117.111.B-ishrelease-R114-15437.B-ishrelease-R113-15393.B-ishrelease-R112-15359.B-ishrelease-R111-15329.B-ishrelease-R110-15278.B-ishrelease-R109-15237.B-ishrelease-R109-15236.B-ishrelease-R108-15183.B-ishrelease-R107-15117.B-ishishfirmware-ti50-prepvt-15315.B-ishfirmware-skyrim-15390.B-ishfirmware-skyrim-15369.B-ishfirmware-nissa-15217.B-ishfirmware-nissa-15217.45.B-ishfirmware-nissa-15217.126.B-ishfirmware-duplo-15151.B-ishfirmware-corsola-15194.B-ishfactory-trogdor-15210.B-ishfactory-skyrim-15384.B-ishfactory-nissa-15199.B-ishfactory-corsola-15197.B-ishfactory-corsola-15196.B-ishfactory-brya-15231.B-ishMike Frysinger2022-09-141-1/+1
| | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: I5b357b85ae9473a192b80983871bef4ae0d4b16f Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3893394 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cbi: Add CONFIG_EEPROM_CBI_WPAseda Aboagye2021-07-291-0/+9
| | | | | | | | | | | | | | | | | | | | | This commit adds the config option, CONFIG_EEPROM_CBI_WP. It is to be defined when the EC directly controls the CBI EEPROM WP signal. The EC will set the WP according to the result of `system_is_locked()`. Note that once the WP is set, the EC must be reset via EC_RST_ODL in order for the WP to become unset. This is enabled by the accompanying hardware. BUG=b:181769483 BRANCH=None TEST=`make -j buildall` Signed-off-by: Aseda Aboagye <aaboagye@google.com> Change-Id: If490594ab4dd24af98119b01299215b997913b66 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3046412 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* include/flash: rename the APIsTim Lin2021-06-091-1/+1
| | | | | | | | | | | | | | | | The names conflict when enabling both Zephyr's flash driver and CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h BUG=b:187192628 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* zephyr: Update banner to match Chromium OSKeith Short2021-04-231-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the boot banner to match Chromium OS. This also modifies the version output to include "_zephyr" after the board name to clearly identify the image type. Boot banner: Booting Zephyr OS build zephyr-v2.5.0-31-g6fcd6373e58a --- UART initialized after reboot --- [Image: RO, volteer_zephyr_v2.0.8350-190d6f 2021-04-08 11:15:09 keithshort@mtbaldy] [Reset cause: reset-pin] uart:~$ version Chip: Nuvoton NPCX796FC 02 Board: 1 RO: volteer_zephyr_v2.0.8350-190d6f RW: volteer_zephyr_v2.0.8350-190d6f Build: volteer_zephyr_v2.0.8350-190d6f 2021-04-08 11:15:09 keithshort@mtbaldy BUG=none BRANCH=none TEST=zmake testall Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: Ia136c4e025aba95217f1d8c51de39255fef54f7b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2822208 Commit-Queue: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* zephyr: Fix recovery modeKeith Short2021-03-161-1/+1
| | | | | | | | | | | | | | | | | | | The Zephyr initialization was missing a call to lpc_int_mask(), which caused the detected recovery event to be ignored. Add this call before keyboard_scan_init() to match Chromium EC initialization. Note - this requires CL:2731180 for recovery mode be detected correctly. BUG=b:182808955 BRANCH=none TEST=zmake testall TEST=Press recovery combo, verify depthcharge starts recovery mode. Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: If03a837208d6fc025aef1359e72c09fcf39b5656 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2760805 Commit-Queue: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* npcx/system: LCT compensate for MTC in PSL_hibernateWealian Liao2021-01-121-0/+4
| | | | | | | | | | | | | | | | | | | | | NPCX chip uses the MTC module as the RTC counter. However, in PSL hibernate, MTC will stop counting. NPCX9 supports the LCT module which could count continuously when VCC1 power is off. The CL uses LCT to compensate for the MTC counter value after PSL hibernate wake-up. The LCT maximum counting value is 16 weeks. BRANCH=none BUG=b:165777478, b:171919875 TEST=pass "make buildall" TEST=Check the RTC value in the following scenario: 1. "hibernate" and wake up EC by PSL input. 2. "hibernate 30" and wake up EC after timeout. 3. "hibernate 30" and wake up EC by PSL input before timeout. Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com> Change-Id: I39e370a437f40749acbd3a35a8b37ebec70f1bf2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2506864 Reviewed-by: Keith Short <keithshort@chromium.org>
* COIL: Rename CONFIG_I2C_CONTROLLERDiana Z2020-11-051-1/+1
| | | | | | | | | | | | | Rename CONFIG_I2C_CONTROLLER and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* PB: Clear AP_IDLE for recovery bootDaisuke Nojiri2020-06-171-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Currently, if CONFIG_POWER_BUTTON_INIT_IDLE is defined, EC_RESET_FLAG_AP_IDLE is set when the system enters S5. This is for restoring the power state after power loss or blackout. This can cause a recovery boot to be blocked depending on the timing that the hardware resets the EC. This patch makes EC clear AP_IDLE flag when a manual recovery request is detected so that AP can be unconditionally booted in the recovery mode. BUG=b:158802935, b:37536389 BRANCH=none TEST=Shutdown DUT. Press power + recovery. DUT enters recovery mode. TEST=Shutdown DUT. Replug AC. DUT stays off. TEST=Boot DUT to OS. Replug AC. DUT boots back to OS. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Iec1fd51cb0fa49e088f3b2489c5e94c8a4777a9b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2242664 Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* cortex-m: Init the MPU to check for correct operationAndrew McRae2020-05-271-2/+1
| | | | | | | | | | | | | | | | Disable all a MPU regions using the smallest supported size. BUG=chromium:1085868 TEST=Boot successfully on Puff TEST=Boot successfully on Volteer BRANCH=none Change-Id: Ie6924c3d9691ba6f4b218c9897b4e42b35b12bb7 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2212010 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
* MPU: Don't panic when mpu_pre_init failsDaisuke Nojiri2020-05-231-1/+2
| | | | | | | | | | | | | | This is a workaround for chromium:1085868. BUG=chromium:1085868 BRANCH=none TEST=Boot Puff. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Iea223bc992206d70f69b4789da3f9f009790df9e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213600 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* system: Print reset flags also on RW startDaisuke Nojiri2020-05-231-7/+7
| | | | | | | | | | | | | | | | Currently, only RO prints reset flags. Reset flags are passed from RO to RW and affect how RW behaves. This patch makes RW also print reset flags. BUG=none BRANCH=none TEST=Verify reset cause is printed after sysjump. TEST=Verify test_that suite:faft_bios passes. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I5b286d8d29603bbff7ad43f90798a2d6d911a572 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2211602 Reviewed-by: Sam Hurst <shurst@google.com>
* cortex-m: Clean up MPU logicTom Hughes2020-05-221-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add error checking for failures and use IS_ENABLED combined with helper functions for readability. BRANCH=none BUG=b:155229277, b:156501835 TEST=Compile and flash "rollback" test on dragonclaw with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 8020000" => PASS TEST=Compile and flash "rollback" test on dragonclaw with region 1 On console: "runtest" => Memory is successfully read => FAIL TEST=Compile and flash "rollback" test on dragontalon with region 0 On console: "runtest" => Reboots with "Data access violation, mfar = 80c0000" => PASS TEST=Compile and flash "rollback" on dragontalon with region 1 On console: "runtest" => Reboots with "Data access violation, mfar = 80e0000" => PASS Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I0f8d149c8c5c568241457a6779079c65eb38ce32 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2200199 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Fix comment typoTzung-Bi Shih2020-03-131-1/+1
| | | | | | | | | | | BUG=none TEST=make buildall BRANCH=none Change-Id: I1c75aa5050ccb21015d5feb0d93a09ed4f0430d9 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2099724 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* common/system: Unify ec_current_image and system_image_copy_tTom Hughes2020-02-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "enum ec_current_image" is exposed in ec_commands.h (and used by non-EC code, such as biod). We also have an "enum system_image_copy_t" that is the exact same thing (though has a few more definitions). A followup CL (I714b6bd8c0d7192386404c25a831e38438fa5238) adds the "sysinfo" host command, so we want to be able to expose all the potential image variants. Rather than maintain two enums that can potentially get out of sync, unify the code to use a single enum. We choose to keep the "enum ec_current_image", since external code depends on it. To verify that this change results in no changes to the generated binaries: ./util/compare_build.sh --board all BRANCH=none BUG=b:146447208 TEST=./util/compare_build.sh --board=all Change-Id: I13776bc3fd6e6ad635980476a35571c52b1767ac Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036599 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* EFS2: Implement Early Firmware Selection ver.2Daisuke Nojiri2020-02-091-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EFS v1 allowed Chromeboxes to verify RW without AP. EFS v2 will bring the benefts to Chromebooks, which are: - Reduce RO dependency and presence. Allow more code to be updated in the fields. - Remove jumptag and workarounds needed for late sysjump. Major imporvements over v1 are: - No A/B slot required. - No signature in RW or public key in RO. - Rollback-attack protection. - Verifies only RW being used instead of whole RW section. For battery-equipped devices, additional benefts are: - Immediate boot on drained battery. - Support recovery mode regardless of battery condition. - Faster charge in S5/G3. EC-Cr50 communication is based on the shared UART (go/ec-cr50-comm). EFS2 is documented in go/ec-efs2. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1045217,chromium:141143112 BRANCH=none TEST=Boot Helios in NORMAL/NO_BOOT/NO_BOOT_RECOVERY/RECOVERY mode. TEST=Wake up EC from hibernate. TEST=Make EC assert PACKET_MODE to wake up Cr50 from deepsleep. Change-Id: I98a4fe1ecc59d106810a75daec3c424f953ff880 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2015357 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* main: Initialize I2C pretty earlyAlexandru M Stan2019-10-241-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices (like the keyboard, CBI) need I2C access pretty early. Until now I2C would get initialized pretty late in a hook, which was far too late for some stuff. As a result from this change, CONFIG_I2C_MASTER now implies the i2c_init() function will be called at board boot. Some chips (cr50, host tests) needed a stub i2c_init in order to compile cleanly. BUG=b/138384267 TEST=EFS doesn't happen significantly later than it used to TEST=Recovery keys now work with I2C keyboard on jacuzzi TEST=make buildall TEST=Sanity check i2c behavior (booting, "i2scan", "battery") on a variety of ECs: * ampton (ite EC, x86 AP) * bobba (npcx EC, x86 AP) * jacuzzi (stm32f0 EC, ARM AP) * cheza (npcx EC, ARM AP) BRANCH=master Change-Id: Ifa830e8e509ff16b36b4dcc86617869b1cb86ac3 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1772490 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kukui_scp: support CONFIG_PRESERVE_LOGSYilun Lin2019-10-041-1/+2
| | | | | | | | | | | | | | | | | Enable CONFIG_PRESERVE_LOGS to gather more information when SCP is crashed. TEST=1. crash scp 2. restart scp 3. restart timberslide to ensure the logs are fetched 4. see that untransmitted logs are fetched into /var/log/cros_scp.log BUG=b:140220117 BRANCH=none Change-Id: I12635afa6c92fd8fa9cc889ce75999f855f18db0 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1833943 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-261-3/+3
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* log: Preserve Kukui EC reset logs across every EC reboot on SRAM.Shannon Chen2019-08-211-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | On Kukui, we need to put console logs and reset reasons at fixed addresses on SRAM to save the information across each EC resets. Otherwise, EC will lose console logs and reset reasons after resetting EC. This CL ensures that the contents of reset and console logs will not be clobbered or cleared by putting mandatory symbols at a fixed location on SRAM. The values will only be reset when checksum or sanity check fails. BUG=b:133795403 TEST=1. On Kukui, shutdown AP, reboot AP, or sysjump, and see the previous logs before reboot will be kept on /var/log/croc_ec.log 2. Reset reasons can be viewed with ectool uptimeinfo BRANCH=master Change-Id: I19db49101fda1675dc2fdc047b7f14af77cdb6e6 Signed-off-by: Shannon Chen <shannc@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1716671 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Shannon Chen <shannc@chromium.org> Tested-by: Shannon Chen <shannc@chromium.org>
* cleanup: remove CONFIG_REPLACE_LOADER_WITH_BSS_SLOWJack Rosenthal2019-07-311-9/+0
| | | | | | | | | | | | | | | | | | This option was only used with kunimitsu, which was removed from the EC codebase a long time ago. The EC code won't even compile with this option enabled anymore. Remove it! BUG=chromium:989301 BRANCH=none TEST=buildall Change-Id: I8ede226ec1e7b300ded6bb1769d82e142db1b0aa Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1727569 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core: Allow .bss and .data sections in DRAMNicolas Boichat2019-02-181-1/+10
| | | | | | | | | | | | | | | | | We manually copy other .data from the original section on boot, and clear DRAM .bss. This way, a single object file (or archive) can be moved fully to DRAM. BRANCH=none BUG=b:122058243 TEST=With next CL, dram_test works Change-Id: I1a434bbd8a4135d16b3f49b0d1b75b96506e3e24 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1445652 Reviewed-by: Jett Rink <jettrink@chromium.org>
* lpc/espi: convert remaning CONFIG_LPC to CONFIG_HOSTCMD_X86Jett Rink2018-05-221-1/+1
| | | | | | | | | | | | | | We have converted all LPC-only configs to HOSTCMD_LPC so the remaining CONFIG_LPC defines represent the common case. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Iba9a48f2cab12fadd0d9ab8eab0d5d5476eab238 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067503 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fizz: Execute PMIC reset before vboot_mainDaisuke Nojiri2018-02-081-0/+6
| | | | | | | | | | | | | | | | | | | When AP requests cold reboot, currently EC does not perform PMIC reset because chipset_handle_reboot is executed only after EC jumps to RW. This causes EC to miss CHIPSET_STARTUP and CHIPSET_RESUME events because power rails do not cycle. This patch will make EC execute PMIC reset to before vboot_main. BUG=b:73093795 BRANCH=none TEST=reboot, reboot ap-off, verify USB ports are powered after transitionining to dev mode. Change-Id: Ic04395d8a4bff45d9fc60601b07c600dfb75d9c0 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/908094 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Enable PD communication in RO for external displayDaisuke Nojiri2018-02-031-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | This patch makes EC enable PD communication if it's running in manual recovery mode. This is required to show recovery screen on a type-c monitor. This patch also makes EC-EFS ignore power availability. It will make EC verify & jump to RW even if power is sourced by a barrel jack adapter. This should allow depthcharge to show screens (e.g. broken, warning) on a type-c monitor. BUG=b:72387533 BRANCH=none TEST=On Fizz with type-c monitor, verify - Recovery screen is displayed in manual recovery mode. - Critical update screen is displayed in normal mode. - Warning screen is displayed in developer mode. Monitors tested: Dingdong, Dell S2718D Change-Id: Ib53e02d1e5c0f5b2d96d9a02fd33022f92e52b04 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/898346 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* buttons: Make buttons[] common.Aseda Aboagye2017-11-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Nearly every board had a buttons array defined in which its contents had the standard volume buttons. This commit creates a single common buttons array that can contain the standard volume buttons and recovery buttons. If a board has volume up and down buttons, they can simply define CONFIG_VOLUME_BUTTONS and it will populate the buttons array with the standard definition. The buttons are active low and have a 30 ms debounce period. Similiarly, if a board has a dedicated recovery button, defining CONFIG_DEDICATED_RECOVERY_BUTTON will also populate the buttons array with a recovery button. BUG=chromium:783371 BRANCH=None TEST=make -j buildall. TEST=Flash a device with CONFIG_VOLUME_BUTTONS, verify pressing volume buttons still work. Change-Id: Ie5d63670ca4c6b146ec8ffb64d40ea9ce437b913 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/773794 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* host_event: Perform lpc_init_mask before keyboard/button initFurquan Shaikh2017-10-241-0/+11
| | | | | | | | | | | | | | | | | | | | | | keyboard/button init are responsible for checking if user requested manual recovery. However, by this time, hook init is not run and hence host event set operation for manual recovery is dropped. This change adds a call to lpc_init_mask before keyboard/button init operations are performed. BUG=b:68189465 BRANCH=None TEST=Verified that manual recovery works fine. Recovery using software command works too: reboot ap-off hostevent set 0x4000 powerb Change-Id: I15cb648d4b253a523293c7ab2cd3e8e08e31a763 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/735799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Remove 'ryu' boardShawn Nematbakhsh2017-09-111-10/+0
| | | | | | | | | | | | | | | Remove 'ryu' and related ryu-only code. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: I19b966ea6964a7ed083724f7de80ae192235a406 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/656314 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Remove jtag_pre_init()Shawn Nematbakhsh2017-09-071-3/+0
| | | | | | | | | | | | | | | Use our newly-created chip_pre_init() for doing JTAG initialization. BUG=chromium:747629 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic5771895a214a9f1aa9bd289eef576f52adf973f Reviewed-on: https://chromium-review.googlesource.com/629676 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* EFS: Rename CONFIG_VBOOT_EC to _EFSDaisuke Nojiri2017-08-291-4/+3
| | | | | | | | | | | | | | This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: Move chip pre-init to chip_pre_init()Randall Spangler2017-08-241-0/+4
| | | | | | | | | | | | | | | | | | | | Currently, chip/g uses jtag_pre_init() to do some chip pre-initialization that isn't actually related to JTAG. This has been harmless, but it's currently the only chip which actually does "JTAG" pre-init, and we'd like to get rid of that. So, move that functionality to a new optional chip_pre_init() function. BUG=chromium:747629 BRANCH=cr50 TEST=make buildall boot cr50 make all dis; confirm chip_pre_init() is called early in <main> Change-Id: I3cae0747ab0c3cc974fce9f108947207b38e035f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/629876 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* g: slightly optimize boot on USB resumeVincent Palatin2017-08-021-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | Save a small amount of time when the USB resume is making the chip boot from deep-sleep by removing the verbose serial traces in main and increasing the usb initialization priority. This brings us from borderline timings wrt the USB specification to a reasonable margin. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:38160821 TEST=run on hotelgolf, go to deep-sleep on USB-suspend. On USB resume, measure the time from CPU boot to the end of usb_init using the CPU cycle count. We are shaving 1.3ms. Change-Id: Ia5bf69c0ca26748dec59a87f3908a5fe68296b36 Reviewed-on: https://chromium-review.googlesource.com/563206 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* vboot: Add vboot for EC by ECDaisuke Nojiri2017-06-281-0/+2
| | | | | | | | | | | | | | | | | This patch adds vboot for EC by EC (vboot EC) for x86 systems. When ec is transitioning s5->s3, it checks the power supply is enough to boot AP or not. If not, it runs other checks and may finally validate and jump to a RW image. BUG=b:38462249 BRANCH=none TEST=Boot Fizz on barrel jack and type-c charger. Change-Id: I5988b0595976370c5303c45541702ae89d86fc97 Reviewed-on: https://chromium-review.googlesource.com/518254 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* rwsig: do not jump if reset source is hard pin resetWei-Ning Huang2017-04-271-3/+15
| | | | | | | | | | | | | | | | | | | According to the new MCU secure update model, EC should wait for host if reset source is reset-pin. BRANCH=none BUG=b:37584134 TEST=on rose, toggle reset pin from host. EC should stay in RO, showing [0.426089 Hard pin-reset detected, disable RW jump] in console. Change-Id: Ie1908cb0744773e2e3ca8b3d8c627b8a9ef4567f Reviewed-on: https://chromium-review.googlesource.com/485199 Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org> Tested-by: Wei-Ning Huang <wnhuang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* rwsig: Make it possible to run as a taskNicolas Boichat2017-04-111-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | (Optionally) split rwsig verification into a separate task. This allows us to initialize other components (e.g. USB) while the verification is in progress, speeding up the boot process to active USB in RO case. After CONFIG_RWSIG_JUMP_TIMEOUT, the EC will jump to the RW section if no action is taken by the AP (such as a forced request to jump to RW, or starting an update). Note: This comes with a ~36ms boot time regression, as other code gets to run before verification starts. BRANCH=none BUG=b:35587171 TEST=Flash, board boots to RW after 1s TEST=Change jump timeout to 5s, add 5s delay in check_signature, add console command to manually abort/continue rwsig verification. 'rwsig continue' works => Board jumps to RW after check_signature is completed (or immediately while waiting for timeout) 'rwsig abort' works => Board does not jump to RW. Change-Id: Ica5732b9298bb4d3b743cae2ba78df259db915ef Reviewed-on: https://chromium-review.googlesource.com/468709 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* common: Split rwsig parts from rsa.h headerNicolas Boichat2017-04-111-1/+1
| | | | | | | | | | | | | | | | We're going to add more rwsig-related functions, and adding them to rsa.h seems increasingly incorrect. BRANCH=none BUG=b:35587171 TEST=make buildall -j Change-Id: I334c1774ce9a6ed8e219140f65ebe94d653e22d2 Reviewed-on: https://chromium-review.googlesource.com/468708 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* button: Check volume up/down status and set recovery modeNicolas Boichat2017-01-201-0/+4
| | | | | | | | | | | | | | Add support for entering recovery mode using volume up/down keys. BRANCH=none BUG=chrome-os-partner:61930 TEST=Press Power+Volume Up+Volume Down, poppy enters recovery Change-Id: Id40a144e9b430cfb9dfd47048e9e96d598bc3db8 Reviewed-on: https://chromium-review.googlesource.com/428530 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix various misspellings in commentsMartin Roth2016-11-151-1/+1
| | | | | | | | | | | | | No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* g: CONFIG_FLASH should be optionalBill Richardson2016-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The application may need to read/write/erase the flash memory, but we not want console users to do so. This CL adds CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH to be undefined while still providing the chip-specific flash_physical_* accessor functions. There aren't many board.h files that needed changes, since CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH. BUG=chrome-os-partner:57408 BRANCH=none TEST=make buildall; try on Gru with and without CR50_DEV=1 See that it still boots, updates, wipes, restores, etc. without linking common/flash.o in the production image; and that the flash commands are still there in the dev build. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93 Reviewed-on: https://chromium-review.googlesource.com/391188 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: enable case closed debugMary Ruthven2016-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds a ccd console command to control the usb endpoints. The uart console command is moved into this command so 'ccd uart [enable|disable]' controls the AP and EC TX signals instead of the 'uart' console command. CCD can be enabled using 'ccd enable'. This switches the PHY used by the USB controller to be the external PHY. Changing the PHY exposes the cr50, AP, and EC consoles as well as the upgrading mechanisms for the AP, EC and cr50. The AP and EC consoles will be read only until 'ccd uart enable' is called. Cr50 can be updated using the usb upgrade endpoint. The EC and AP can be updated using the USB SPI endpoint. When CCD is disabled the usb controller will switch to using the AP PHY. None of the endpoints will be visible to the host. The USB SPI endpoint can be used to flash the EC or AP using 'flashrom -p raiden_debug_spi:target=[AP|EC]'. If CCD is not enabled running flashrom using the raiden_debug_spi programmer will fail. Cr50 will not forward the commands to the external AP or EC ROM, so flashrom will not be able to find the chip. The UART TX signals are now controlled by the 'ccd uart' console command instead of the 'uart' console command. The UART TX is enabled separately from CCD, because we want to be able to enable CCD while servo is connected, and having the cr50 UART TX pins wired directly to the Servo TX lines could damage both devices. The AP and EC consoles are be read only until 'ccd uart enable' is called. 'ccd uart disable' disconnects the AP and EC TX pins from the UART peripheral. When RDD becomes reliable on cr50, ccd_set_mode will select the PHY being used by the g chip USB controller. BUG=chrome-os-partner:49960,chrome-os-partner:52281 BRANCH=none TEST=manual TEST SERVO power cycle the DUT connect servo and check that the AP and EC consoles still work check that both the AP and EC can be flashed using servo. TEST SUZY Q Attach Suzy Q Connect to the all three consoles. Check that the cr50 console is in read-write mode and the EC and AP consoles are read only. Attach Servo. Verify all of the servo functionality described above still works with suzy q attached and ccd enabled. Disconnect Servo. run 'ccd uart enable' on the cr50 console and check both the AP and EC consoles can be written to. Check that the AP and EC can be programmed using the raiden_debug_spi programmer. Change-Id: I96db2a72fc95086871c9e4c778c19ebd01efb851 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342563
* system: Add support to reclaim space from loader.Aseda Aboagye2015-10-131-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Certain ECs which cannot load both the RO and RW images into memory simultaneously have a little firmware (LFW) loader that is loaded into the beginning of the program memory. This loader is responsible for loading the RO/RW images, however once we begin executing code from main(), the loader has already completed it's purpose. We can reuse this space by allocating portions of the .bss section here. This currently saves us 3k for mec1322. This section is .bss.slow. To use this feature simply define the following config option in board.h. #define CONFIG_REPLACE_LOADER_WITH_BSS_SLOW In some cases, such as the mec1322, this region of RAM is optimized for code and not data. Therefore, ideally infrequently used data should go into this region. BUG=chrome-os-partner:46056 BUG=chrome-os-partner:46063 BRANCH=None TEST=Flash GLaDOS; sysjump rw; Verify that we are in rw; sysjump ro; Verify we are back in ro. TEST=Build GLaDOS, check output memory map for LDR_REGION and .bss.slow section. TEST=make -j buildall tests Change-Id: I5b95cacc211278cf780a857b5a2ecfc1a0a28c45 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305254 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* eoption: Remove unused eeprom option storage codeAnton Staaf2015-09-081-4/+0
| | | | | | | | | | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I2174a904df160d19d47f1aa2d053349356cb4291 Reviewed-on: https://chromium-review.googlesource.com/297805 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hooks: Move HOOK_INIT to after task switching.Aseda Aboagye2015-07-131-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | This commit changes the way in which tasks are started. Instead of having all tasks marked as ready to run upon initialization, only the hooks task is marked as ready to run. HOOK_INITs are now run at the beginning of the hooks task. After the HOOK_INITs, the hooks task calls back to enable the rest of the tasks, reschedules, and proceeds as usual. This also allows the removal of checks for task_start_called(). BUG=chrome-os-partner:27226 BRANCH=None TEST=Built and flash EC image for samus and verified that EC boot was successful as well as AP boot. Additionally, verified that charging, keyboard, tap-for-battery were all still functional. TEST=make -j buildall tests Change-Id: Iea53670222c803c2985e9c86c96974386888a4fe Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/283657 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* Add option to enable GCC LTOVincent Palatin2015-05-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | Add CONFIG_LTO to use GCC Link-Time Optimizations to try to reduce the flash footprint of the firmware. Add additional protection to some functions/data to avoid removal by the linker when their usage is not obvious. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=make buildall (with and without LTO enable on all boards) Change-Id: I586b8c1eda4592b416c85383b65153c1d5ab0059 Reviewed-on: https://chromium-review.googlesource.com/271291 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* CCD: Switch PD_NO_DEBUG logic to use system_is_lockedAnton Staaf2015-04-131-10/+5
| | | | | | | | | | | | | | | | | | | | The system_is_locked function encompases the required checks for asserting PD_NO_DEBUG. It also supports forcing a system to be unlocked at build time, as well as handling systems without flash. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I676acb5a2ae169f9739a19910a760706f69f5b7b Reviewed-on: https://chromium-review.googlesource.com/265463 Trybot-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org>
* Ryu: Add PD_NO_DEBUG logicAnton Staaf2015-04-131-0/+15
| | | | | | | | | | | | | | | Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=chromium:470299 TEST=make buildall -j Change-Id: I79f831c8a0b581561472470986b86c77b7f824a1 Reviewed-on: https://chromium-review.googlesource.com/264796 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Commit-Queue: Anton Staaf <robotboy@chromium.org> Trybot-Ready: Anton Staaf <robotboy@chromium.org>
* Add RW firmware signature verification for common runtimeVincent Palatin2014-12-011-0/+9
| | | | | | | | | | | | | | | | | | For accessories without software-sync mechanism, add the option to do a RSA-based signature verification of the Read-Write firmware. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:31192 TEST=enable the configuration on Fruitpie and see the RW firmware validated and jump to. Tried with good and bad RW images. Change-Id: I3c886c2cbe17ca9543e19bf8599061c3f9751d4f Reviewed-on: https://chromium-review.googlesource.com/229594 Reviewed-by: Todd Broch <tbroch@chromium.org> Commit-Queue: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org>
* Add CONFIG_BRINGUP option to help debug signals for bringupBill Richardson2014-06-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When this option is configured, two changes take place. First, the AP doesn't power on by default when the EC reboots. To boot it, you can run the "powerbtn" command, or poke the power button manually, or any of the normal things. Second, we watch for power-related signal changes (anything that's connected to the power_signal_interrupt() function) and keep track of them as they happen. After a second with no further changes, we print the time and value of each change. For example: [19.939212 Port 80: 0x29] [19.967971 HC 0x23] [19.976236 Port 80: 0x3a] [19.995700 HC 0x87] [20.567884 Port 80: 0x73] 11 signal changes: 19.638241 +0.000000 PCH_SLP_SUS_L => 1 19.654378 +0.016137 PCH_SLP_S5_L => 1 19.654457 +0.000079 PCH_SLP_A_L => 1 19.654535 +0.000078 PCH_SLP_S3_L => 1 19.654587 +0.000052 PCH_SLP_S4_L => 1 19.659630 +0.005043 PGOOD_1_5V_DDR => 1 19.663199 +0.003569 PGOOD_1_5V_PCH => 1 19.664751 +0.001552 PGOOD_1_8VS => 1 19.668735 +0.003984 PGOOD_VCCP => 1 19.671883 +0.003148 PGOOD_VCCSA => 1 19.868406 +0.196523 PGOOD_CPU_CORE => 1 [21.908551 Port 80: 0xf0] [21.908855 HC 0x48] BUG=none BRANCH=ToT TEST=manual Build with CONFIG_BRINGUP, notice those two changes. Change-Id: I55fd2021a0eae7dbfd1aaf5d93971f65bf2367b9 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/202574 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Add cprints() and ccprints()Vic Yang2014-05-211-2/+3
| | | | | | | | | | | | | | | | | | | | | Our code base contains a lot of debug messages in this pattern: CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n") The strings are taking up spaces in the EC binaries, so let's refactor this by adding cprints() and ccprints(). cprints() is just like cprintf(), except that it adds the brackets and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...) This saves us hundreds of bytes in EC binaries. BUG=chromium:374575 TEST=Build and check flash size BRANCH=None Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200490 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Initalize DMA before UARTRandall Spangler2013-09-101-0/+6
| | | | | | | | | | | | | | This is in preparation for enabling DMA-based UART transfers, to improve UART performance on STM32. BUG=chrome-os-partner:20485 BRANCH=none TEST=Boot pit. Host commands should still be received; this verifies DMA is still operational. Change-Id: Ibc3b2e2cd187547eb61b85e4a086704accd7f2fb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/168810
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