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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-707/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* mchp: Optimize spi_flash_read() APImartin yan2021-08-061-1/+1
| | | | | | | | | | | | | | | | | | Optimize SPI flash read timing, MEC172x QMSPI controller controls CS# by hardware, it will add several system clock cycles delay between CS deassertion to CS assertion at the start of the next transaction, this guarantees SPI back to back transactions, so 1ms delay can be removed to optimze timing. BUG=none BRANCH=none TEST=Tested on ADL RVP and MCHP1727 MECC system via FAFT ECBootTime job save 720ms as EC performs 180KB RW code's SHA256 hash computation Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: I5cf9c668efb1cd008b91cdd8aa09f7351c017af0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074767 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* include/flash: rename the APIsTim Lin2021-06-091-1/+2
| | | | | | | | | | | | | | | | The names conflict when enabling both Zephyr's flash driver and CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h BUG=b:187192628 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* spi: Pass in spi_device as argument to spi_enable instead of portTom Hughes2021-01-281-7/+8
| | | | | | | | | | | | | | | | | | | | | | Rather than passing in the port and iterating over the global spi_devices variable, pass in the specific spi_device that is being enabled/disabled. The spi_device_t struct has the port. This change makes the functions in spi.h more consistent since they now all take a spi_device_t*. This change is the first step in making the SPI configuration more dynamic. BRANCH=none BUG=b:177908650 TEST=git grep 'spi_enable(CONFIG' => no results TEST=make buildall TEST=Flash dragonclaw v0.2 and view console to verify FP sensor ID Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I64124e0ebcf898e88496acb77703b5f59ae931c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2654081 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-151-6/+8
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* host_command: Change host command return value to enum ec_statusTom Hughes2019-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the host command handler callback function returns an int, it's easy to accidentally mix up the enum ec_error_list and enum ec_status types. The host commands always expect an enum ec_status type, so we change the return value to be of that explicit type. Compilation will then fail if you accidentally try to return an enum ec_error_list value. Ran the following commands and then manually fixed up a few remaining instances that were not caught: git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\ static enum ec_status \1(struct host_cmd_handler_args \*args)##' git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\ enum ec_status \1(struct host_cmd_handler_args \*args)##' BRANCH=none BUG=chromium:1004831 TEST=make buildall -j Cq-Depend: chrome-internal:1872675 Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common/spi_flash: don't mix up unsigned and signed typesPatrick Georgi2018-08-011-6/+6
| | | | | | | | | | Change-Id: Ib06fd16ddbe6455b0f194ee4b6c6f1c1bc8f3adc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Found-by: Coverity Scan #142081, #142083 Reviewed-on: https://chromium-review.googlesource.com/1158505 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* flash: Fix offset bug in spi_flash_readscott worley2018-05-181-5/+5
| | | | | | | | | | | | | | | | | | | | | Observed VBOOT hash failure for EC_RW. Function spi_flash_read with size > SPI_FLASH_MAX_READ_LEN is incorrectly incrementing the offset. For example: 0, 0x100, 0x300, 0x600, all with read size = 256. BUG= BRANCH=any EC using SPI flash TEST=Trigger VBOOT hash re-calculation using EC console hash rw command. Second test program SPI flash with known test pattern longer than SPI_FLASH_MAX_READ_LEN and read using EC console flashread. Change-Id: I5fda47f132f64b12044b94663a19d889f1c2b32a Reviewed-on: https://chromium-review.googlesource.com/1036258 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Shuffle const aroundPatrick Georgi2018-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | gcc 8.1 complains about duplicate const, and while some of these really are duplicate, others look like they were supposed to tighten the API contract so that variables are "const pointer to const data", but didn't have that effect. BUG=b:65441143 BRANCH=none TEST=building Chrome EC as part of upstream coreboot's build with a gcc 8.1 compiler now works (better. there are other issues left) Change-Id: I6016c5f282516471746f08d5714ea07ebdd10331 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1039812 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Enable spi_flash_read to read > SPI_FLASH_MAX_READ_SIZEphilipchen2016-10-051-9/+21
| | | | | | | | | | | | BUG=chromium:542789 BRANCH=none TEST=make buildall Change-Id: I55bf5bdb09b10be1c522ea4d843690abcc45abb2 Reviewed-on: https://chromium-review.googlesource.com/391867 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* flash: Add command to get SPI flash chip infoRandall Spangler2016-09-231-29/+50
| | | | | | | | | | | | | | | | | | | Previously, there was no way to identify which flash chip was used by the EC, for ECs using an external SPI flash. Now, 'ectool flashinfo' will print more information about the SPI flash chip in these cases. BUG=chrome-os-partner:56765 BRANCH=any EC with MEC1322 or NPCX still going through factory TEST=define CONFIG_HOSTCMD_FLASH_SPI_INFO, then 'ectool flashspiinfo' on samus indicates no SPI flash info, and prints additional info on chell and kevin. Without the config defined, all platforms report no spi flash info. CQ-DEPEND=CL:386368 Change-Id: I3c162f7ad12ed4b30ab951c03f24476683382114 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385702 Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-241-14/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* spi_flash: print spi flash size in proper unitNaresh G Solanki2016-03-301-1/+1
| | | | | | | | | | | | | Spi flash size is calculated in the units of kB but is printed as MB. correcting it to kB unit. Change-Id: If71681fc868a5974b44d135055c01f9184c71602 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332732 Commit-Ready: Naresh Solanki <naresh.solanki@intel.com> Tested-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
* spi_flash: Reload watchdog before writing a flash pageShamile Khan2016-03-251-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | When EC receives many flash write requests from host and PDCMD, CHARGE and USB_CHG_P0 tasks are all ready to run, the HOOK task may not get scheduled in time to pet the watchdog resulting in an EC reset. BUG=chrome-os-partner:51438 BRANCH=None TEST=Manual on lars, determine two EC versions that have enough differences so that replacing one image with the other will require all or most of the flash pages to be updated. Alternate between flashing the two images with flashrom using a script. Atleast 1000 iterations should pass. Change-Id: I8b5c8b680a2935b945f3740e371dee2d218ec4c5 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/334457 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit a537d1ac44c40e7f6e1131e8cc852b030ccdba52) Reviewed-on: https://chromium-review.googlesource.com/334903 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org>
* spi_flash: Reload watchdog after erasing each 32K blockShawn Nematbakhsh2016-03-021-0/+5
| | | | | | | | | | | | | | | | | A single erase host command may erase an arbitrarily large region of storage, which may lead to our watchdog firing. BUG=chrome-os-partner:50587 BRANCH=glados TEST=Manual on glados, flash RW EC / PD FW while plugging + unplugging zinger. Verify that watchdog doesn't fire. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I90dc85306aec43326c11c794861f68c6e12686e4 Reviewed-on: https://chromium-review.googlesource.com/329987 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Ensure flash operation has completed before returning.Shamile Khan2015-09-291-46/+8
| | | | | | | | | | | | | | | | | | | | | | | When flashrom performs a flash read following an erase and we do not wait in between for the erase to complete, we read 0x00 instead of 0xFF. Flashrom detects this and does not proceed further. Inserting a wait after erase solves this issue. Also added a wait following a flash write operation to preempt future issues, and moved spi_flash_wait() calls from Host Command APIs to lower level spi_flash_* functions. BUG=chrome-os-partner:43160 BRANCH=none TEST=Manually tested on Kunimitsu FAB3. flashrom -p ec -w ec.bin is successful Signed-off-by: Shamile Khan <shamile.khan@intel.com> Change-Id: I00925aa2da3709a6f3e73a40543b079112906e0a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/302683 Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Remove redundant FLASH_SIZE CONFIGsShawn Nematbakhsh2015-09-161-6/+6
| | | | | | | | | | | | | | | | | | | | Since there is no more concept of a flash region belonging only to the EC, we only need one FLASH_SIZE config, which represents the actual physical size of flash. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6 Reviewed-on: https://chromium-review.googlesource.com/297824 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: change interface to SPI flashGwendal Grignou2015-07-301-17/+20
| | | | | | | | | | | | | | | | Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
* cyan: fix issues with write protectionAndrey Petrov2015-07-161-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Fixes cyan/board.h to use correct SPI part * Adds new flash protection regions in spi_flash_reg.c * Sets SRP register in flash_physical_protect_at_boot() * Fixes a bug in COMPARE_BIT macro * Makes spi_flash_set_status() fail only when both HW pin is asserted AND SRP(s) are set * Makes sure set_flash_set_status() completes before returning BUG=chrome-os-partner:40908 BRANCH=master TEST=on Cyan: With WP pin de-asserted: flashrom -p ec --wp-enable flashrom -p ec --wp-status, make sure it is enabled flashrom -p ec --wp-disable flashrom -p ec --status, make sure it is disabled flashrom -p ec --wp-enable Assert WP pin (either with screwdriver or dut-control) flashrom -p ec --wp-disable make sure it failed Change-Id: I338cc906b73e723fdbb37f7c2fd0c4da358b6c8e Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/276671 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* spi/mec1322: Ensure that SPI Flash write chunks do not crossShamile Khan2015-06-121-13/+32
| | | | | | | | | | | | | | | | | | | | | | Page Boundary. If SPI Flash write is at an offset within the page and the length is greater than remainder of the page, the Flash page gets corrupted as addressing wraps to the beginning of page and previously written data gets overwritten. This change splits SPI Flash writes in such cases into two operations in different pages. BUG=None BRANCH=None TEST=During Software Sync, Depthcharge sends Flash write chunks that cross page boundary. With this change, the RW parition does not get corrupted. This can be confirmed by executing a successful "sysjump RW" after a Software Sync. Change-Id: I46349eea0d8e927353de7cb55a61e9960291adb6 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/275760 Reviewed-by: Shawn N <shawnn@chromium.org>
* spi_flash: Rework protection translation functionsShawn Nematbakhsh2015-03-171-236/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we defined separate functions to map registers to protect ranges for each supported SPI ROM. This change instead adds a protect range table + flags for each supported SPI ROM and adds common functions for translation between ranges + registers. This makes supporting new parts easier. Since we will never use most supported protection ranges, we can even simplfy the tables. The implementation is now similar to flashrom. BUG=chrome-os-partner:37688 TEST=Manual on Glower. flashwp disable + spi_flash_rsr --> 0 flashinfo --> shows no protection spi_flash_prot 0 0x10000 + spi_flash_rsr --> 0x24 flashinfo --> shows 64KB protected spi_flash_prot 0 0x20000 + spi_flash_rsr --> 0x28 flashinfo --> shows all 96KB protected spi_flash_prot 0 0x40000 + spi_flash_rsr --> 0x2c spi_flash_prot 0 0x80000 + spi_flash_rsr --> 0x10 spi_flash_prot 0 0 + spi_flash_rsr --> 0x00 spi_flash_prot 0 0x1000 --> error spi_flash_prot 0x10000 0x10000 --> error BRANCH=None Change-Id: Ie5908ce687b7ff207b09794c7b001a4fbd9e0f5a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/259310 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* spi_flash: Add protect support for W25X40Shawn Nematbakhsh2015-03-111-15/+104
| | | | | | | | | | | | | | | | W25X40 uses a different protection register encoding than our existing W25Q64 code. Move the SPI ROM option to a config, and add support for the new part. BUG=chrome-os-partner:37688 TEST=`make buildall -j`. W25X40 protection code tested in a subsequent commit. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Iaaeabf42c6c62c20debc91afd2cf8671c14244c8 Reviewed-on: https://chromium-review.googlesource.com/258440 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix errors discovered by new compiler.Bill Richardson2014-11-211-16/+0
| | | | | | | | | | | | | | The latest gcc picked up a couple out-of-bounds issues, so "make buildall" was failing. This fixes them. BUG=none BRANCH=ToT TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Idcd6a3358ecbb0e0d2a610e1cd28c2f138ce520b Reviewed-on: https://chromium-review.googlesource.com/231156 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Refactor STM32 SPI flash driverVic Yang2014-07-151-0/+841
This CL factors out the SPI flash driver to be a STM32-specific SPI master driver and a common SPI flash driver. BUG=None TEST=Verify on Fruitpie BRANCH=None Change-Id: I9cca918299bc57a6532c85c4452e73f04550a424 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/206582 Reviewed-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Daming Chen <ddchen@chromium.org> Tested-by: Daming Chen <ddchen@chromium.org>
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