| Commit message (Collapse) | Author | Age | Files | Lines |
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The Careena baseboard IMU principle axes are rotated relative to the
Grunt reference design for manufacturability. Also, refactor
common/spi_flash_reg.c to avoid a name collision with axis definitions
in math_util.
BRANCH=none
BUG=b:111983307
TEST=make -j buldall; Observe `accelread 1` output with the base in
orientations: flat, perturbed by rotation about +y, and perturbed by
rotation about +x.
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Change-Id: Ib85d657ef47a89aaa63134b2bdf43920caf6c06e
Reviewed-on: https://chromium-review.googlesource.com/1155628
Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
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- Correct two range checks in set_pwm_led_color(). The erroneous checks
allowed a real array out-of-bounds error accessible via the EC console.
Scope is limited to pre-release hardware that had enabled
CONFIG_CMD_LEDTEST.
- Correct comparisons of unsigned integers to a negative constant.
- Add an explicit /* fallthrough */ on an un-recognized deliberate
fallthrough.
TEST=make -j buildall
BUG=none
BRANCH=none
Change-Id: Ifc460427729ce597e945142f0256a1364b0a083e
Signed-off-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1145051
Reviewed-by: Edward Hill <ecgh@chromium.org>
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Add W25Q128 flash device support.
BRANCH=none
BUG=
TEST=Modify a board build for W25Q128 and check
SPI code sets flash security bits correctly.
Change-Id: I6173f4cf751f3fbf68af75983f44d357a0b954f6
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
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In order to support write-protect mechanism for the internal flash
of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by
controlling the WP_L pin of internal flash. During ec initialization
or any utilities related to access status registers, we'll protect them
if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we
only can unlock write protection of internal flash by rebooting ec.
This CL also includes:
1. Add protect_range array of npcx7's internal flash (W25Q80) for
write-protect mechanism.
2. Add bypass of bit 7 of DEVCNT.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series. (Besides gru)
Build poppy board and upload FW to platform. No issues found.
Passed flash write-protect checking on npcx796f evb.
Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/501727
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The lengths were previously specified as end offsets and were
thus off by 1.
Fortunately it seems these chips were never used with an EC where we
actually utilize this table. Still, it would be nice if we actually
tested this on real hardware to check that there aren't any other
silly errors.
BUG=none
BRANCH=none
TEST=needs testing
Signed off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: I0a5315808c756797940436a10cd4f6df7313ab8c
Reviewed-on: https://chromium-review.googlesource.com/400642
Commit-Ready: Dan Shi <dshi@google.com>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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This adds support for the GD25LQ40 NOR flash chip which is identical
to W25Q40 for the purposes of write-protection support for the ranges
that we care about.
BUG=chrome-os-partner:57015
BRANCH=none
TEST=needs testing
Change-Id: I09ad02e04fab4c539b9558180d73bf6c31da6aed
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/382641
Reviewed-by: Shawn N <shawnn@chromium.org>
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This removes write-protect ranges that are unnecessary so
that we save a bit of space.
BUG=chromium:633431
BRANCH=none
TEST=compiled only.
Change-Id: Ib34c6a125b001fc92a21f795ac3d922e77143342
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/365210
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BUG=chrome-os-partner:53035
BRANCH=none
TEST=needs testing
Change-Id: I4b2bc758a22c2c19ddf0438a2af26f8c76093081
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/339291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Since there is no more concept of a flash region belonging only to the
EC, we only need one FLASH_SIZE config, which represents the actual
physical size of flash.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6
Reviewed-on: https://chromium-review.googlesource.com/297824
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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MEC1322 use external spi rom. Now, we support W25X40 and W25Q64.
Celes will use GD25Q41B for external EC ROM.
So, we need to add define for GD25Q41B.
BUG=chrome-os-partner:45246
BRANCH=master
TEST=emerge-strago chromeos-ec
Change-Id: Idec79955306b2dd79027fa57afc15ed8474413e6
Signed-off-by: jongpil19.jung <jongpil19.jung@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/299576
Commit-Ready: Jongpil Jung <jongpil19.jung@samsung.com>
Tested-by: Jongpil Jung <jongpil19.jung@samsung.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
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* Fixes cyan/board.h to use correct SPI part
* Adds new flash protection regions in spi_flash_reg.c
* Sets SRP register in flash_physical_protect_at_boot()
* Fixes a bug in COMPARE_BIT macro
* Makes spi_flash_set_status() fail only when both HW pin is asserted
AND SRP(s) are set
* Makes sure set_flash_set_status() completes before returning
BUG=chrome-os-partner:40908
BRANCH=master
TEST=on Cyan:
With WP pin de-asserted:
flashrom -p ec --wp-enable
flashrom -p ec --wp-status, make sure it is enabled
flashrom -p ec --wp-disable
flashrom -p ec --status, make sure it is disabled
flashrom -p ec --wp-enable
Assert WP pin (either with screwdriver or dut-control)
flashrom -p ec --wp-disable
make sure it failed
Change-Id: I338cc906b73e723fdbb37f7c2fd0c4da358b6c8e
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/276671
Reviewed-by: Shawn N <shawnn@chromium.org>
Tested-by: Divya Jyothi <divya.jyothi@intel.com>
Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
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Previously we defined separate functions to map registers to protect
ranges for each supported SPI ROM. This change instead adds a protect range
table + flags for each supported SPI ROM and adds common functions for
translation between ranges + registers. This makes supporting new parts
easier. Since we will never use most supported protection ranges, we can
even simplfy the tables.
The implementation is now similar to flashrom.
BUG=chrome-os-partner:37688
TEST=Manual on Glower.
flashwp disable + spi_flash_rsr --> 0
flashinfo --> shows no protection
spi_flash_prot 0 0x10000 + spi_flash_rsr --> 0x24
flashinfo --> shows 64KB protected
spi_flash_prot 0 0x20000 + spi_flash_rsr --> 0x28
flashinfo --> shows all 96KB protected
spi_flash_prot 0 0x40000 + spi_flash_rsr --> 0x2c
spi_flash_prot 0 0x80000 + spi_flash_rsr --> 0x10
spi_flash_prot 0 0 + spi_flash_rsr --> 0x00
spi_flash_prot 0 0x1000 --> error
spi_flash_prot 0x10000 0x10000 --> error
BRANCH=None
Change-Id: Ie5908ce687b7ff207b09794c7b001a4fbd9e0f5a
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/259310
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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